mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next
- Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - Convert more clk bindings to YAML * clk-mobileye: clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: eyeq: add driver clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS flag dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings" * clk-twl: clk: twl: add TWL6030 support clk: twl: remove is_prepared * clk-nuvoton: clk: npcm8xx: add clock controller reset: npcm: register npcm8xx clock auxiliary bus device dt-bindings: reset: npcm: add clock properties * clk-renesas: clk: renesas: vbattb: Add VBATTB clock driver clk: Add devm_clk_hw_register_gate_parent_hw() clk: renesas: rzg2l: Fix FOUTPOSTDIV clk dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB clk: renesas: r9a08g045: Add power domain for RTC clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup() dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks clk: renesas: r9a09g057: Add clock and reset entries for ICU clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: Remove duplicate and trailing empty lines * clk-bindings: dt-bindings: clock: actions,owl-cmu: convert to YAML dt-bindings: clock: ti: Convert mux.txt to json-schema dt-bindings: clock: ti: Convert divider.txt to json-schema dt-bindings: clock: ti: Convert interface.txt to json-schema dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
This commit is contained in:
Stephen Boyd
@@ -1,52 +0,0 @@
|
||||
* Actions Semi Owl Clock Management Unit (CMU)
|
||||
|
||||
The Actions Semi Owl Clock Management Unit generates and supplies clock
|
||||
to various controllers within the SoC. The clock binding described here is
|
||||
applicable to S900, S700 and S500 SoC's.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be one of the following,
|
||||
"actions,s900-cmu"
|
||||
"actions,s700-cmu"
|
||||
"actions,s500-cmu"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- clocks: Reference to the parent clocks ("hosc", "losc")
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier, and client nodes can use this identifier
|
||||
to specify the clock which they consume.
|
||||
|
||||
All available clocks are defined as preprocessor macros in corresponding
|
||||
dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
|
||||
actions,s500-cmu.h header and can be used in device tree sources.
|
||||
|
||||
External clocks:
|
||||
|
||||
The hosc clock used as input for the plls is generated outside the SoC. It is
|
||||
expected that it is defined using standard clock bindings as "hosc".
|
||||
|
||||
Actions Semi S900 CMU also requires one more clock:
|
||||
- "losc" - internal low frequency oscillator
|
||||
|
||||
Example: Clock Management Unit node:
|
||||
|
||||
cmu: clock-controller@e0160000 {
|
||||
compatible = "actions,s900-cmu";
|
||||
reg = <0x0 0xe0160000 0x0 0x1000>;
|
||||
clocks = <&hosc>, <&losc>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes clock generated by the clock
|
||||
management unit:
|
||||
|
||||
uart: serial@e012a000 {
|
||||
compatible = "actions,s900-uart", "actions,owl-uart";
|
||||
reg = <0x0 0xe012a000 0x0 0x2000>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu CLK_UART5>;
|
||||
};
|
||||
@@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/actions,owl-cmu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Actions Semi Owl Clock Management Unit (CMU)
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description: |
|
||||
The Actions Semi Owl Clock Management Unit generates and supplies clock
|
||||
to various controllers within the SoC.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/actions,s500-cmu.h
|
||||
include/dt-bindings/clock/actions,s700-cmu.h
|
||||
include/dt-bindings/clock/actions,s900-cmu.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- actions,s500-cmu
|
||||
- actions,s700-cmu
|
||||
- actions,s900-cmu
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Host oscillator source
|
||||
- description: Internal low frequency oscillator source
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@e0160000 {
|
||||
compatible = "actions,s900-cmu";
|
||||
reg = <0xe0160000 0x1000>;
|
||||
clocks = <&hosc>, <&losc>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -1,51 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mobileye EyeQ5 clock controller
|
||||
|
||||
description:
|
||||
The EyeQ5 clock controller handles 10 read-only PLLs derived from the main
|
||||
crystal clock. It also exposes one divider clock, a child of one of the PLLs.
|
||||
Its registers live in a shared region called OLB.
|
||||
|
||||
maintainers:
|
||||
- Grégory Clement <gregory.clement@bootlin.com>
|
||||
- Théo Lebrun <theo.lebrun@bootlin.com>
|
||||
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mobileye,eyeq5-clk
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: plls
|
||||
- const: ospi
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
description:
|
||||
Input parent clock to all PLLs. Expected to be the main crystal.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
@@ -0,0 +1,84 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Battery Backup Function (VBATTB)
|
||||
|
||||
description:
|
||||
Renesas VBATTB is an always on powered module (backed by battery) which
|
||||
controls the RTC clock (VBATTCLK), tamper detection logic and a small
|
||||
general usage memory (128B).
|
||||
|
||||
maintainers:
|
||||
- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a08g045-vbattb
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: tamper detector interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: VBATTB module clock
|
||||
- description: RTC input clock (crystal or external clock device)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bclk
|
||||
- const: rtx
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: VBATTB module reset
|
||||
|
||||
quartz-load-femtofarads:
|
||||
description: load capacitance of the on board crystal
|
||||
enum: [ 4000, 7000, 9000, 12500 ]
|
||||
default: 4000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- power-domains
|
||||
- resets
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a08g045-cpg.h>
|
||||
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
clock-controller@1005c000 {
|
||||
compatible = "renesas,r9a08g045-vbattb";
|
||||
reg = <0x1005c000 0x1000>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
|
||||
clock-names = "bclk", "rtx";
|
||||
assigned-clocks = <&vbattb VBATTB_MUX>;
|
||||
assigned-clock-parents = <&vbattb VBATTB_XC>;
|
||||
#clock-cells = <1>;
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A08G045_VBAT_BRESETN>;
|
||||
quartz-load-femtofarads = <12500>;
|
||||
};
|
||||
@@ -1,58 +0,0 @@
|
||||
* Rockchip RK3328 Clock and Reset Unit
|
||||
|
||||
The RK3328 clock controller generates and supplies clock to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be "rockchip,rk3328-cru"
|
||||
- reg: physical base address of the controller and length of memory mapped
|
||||
region.
|
||||
- #clock-cells: should be 1.
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Optional Properties:
|
||||
|
||||
- rockchip,grf: phandle to the syscon managing the "general register files"
|
||||
If missing pll rates are not changeable, due to the missing pll lock status.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
|
||||
External clocks:
|
||||
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
- "hdmi_phy" - output clock of the hdmi phy pll - optional
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
cru: clock-controller@ff440000 {
|
||||
compatible = "rockchip,rk3328-cru";
|
||||
reg = <0x0 0xff440000 0x0 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart0: serial@ff120000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0xff120000 0x100>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&cru SCLK_UART0>;
|
||||
};
|
||||
@@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3328-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3328 Clock and Reset Unit (CRU)
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3328 clock controller generates and supplies clocks to various
|
||||
controllers within the SoC and also implements a reset controller for SoC
|
||||
peripherals.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be
|
||||
used in device tree sources. Similar macros exist for the reset sources in
|
||||
these files.
|
||||
There are several clocks that are generated outside the SoC. It is expected
|
||||
that they are defined using standard clock bindings with following
|
||||
clock-output-names:
|
||||
- "xin24m" - crystal input - required,
|
||||
- "clkin_i2s" - external I2S clock - optional,
|
||||
- "gmac_clkin" - external GMAC clock - optional
|
||||
- "phy_50m_out" - output clock of the pll in the mac phy
|
||||
- "hdmi_phy" - output clock of the hdmi phy pll - optional
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3328-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xin24m
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF),
|
||||
if missing pll rates are not changeable, due to the missing pll
|
||||
lock status.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@ff440000 {
|
||||
compatible = "rockchip,rk3328-cru";
|
||||
reg = <0xff440000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -16,8 +16,8 @@ merged to this clock. The component clocks shall be of one of the
|
||||
"ti,*composite*-clock" types.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/mux.txt
|
||||
[3] Documentation/devicetree/bindings/clock/ti/divider.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/ti,mux-clock.yaml
|
||||
[3] Documentation/devicetree/bindings/clock/ti/ti,divider-clock.yaml
|
||||
[4] Documentation/devicetree/bindings/clock/ti/gate.txt
|
||||
|
||||
Required properties:
|
||||
|
||||
@@ -1,115 +0,0 @@
|
||||
Binding for TI divider clock
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped adjustable clock rate divider that does not gate and has
|
||||
only one input clock or parent. By default the value programmed into
|
||||
the register is one less than the actual divisor value. E.g:
|
||||
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 3
|
||||
|
||||
This assumption may be modified by the following optional properties:
|
||||
|
||||
ti,index-starts-at-one - valid divisor values start at 1, not the default
|
||||
of 0. E.g:
|
||||
register value actual divisor value
|
||||
1 1
|
||||
2 2
|
||||
3 3
|
||||
|
||||
ti,index-power-of-two - valid divisor values are powers of two. E.g:
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 4
|
||||
|
||||
Additionally an array of valid dividers may be supplied like so:
|
||||
|
||||
ti,dividers = <4>, <8>, <0>, <16>;
|
||||
|
||||
Which will map the resulting values to a divisor table by their index:
|
||||
register value actual divisor value
|
||||
0 4
|
||||
1 8
|
||||
2 <invalid divisor, skipped>
|
||||
3 16
|
||||
|
||||
Any zero value in this array means the corresponding bit-value is invalid
|
||||
and must not be used.
|
||||
|
||||
The binding must also provide the register to control the divider and
|
||||
unless the divider array is provided, min and max dividers. Optionally
|
||||
the number of bits to shift that mask, if necessary. If the shift value
|
||||
is missing it is the same as supplying a zero shift.
|
||||
|
||||
This binding can also optionally provide support to the hardware autoidle
|
||||
feature, see [2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : offset for register controlling adjustable divider
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,dividers : array of integers defining divisors
|
||||
- ti,bit-shift : number of bits to shift the divider value, defaults to 0
|
||||
- ti,min-div : min divisor for dividing the input clock rate, only
|
||||
needed if the first divisor is offset from the default value (1)
|
||||
- ti,max-div : max divisor for dividing the input clock rate, only needed
|
||||
if ti,dividers is not defined.
|
||||
- ti,index-starts-at-one : valid divisor programming starts at 1, not zero,
|
||||
only valid if ti,dividers is not defined.
|
||||
- ti,index-power-of-two : valid divisor programming must be a power of two,
|
||||
only valid if ti,dividers is not defined.
|
||||
- ti,autoidle-shift : bit shift of the autoidle enable bit for the clock,
|
||||
see [2]
|
||||
- ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0,
|
||||
see [2]
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent
|
||||
- ti,latch-bit : latch the divider value to HW, only needed if the register
|
||||
access requires this. As an example dra76x DPLL_GMAC H14 divider implements
|
||||
such behavior.
|
||||
|
||||
Examples:
|
||||
dpll_usb_m2_ck: dpll_usb_m2_ck@4a008190 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_usb_ck>;
|
||||
ti,max-div = <127>;
|
||||
reg = <0x190>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
aess_fclk: aess_fclk@4a004528 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&abe_clk>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x528>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0134>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
@@ -1,55 +0,0 @@
|
||||
Binding for Texas Instruments interface clock.
|
||||
|
||||
This binding uses the common clock binding[1]. This clock is
|
||||
quite much similar to the basic gate-clock [2], however,
|
||||
it supports a number of additional features, including
|
||||
companion clock finding (match corresponding functional gate
|
||||
clock) and hardware autoidle enable / disable.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be one of:
|
||||
"ti,omap3-interface-clock" - basic OMAP3 interface clock
|
||||
"ti,omap3-no-wait-interface-clock" - interface clock which has no hardware
|
||||
capability for waiting clock to be ready
|
||||
"ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
|
||||
handling
|
||||
"ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
|
||||
"ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
|
||||
"ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
|
||||
"ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
|
||||
handling
|
||||
- #clock-cells : from common clock binding; shall be set to 0
|
||||
- clocks : link to phandle of parent clock
|
||||
- reg : base address for the control register
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : bit shift for the bit enabling/disabling the clock (default 0)
|
||||
|
||||
Examples:
|
||||
aes1_ick: aes1_ick@48004a14 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <0x48004a14 0x4>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
|
||||
cam_ick: cam_ick@48004f10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-no-wait-interface-clock";
|
||||
clocks = <&l4_ick>;
|
||||
reg = <0x48004f10 0x4>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
ssi_ick_3430es2: ssi_ick_3430es2@48004a10 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-ssi-interface-clock";
|
||||
clocks = <&ssi_l4_ick>;
|
||||
reg = <0x48004a10 0x4>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
@@ -1,78 +0,0 @@
|
||||
Binding for TI mux clock.
|
||||
|
||||
This binding uses the common clock binding[1]. It assumes a
|
||||
register-mapped multiplexer with multiple input clock signals or
|
||||
parents, one of which can be selected as output. This clock does not
|
||||
gate or adjust the parent rate via a divider or multiplier.
|
||||
|
||||
By default the "clocks" property lists the parents in the same order
|
||||
as they are programmed into the register. E.g:
|
||||
|
||||
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
|
||||
|
||||
results in programming the register as follows:
|
||||
|
||||
register value selected parent clock
|
||||
0 foo_clock
|
||||
1 bar_clock
|
||||
2 baz_clock
|
||||
|
||||
Some clock controller IPs do not allow a value of zero to be programmed
|
||||
into the register, instead indexing begins at 1. The optional property
|
||||
"index-starts-at-one" modified the scheme as follows:
|
||||
|
||||
register value selected clock parent
|
||||
1 foo_clock
|
||||
2 bar_clock
|
||||
3 baz_clock
|
||||
|
||||
The binding must provide the register to control the mux. Optionally
|
||||
the number of bits to shift the control field in the register can be
|
||||
supplied. If the shift value is missing it is the same as supplying
|
||||
a zero shift.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
|
||||
- #clock-cells : from common clock binding; shall be set to 0.
|
||||
- clocks : link phandles of parent clocks
|
||||
- reg : register offset for register controlling adjustable mux
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names : from common clock binding.
|
||||
- ti,bit-shift : number of bits to shift the bit-mask, defaults to
|
||||
0 if not present
|
||||
- ti,index-starts-at-one : valid input select programming starts at 1, not
|
||||
zero
|
||||
- ti,set-rate-parent : clk_set_rate is propagated to parent clock,
|
||||
not supported by the composite-mux-clock subtype
|
||||
- ti,latch-bit : latch the mux value to HW, only needed if the register
|
||||
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
|
||||
implements such behavior.
|
||||
|
||||
Examples:
|
||||
|
||||
sys_clkin_ck: sys_clkin_ck@4a306110 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
|
||||
reg = <0x0110>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@4a306108 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x0108>;
|
||||
};
|
||||
|
||||
mcbsp5_mux_fck: mcbsp5_mux_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-mux-clock";
|
||||
clocks = <&core_96m_fck>, <&mcbsp_clks>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x02d8>;
|
||||
};
|
||||
@@ -0,0 +1,193 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments divider clock
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
This clock It assumes a register-mapped adjustable clock rate divider
|
||||
that does not gate and has only one input clock or parent. By default the
|
||||
value programmed into the register is one less than the actual divisor value.
|
||||
E.g:
|
||||
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 3
|
||||
|
||||
This assumption may be modified by the following optional properties:
|
||||
|
||||
ti,index-starts-at-one - valid divisor values start at 1, not the default
|
||||
of 0. E.g:
|
||||
register value actual divisor value
|
||||
1 1
|
||||
2 2
|
||||
3 3
|
||||
|
||||
ti,index-power-of-two - valid divisor values are powers of two. E.g:
|
||||
register value actual divisor value
|
||||
0 1
|
||||
1 2
|
||||
2 4
|
||||
|
||||
Additionally an array of valid dividers may be supplied like so:
|
||||
|
||||
ti,dividers = <4>, <8>, <0>, <16>;
|
||||
|
||||
Which will map the resulting values to a divisor table by their index:
|
||||
register value actual divisor value
|
||||
0 4
|
||||
1 8
|
||||
2 <invalid divisor, skipped>
|
||||
3 16
|
||||
|
||||
Any zero value in this array means the corresponding bit-value is invalid
|
||||
and must not be used.
|
||||
|
||||
The binding must also provide the register to control the divider and
|
||||
unless the divider array is provided, min and max dividers. Optionally
|
||||
the number of bits to shift that mask, if necessary. If the shift value
|
||||
is missing it is the same as supplying a zero shift.
|
||||
|
||||
This binding can also optionally provide support to the hardware autoidle
|
||||
feature, see [1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/ti/autoidle.txt
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,divider-clock
|
||||
- ti,composite-divider-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ti,dividers:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
array of integers defining divisors
|
||||
|
||||
ti,bit-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
number of bits to shift the divider value
|
||||
maximum: 31
|
||||
default: 0
|
||||
|
||||
ti,min-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
min divisor for dividing the input clock rate, only
|
||||
needed if the first divisor is offset from the default value (1)
|
||||
minimum: 1
|
||||
default: 1
|
||||
|
||||
|
||||
ti,max-div:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
max divisor for dividing the input clock rate, only needed
|
||||
if ti,dividers is not defined.
|
||||
|
||||
ti,index-starts-at-one:
|
||||
type: boolean
|
||||
description:
|
||||
valid divisor programming starts at 1, not zero,
|
||||
only valid if ti,dividers is not defined
|
||||
|
||||
ti,index-power-of-two:
|
||||
type: boolean
|
||||
description:
|
||||
valid divisor programming must be a power of two,
|
||||
only valid if ti,dividers is not defined.
|
||||
|
||||
ti,autoidle-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
bit shift of the autoidle enable bit for the clock,
|
||||
see [1].
|
||||
maximum: 31
|
||||
default: 0
|
||||
|
||||
ti,invert-autoidle-bit:
|
||||
type: boolean
|
||||
description:
|
||||
autoidle is enabled by setting the bit to 0,
|
||||
see [1]
|
||||
|
||||
ti,set-rate-parent:
|
||||
type: boolean
|
||||
description:
|
||||
clk_set_rate is propagated to parent |
|
||||
|
||||
ti,latch-bit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
latch the divider value to HW, only needed if the register
|
||||
compatible access requires this. As an example dra76x DPLL_GMAC
|
||||
H14 divider implements such behavior.
|
||||
|
||||
dependentSchemas:
|
||||
ti,dividers:
|
||||
properties:
|
||||
ti,min-div: false
|
||||
ti,max-div: false
|
||||
ti,index-power-of-two: false
|
||||
ti,index-starts-at-one: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@190 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_usb_ck>;
|
||||
ti,max-div = <127>;
|
||||
reg = <0x190>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
clock-controller@528 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&abe_clk>;
|
||||
ti,bit-shift = <24>;
|
||||
reg = <0x528>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
clock-controller@a40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,composite-divider-clock";
|
||||
clocks = <&corex2_fck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x0a40>;
|
||||
ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,interface-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments interface clock.
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
This clock is quite much similar to the basic gate-clock[1], however,
|
||||
it supports a number of additional features, including
|
||||
companion clock finding (match corresponding functional gate
|
||||
clock) and hardware autoidle enable / disable.
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,omap3-interface-clock # basic OMAP3 interface clock
|
||||
- ti,omap3-no-wait-interface-clock # interface clock which has no hardware
|
||||
# capability for waiting clock to be ready
|
||||
- ti,omap3-hsotgusb-interface-clock # interface clock with USB specific HW handling
|
||||
- ti,omap3-dss-interface-clock # interface clock with DSS specific HW handling
|
||||
- ti,omap3-ssi-interface-clock # interface clock with SSI specific HW handling
|
||||
- ti,am35xx-interface-clock # interface clock with AM35xx specific HW handling
|
||||
- ti,omap2430-interface-clock # interface clock with OMAP2430 specific HW handling
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ti,bit-shift:
|
||||
description:
|
||||
bit shift for the bit enabling/disabling the clock
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
default: 0
|
||||
maximum: 31
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
aes1_ick: clock-controller@3 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&security_l4_ick2>;
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,125 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments mux clock
|
||||
|
||||
maintainers:
|
||||
- Tero Kristo <kristo@kernel.org>
|
||||
|
||||
description: |
|
||||
This clock assumes a register-mapped multiplexer with multiple inpt clock
|
||||
signals or parents, one of which can be selected as output. This clock does
|
||||
not gate or adjust the parent rate via a divider or multiplier.
|
||||
|
||||
By default the "clocks" property lists the parents in the same order
|
||||
as they are programmed into the register. E.g:
|
||||
|
||||
clocks = <&foo_clock>, <&bar_clock>, <&baz_clock>;
|
||||
|
||||
Results in programming the register as follows:
|
||||
|
||||
register value selected parent clock
|
||||
0 foo_clock
|
||||
1 bar_clock
|
||||
2 baz_clock
|
||||
|
||||
Some clock controller IPs do not allow a value of zero to be programmed
|
||||
into the register, instead indexing begins at 1. The optional property
|
||||
"index-starts-at-one" modified the scheme as follows:
|
||||
|
||||
register value selected clock parent
|
||||
1 foo_clock
|
||||
2 bar_clock
|
||||
3 baz_clock
|
||||
|
||||
The binding must provide the register to control the mux. Optionally
|
||||
the number of bits to shift the control field in the register can be
|
||||
supplied. If the shift value is missing it is the same as supplying
|
||||
a zero shift.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,mux-clock
|
||||
- ti,composite-mux-clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks: true
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
ti,bit-shift:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Number of bits to shift the bit-mask
|
||||
maximum: 31
|
||||
default: 0
|
||||
|
||||
ti,index-starts-at-one:
|
||||
type: boolean
|
||||
description:
|
||||
Valid input select programming starts at 1, not zero
|
||||
|
||||
ti,set-rate-parent:
|
||||
type: boolean
|
||||
description:
|
||||
clk_set_rate is propagated to parent clock,
|
||||
not supported by the composite-mux-clock subtype.
|
||||
|
||||
ti,latch-bit:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Latch the mux value to HW, only needed if the register
|
||||
access requires this. As an example, dra7x DPLL_GMAC H14 muxing
|
||||
implements such behavior.
|
||||
maximum: 31
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,composite-mux-clock
|
||||
then:
|
||||
properties:
|
||||
ti,set-rate-parent: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@110 {
|
||||
compatible = "ti,mux-clock";
|
||||
reg = <0x0110>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>;
|
||||
ti,index-starts-at-one;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
clock-controller@120 {
|
||||
compatible = "ti,composite-mux-clock";
|
||||
reg = <0x0120>;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&core_96m_fck>, <&mcbsp_clks>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
};
|
||||
@@ -21,6 +21,13 @@ properties:
|
||||
'#reset-cells':
|
||||
const: 2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: specify external 25MHz reference clock.
|
||||
|
||||
nuvoton,sysgcr:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: a phandle to access GCR registers.
|
||||
@@ -39,6 +46,17 @@ required:
|
||||
- '#reset-cells'
|
||||
- nuvoton,sysgcr
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nuvoton,npcm845-reset
|
||||
then:
|
||||
required:
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -41,9 +41,7 @@ properties:
|
||||
enum: [ 1, 2 ]
|
||||
|
||||
'#clock-cells':
|
||||
description:
|
||||
Cell is clock index. Optional if compatible has a single clock.
|
||||
enum: [ 0, 1 ]
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
@@ -312,26 +310,6 @@ allOf:
|
||||
properties:
|
||||
'#reset-cells': false
|
||||
|
||||
# Compatibles exposing a single clock.
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mobileye,eyeq6h-central-olb
|
||||
- mobileye,eyeq6h-east-olb
|
||||
- mobileye,eyeq6h-west-olb
|
||||
- mobileye,eyeq6h-ddr0-olb
|
||||
- mobileye,eyeq6h-ddr1-olb
|
||||
then:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
else:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
# Only EyeQ5 has pinctrl in OLB.
|
||||
- if:
|
||||
not:
|
||||
|
||||
+1
-1
@@ -1996,7 +1996,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-actions@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/actions.yaml
|
||||
F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt
|
||||
F: Documentation/devicetree/bindings/clock/actions,owl-cmu.yaml
|
||||
F: Documentation/devicetree/bindings/dma/owl-dma.yaml
|
||||
F: Documentation/devicetree/bindings/i2c/i2c-owl.yaml
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/actions,owl-sirq.yaml
|
||||
|
||||
+20
-1
@@ -226,6 +226,17 @@ config COMMON_CLK_EP93XX
|
||||
help
|
||||
This driver supports the SoC clocks on the Cirrus Logic ep93xx.
|
||||
|
||||
config COMMON_CLK_EYEQ
|
||||
bool "Clock driver for the Mobileye EyeQ platform"
|
||||
depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
|
||||
select AUXILIARY_BUS
|
||||
default MACH_EYEQ5 || MACH_EYEQ6H
|
||||
help
|
||||
This driver provides clocks found on Mobileye EyeQ5, EyeQ6L and Eye6H
|
||||
SoCs. Controllers live in shared register regions called OLB. Driver
|
||||
provides read-only PLLs, derived from the main crystal clock (which
|
||||
must be constant). It also exposes some divider clocks.
|
||||
|
||||
config COMMON_CLK_FSL_FLEXSPI
|
||||
tristate "Clock driver for FlexSPI on Layerscape SoCs"
|
||||
depends on ARCH_LAYERSCAPE || COMPILE_TEST
|
||||
@@ -291,7 +302,7 @@ config CLK_TWL
|
||||
help
|
||||
Enable support for controlling the clock resources on TWL family
|
||||
PMICs. These devices have some 32K clock outputs which can be
|
||||
controlled by software. For now, only the TWL6032 clocks are
|
||||
controlled by software. For now, the TWL6032 and TWL6030 clocks are
|
||||
supported.
|
||||
|
||||
config CLK_TWL6040
|
||||
@@ -342,6 +353,14 @@ config COMMON_CLK_LOCHNAGAR
|
||||
This driver supports the clocking features of the Cirrus Logic
|
||||
Lochnagar audio development board.
|
||||
|
||||
config COMMON_CLK_NPCM8XX
|
||||
tristate "Clock driver for the NPCM8XX SoC Family"
|
||||
depends on ARCH_NPCM || COMPILE_TEST
|
||||
help
|
||||
This driver supports the clocks on the Nuvoton BMC NPCM8XX SoC Family,
|
||||
all the clocks are initialized by the bootloader, so this driver
|
||||
allows only reading of current settings directly from the hardware.
|
||||
|
||||
config COMMON_CLK_LOONGSON2
|
||||
bool "Clock driver for Loongson-2 SoC"
|
||||
depends on LOONGARCH || COMPILE_TEST
|
||||
|
||||
@@ -56,6 +56,7 @@ obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o
|
||||
obj-$(CONFIG_COMMON_CLK_EP93XX) += clk-ep93xx.o
|
||||
obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o
|
||||
obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o
|
||||
obj-$(CONFIG_COMMON_CLK_EYEQ) += clk-eyeq.o
|
||||
obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
|
||||
obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
|
||||
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
|
||||
@@ -76,6 +77,7 @@ obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
|
||||
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
|
||||
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
|
||||
obj-$(CONFIG_ARCH_NPCM7XX) += clk-npcm7xx.o
|
||||
obj-$(CONFIG_COMMON_CLK_NPCM8XX) += clk-npcm8xx.o
|
||||
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
|
||||
obj-$(CONFIG_COMMON_CLK_PALMAS) += clk-palmas.o
|
||||
obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o
|
||||
|
||||
@@ -72,6 +72,8 @@ static unsigned int _get_maxdiv(const struct clk_div_table *table, u8 width,
|
||||
return clk_div_mask(width);
|
||||
if (flags & CLK_DIVIDER_POWER_OF_TWO)
|
||||
return 1 << clk_div_mask(width);
|
||||
if (flags & CLK_DIVIDER_EVEN_INTEGERS)
|
||||
return 2 * (clk_div_mask(width) + 1);
|
||||
if (table)
|
||||
return _get_table_maxdiv(table, width);
|
||||
return clk_div_mask(width) + 1;
|
||||
@@ -97,6 +99,8 @@ static unsigned int _get_div(const struct clk_div_table *table,
|
||||
return 1 << val;
|
||||
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
|
||||
return val ? val : clk_div_mask(width) + 1;
|
||||
if (flags & CLK_DIVIDER_EVEN_INTEGERS)
|
||||
return 2 * (val + 1);
|
||||
if (table)
|
||||
return _get_table_div(table, val);
|
||||
return val + 1;
|
||||
@@ -122,6 +126,8 @@ static unsigned int _get_val(const struct clk_div_table *table,
|
||||
return __ffs(div);
|
||||
if (flags & CLK_DIVIDER_MAX_AT_ZERO)
|
||||
return (div == clk_div_mask(width) + 1) ? 0 : div;
|
||||
if (flags & CLK_DIVIDER_EVEN_INTEGERS)
|
||||
return (div >> 1) - 1;
|
||||
if (table)
|
||||
return _get_table_val(table, div);
|
||||
return div - 1;
|
||||
@@ -538,7 +544,8 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
|
||||
struct device_node *np, const char *name,
|
||||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
unsigned long clk_divider_flags,
|
||||
const struct clk_div_table *table, spinlock_t *lock)
|
||||
{
|
||||
struct clk_divider *div;
|
||||
@@ -610,8 +617,8 @@ EXPORT_SYMBOL_GPL(__clk_hw_register_divider);
|
||||
struct clk *clk_register_divider_table(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
u8 clk_divider_flags, const struct clk_div_table *table,
|
||||
spinlock_t *lock)
|
||||
unsigned long clk_divider_flags,
|
||||
const struct clk_div_table *table, spinlock_t *lock)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
|
||||
@@ -664,7 +671,8 @@ struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
|
||||
struct device_node *np, const char *name,
|
||||
const char *parent_name, const struct clk_hw *parent_hw,
|
||||
const struct clk_parent_data *parent_data, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
unsigned long clk_divider_flags,
|
||||
const struct clk_div_table *table, spinlock_t *lock)
|
||||
{
|
||||
struct clk_hw **ptr, *hw;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user