mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'nand/for-7.1' into mtd/next
The main changes happened in the SunXi driver in order to support new versions of the Allwinner NAND controller. There are also some DT-binding improvements and cleanups. Finally a couple of actual fixes (Realtek ECC and Winbond SPI NAND), aside with the usual load of misc changes.
This commit is contained in:
Miquel Raynal
@@ -101,7 +101,7 @@ required:
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unevaluatedProperties: false
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allOf:
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- $ref: nand-controller.yaml
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- $ref: nand-controller-legacy.yaml
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- if:
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properties:
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@@ -10,22 +10,43 @@ maintainers:
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- Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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allOf:
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- $ref: nand-controller.yaml
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- $ref: nand-controller-legacy.yaml
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properties:
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compatible:
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oneOf:
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- const: fsl,imx27-nand
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- enum:
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- fsl,imx25-nand
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- fsl,imx27-nand
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- fsl,imx51-nand
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- fsl,imx53-nand
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- items:
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- enum:
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- fsl,imx35-nand
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- const: fsl,imx25-nand
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- items:
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- enum:
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- fsl,imx31-nand
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- const: fsl,imx27-nand
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reg:
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maxItems: 1
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minItems: 1
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items:
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- description: IP register space
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- description: Nand flash internal buffer space
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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dmas:
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maxItems: 1
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dma-names:
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items:
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- const: rx-tx
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required:
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- compatible
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- reg
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@@ -11,6 +11,7 @@ maintainers:
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allOf:
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- $ref: mtd.yaml#
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- $ref: nand-property.yaml
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description: |
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This file covers the generic description of a NAND chip. It implies that the
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@@ -22,51 +23,6 @@ properties:
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description:
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Contains the chip-select IDs.
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nand-ecc-engine:
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description: |
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A phandle on the hardware ECC engine if any. There are
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basically three possibilities:
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1/ The ECC engine is part of the NAND controller, in this
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case the phandle should reference the parent node.
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2/ The ECC engine is part of the NAND part (on-die), in this
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case the phandle should reference the node itself.
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3/ The ECC engine is external, in this case the phandle should
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reference the specific ECC engine node.
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$ref: /schemas/types.yaml#/definitions/phandle
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nand-use-soft-ecc-engine:
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description: Use a software ECC engine.
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type: boolean
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nand-no-ecc-engine:
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description: Do not use any ECC correction.
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type: boolean
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nand-ecc-algo:
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description:
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Desired ECC algorithm.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [hamming, bch, rs]
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nand-ecc-strength:
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description:
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Maximum number of bits that can be corrected per ECC step.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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nand-ecc-step-size:
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description:
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Number of data bytes covered by a single ECC step.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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secure-regions:
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description:
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Regions in the NAND chip which are protected using a secure element
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like Trustzone. This property contains the start address and size of
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the secure regions present.
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$ref: /schemas/types.yaml#/definitions/uint64-matrix
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required:
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- reg
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@@ -0,0 +1,65 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/nand-controller-legacy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NAND Controller Common Properties
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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- Richard Weinberger <richard@nod.at>
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description: >
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The NAND controller should be represented with its own DT node, and
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all NAND chips attached to this controller should be defined as
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children nodes of the NAND controller. This representation should be
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enforced even for simple controllers supporting only one chip.
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This is only for legacy nand controller, new controller should use
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nand-controller.yaml
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properties:
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"#address-cells":
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const: 1
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"#size-cells":
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enum: [0, 1]
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ranges: true
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cs-gpios:
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description:
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Array of chip-select available to the controller. The first
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entries are a 1:1 mapping of the available chip-select on the
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NAND controller (even if they are not used). As many additional
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chip-select as needed may follow and should be phandles of GPIO
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lines. 'reg' entries of the NAND chip subnodes become indexes of
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this array when this property is present.
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minItems: 1
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maxItems: 8
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partitions:
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type: object
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required:
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- compatible
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patternProperties:
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"^nand@[a-f0-9]$":
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type: object
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$ref: raw-nand-chip.yaml#
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"^partition@[0-9a-f]+$":
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type: object
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$ref: /schemas/mtd/partitions/partition.yaml#/$defs/partition-node
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deprecated: true
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allOf:
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- $ref: raw-nand-property.yaml#
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- $ref: nand-property.yaml#
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# This is a generic file other binding inherit from and extend
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additionalProperties: true
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@@ -16,6 +16,8 @@ description: |
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||||
children nodes of the NAND controller. This representation should be
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enforced even for simple controllers supporting only one chip.
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select: false
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properties:
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$nodename:
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pattern: "^nand-controller(@.*)?"
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@@ -0,0 +1,64 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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||||
$id: http://devicetree.org/schemas/mtd/nand-property.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
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||||
title: NAND Chip Common Properties
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|
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maintainers:
|
||||
- Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
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||||
description: |
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||||
This file covers the generic properties of a NAND chip. It implies that the
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bus interface should not be taken into account: both raw NAND devices and
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SPI-NAND devices are concerned by this description.
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properties:
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nand-ecc-engine:
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description: |
|
||||
A phandle on the hardware ECC engine if any. There are
|
||||
basically three possibilities:
|
||||
1/ The ECC engine is part of the NAND controller, in this
|
||||
case the phandle should reference the parent node.
|
||||
2/ The ECC engine is part of the NAND part (on-die), in this
|
||||
case the phandle should reference the node itself.
|
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3/ The ECC engine is external, in this case the phandle should
|
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reference the specific ECC engine node.
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$ref: /schemas/types.yaml#/definitions/phandle
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nand-use-soft-ecc-engine:
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description: Use a software ECC engine.
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type: boolean
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||||
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nand-no-ecc-engine:
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||||
description: Do not use any ECC correction.
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type: boolean
|
||||
|
||||
nand-ecc-algo:
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description:
|
||||
Desired ECC algorithm.
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||||
$ref: /schemas/types.yaml#/definitions/string
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enum: [hamming, bch, rs]
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nand-ecc-strength:
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description:
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Maximum number of bits that can be corrected per ECC step.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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nand-ecc-step-size:
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description:
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Number of data bytes covered by a single ECC step.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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||||
|
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secure-regions:
|
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description:
|
||||
Regions in the NAND chip which are protected using a secure element
|
||||
like Trustzone. This property contains the start address and size of
|
||||
the secure regions present.
|
||||
$ref: /schemas/types.yaml#/definitions/uint64-matrix
|
||||
|
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# This file can be referenced by more specific devices (like spi-nands)
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additionalProperties: true
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@@ -11,6 +11,7 @@ maintainers:
|
||||
|
||||
allOf:
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||||
- $ref: nand-chip.yaml#
|
||||
- $ref: raw-nand-property.yaml#
|
||||
|
||||
description: |
|
||||
The ECC strength and ECC step size properties define the user
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@@ -31,79 +32,6 @@ properties:
|
||||
description:
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Contains the chip-select IDs.
|
||||
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nand-ecc-placement:
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description:
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Location of the ECC bytes. This location is unknown by default
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but can be explicitly set to "oob", if all ECC bytes are
|
||||
known to be stored in the OOB area, or "interleaved" if ECC
|
||||
bytes will be interleaved with regular data in the main area.
|
||||
$ref: /schemas/types.yaml#/definitions/string
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enum: [ oob, interleaved ]
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deprecated: true
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nand-ecc-mode:
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description:
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Legacy ECC configuration mixing the ECC engine choice and
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configuration.
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||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum: [none, soft, soft_bch, hw, hw_syndrome, on-die]
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deprecated: true
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nand-bus-width:
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description:
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Bus width to the NAND chip
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [8, 16]
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default: 8
|
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nand-on-flash-bbt:
|
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description:
|
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With this property, the OS will search the device for a Bad
|
||||
Block Table (BBT). If not found, it will create one, reserve
|
||||
a few blocks at the end of the device to store it and update
|
||||
it as the device ages. Otherwise, the out-of-band area of a
|
||||
few pages of all the blocks will be scanned at boot time to
|
||||
find Bad Block Markers (BBM). These markers will help to
|
||||
build a volatile BBT in RAM.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
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nand-ecc-maximize:
|
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description:
|
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Whether or not the ECC strength should be maximized. The
|
||||
maximum ECC strength is both controller and chip
|
||||
dependent. The ECC engine has to select the ECC config
|
||||
providing the best strength and taking the OOB area size
|
||||
constraint into account. This is particularly useful when
|
||||
only the in-band area is used by the upper layers, and you
|
||||
want to make your NAND as reliable as possible.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nand-is-boot-medium:
|
||||
description:
|
||||
Whether or not the NAND chip is a boot medium. Drivers might
|
||||
use this information to select ECC algorithms supported by
|
||||
the boot ROM or similar restrictions.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nand-rb:
|
||||
description:
|
||||
Contains the native Ready/Busy IDs.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
rb-gpios:
|
||||
description:
|
||||
Contains one or more GPIO descriptor (the numper of descriptor
|
||||
depends on the number of R/B pins exposed by the flash) for the
|
||||
Ready/Busy pins. Active state refers to the NAND ready state and
|
||||
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
|
||||
|
||||
wp-gpios:
|
||||
description:
|
||||
Contains one GPIO descriptor for the Write Protect pin.
|
||||
Active state refers to the NAND Write Protect state and should be
|
||||
set to GPIOD_ACTIVE_LOW unless the signal is inverted.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mtd/raw-nand-property.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Raw NAND Chip Common Properties
|
||||
|
||||
maintainers:
|
||||
- Miquel Raynal <miquel.raynal@bootlin.com>
|
||||
|
||||
description: |
|
||||
The ECC strength and ECC step size properties define the user
|
||||
desires in terms of correction capability of a controller. Together,
|
||||
they request the ECC engine to correct {strength} bit errors per
|
||||
{size} bytes for a particular raw NAND chip.
|
||||
|
||||
The interpretation of these parameters is implementation-defined, so
|
||||
not all implementations must support all possible
|
||||
combinations. However, implementations are encouraged to further
|
||||
specify the value(s) they support.
|
||||
|
||||
properties:
|
||||
nand-ecc-placement:
|
||||
description:
|
||||
Location of the ECC bytes. This location is unknown by default
|
||||
but can be explicitly set to "oob", if all ECC bytes are
|
||||
known to be stored in the OOB area, or "interleaved" if ECC
|
||||
bytes will be interleaved with regular data in the main area.
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum: [ oob, interleaved ]
|
||||
deprecated: true
|
||||
|
||||
nand-ecc-mode:
|
||||
description:
|
||||
Legacy ECC configuration mixing the ECC engine choice and
|
||||
configuration.
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
enum: [none, soft, soft_bch, hw, hw_syndrome, on-die]
|
||||
deprecated: true
|
||||
|
||||
nand-bus-width:
|
||||
description:
|
||||
Bus width to the NAND chip
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [8, 16]
|
||||
default: 8
|
||||
|
||||
nand-on-flash-bbt:
|
||||
description:
|
||||
With this property, the OS will search the device for a Bad
|
||||
Block Table (BBT). If not found, it will create one, reserve
|
||||
a few blocks at the end of the device to store it and update
|
||||
it as the device ages. Otherwise, the out-of-band area of a
|
||||
few pages of all the blocks will be scanned at boot time to
|
||||
find Bad Block Markers (BBM). These markers will help to
|
||||
build a volatile BBT in RAM.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nand-ecc-maximize:
|
||||
description:
|
||||
Whether or not the ECC strength should be maximized. The
|
||||
maximum ECC strength is both controller and chip
|
||||
dependent. The ECC engine has to select the ECC config
|
||||
providing the best strength and taking the OOB area size
|
||||
constraint into account. This is particularly useful when
|
||||
only the in-band area is used by the upper layers, and you
|
||||
want to make your NAND as reliable as possible.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nand-is-boot-medium:
|
||||
description:
|
||||
Whether or not the NAND chip is a boot medium. Drivers might
|
||||
use this information to select ECC algorithms supported by
|
||||
the boot ROM or similar restrictions.
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
|
||||
nand-rb:
|
||||
description:
|
||||
Contains the native Ready/Busy IDs.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
|
||||
rb-gpios:
|
||||
description:
|
||||
Contains one or more GPIO descriptor (the numper of descriptor
|
||||
depends on the number of R/B pins exposed by the flash) for the
|
||||
Ready/Busy pins. Active state refers to the NAND ready state and
|
||||
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
|
||||
|
||||
wp-gpios:
|
||||
description:
|
||||
Contains one GPIO descriptor for the Write Protect pin.
|
||||
Active state refers to the NAND Write Protect state and should be
|
||||
set to GPIOD_ACTIVE_LOW unless the signal is inverted.
|
||||
maxItems: 1
|
||||
|
||||
# This is a generic file other binding inherit from and extend
|
||||
additionalProperties: true
|
||||
@@ -17,10 +17,12 @@
|
||||
* - BCH12 : Generate 20 ECC bytes from 512 data bytes plus 6 free bytes
|
||||
*
|
||||
* It can run for arbitrary NAND flash chips with different block and OOB sizes. Currently there
|
||||
* are only two known devices in the wild that have NAND flash and make use of this ECC engine
|
||||
* (Linksys LGS328C & LGS352C). To keep compatibility with vendor firmware, new modes can only
|
||||
* be added when new data layouts have been analyzed. For now allow BCH6 on flash with 2048 byte
|
||||
* blocks and 64 bytes oob.
|
||||
* are a few known devices in the wild that make use of this ECC engine
|
||||
* (Linksys LGS328C, LGS352C & Netlink HG323DAC). To keep compatibility with vendor firmware,
|
||||
* new modes can only be added when new data layouts have been analyzed. For now allow BCH6 on
|
||||
* flash with 2048 byte blocks and at least 64 bytes oob. Some vendors make use of
|
||||
* 128 bytes OOB NAND chips (e.g. Macronix MX35LF1G24AD) but only use BCH6 and thus the first
|
||||
* 64 bytes of the OOB area. In this case the engine leaves any extra bytes unused.
|
||||
*
|
||||
* This driver aligns with kernel ECC naming conventions. Neverthless a short notice on the
|
||||
* Realtek naming conventions for the different structures in the OOB area.
|
||||
@@ -39,7 +41,7 @@
|
||||
*/
|
||||
|
||||
#define RTL_ECC_ALLOWED_PAGE_SIZE 2048
|
||||
#define RTL_ECC_ALLOWED_OOB_SIZE 64
|
||||
#define RTL_ECC_ALLOWED_MIN_OOB_SIZE 64
|
||||
#define RTL_ECC_ALLOWED_STRENGTH 6
|
||||
|
||||
#define RTL_ECC_BLOCK_SIZE 512
|
||||
@@ -310,10 +312,10 @@ static int rtl_ecc_check_support(struct nand_device *nand)
|
||||
struct mtd_info *mtd = nanddev_to_mtd(nand);
|
||||
struct device *dev = nand->ecc.engine->dev;
|
||||
|
||||
if (mtd->oobsize != RTL_ECC_ALLOWED_OOB_SIZE ||
|
||||
if (mtd->oobsize < RTL_ECC_ALLOWED_MIN_OOB_SIZE ||
|
||||
mtd->writesize != RTL_ECC_ALLOWED_PAGE_SIZE) {
|
||||
dev_err(dev, "only flash geometry data=%d, oob=%d supported\n",
|
||||
RTL_ECC_ALLOWED_PAGE_SIZE, RTL_ECC_ALLOWED_OOB_SIZE);
|
||||
dev_err(dev, "only flash geometry data=%d, oob>=%d supported\n",
|
||||
RTL_ECC_ALLOWED_PAGE_SIZE, RTL_ECC_ALLOWED_MIN_OOB_SIZE);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
@@ -837,9 +837,10 @@ static const struct pci_device_id cafe_nand_tbl[] = {
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
|
||||
|
||||
static int cafe_nand_resume(struct pci_dev *pdev)
|
||||
static int cafe_nand_resume(struct device *dev)
|
||||
{
|
||||
uint32_t ctrl;
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
struct mtd_info *mtd = pci_get_drvdata(pdev);
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
struct cafe_priv *cafe = nand_get_controller_data(chip);
|
||||
@@ -877,12 +878,14 @@ static int cafe_nand_resume(struct pci_dev *pdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static DEFINE_SIMPLE_DEV_PM_OPS(cafe_nand_ops, NULL, cafe_nand_resume);
|
||||
|
||||
static struct pci_driver cafe_nand_pci_driver = {
|
||||
.name = "CAFÉ NAND",
|
||||
.id_table = cafe_nand_tbl,
|
||||
.probe = cafe_nand_probe,
|
||||
.remove = cafe_nand_remove,
|
||||
.resume = cafe_nand_resume,
|
||||
.driver.pm = &cafe_nand_ops,
|
||||
};
|
||||
|
||||
module_pci_driver(cafe_nand_pci_driver);
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
* Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
|
||||
*/
|
||||
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/types.h>
|
||||
@@ -863,7 +864,14 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
|
||||
|
||||
/* Fill in fsl_ifc_mtd structure */
|
||||
mtd->dev.parent = priv->dev;
|
||||
nand_set_flash_node(chip, priv->dev->of_node);
|
||||
|
||||
struct device_node *np __free(device_node) =
|
||||
of_get_next_child_with_prefix(priv->dev->of_node, NULL, "nand");
|
||||
|
||||
if (np)
|
||||
nand_set_flash_node(chip, np);
|
||||
else
|
||||
nand_set_flash_node(chip, priv->dev->of_node);
|
||||
|
||||
/* fill in nand_chip structure */
|
||||
/* set up function call table */
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
* Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2008 Embedded Alley Solutions, Inc.
|
||||
*/
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/slab.h>
|
||||
@@ -2688,7 +2689,15 @@ static int gpmi_nand_init(struct gpmi_nand_data *this)
|
||||
|
||||
/* init the nand_chip{}, we don't support a 16-bit NAND Flash bus. */
|
||||
nand_set_controller_data(chip, this);
|
||||
nand_set_flash_node(chip, this->pdev->dev.of_node);
|
||||
|
||||
struct device_node *np __free(device_node) =
|
||||
of_get_next_child_with_prefix(this->pdev->dev.of_node, NULL, "nand");
|
||||
|
||||
if (np)
|
||||
nand_set_flash_node(chip, np);
|
||||
else
|
||||
nand_set_flash_node(chip, this->pdev->dev.of_node);
|
||||
|
||||
chip->legacy.block_markbad = gpmi_block_markbad;
|
||||
chip->badblock_pattern = &gpmi_bbt_descr;
|
||||
chip->options |= NAND_NO_SUBPAGE_WRITE;
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
|
||||
*/
|
||||
|
||||
#include <linux/cleanup.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/init.h>
|
||||
@@ -1714,7 +1715,14 @@ static int mxcnd_probe(struct platform_device *pdev)
|
||||
this->legacy.chip_delay = 5;
|
||||
|
||||
nand_set_controller_data(this, host);
|
||||
nand_set_flash_node(this, pdev->dev.of_node);
|
||||
|
||||
struct device_node *np __free(device_node) =
|
||||
of_get_next_child_with_prefix(pdev->dev.of_node, NULL, "nand");
|
||||
|
||||
if (np)
|
||||
nand_set_flash_node(this, np);
|
||||
else
|
||||
nand_set_flash_node(this, pdev->dev.of_node);
|
||||
|
||||
host->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(host->clk))
|
||||
|
||||
@@ -43,6 +43,7 @@
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/cleanup.h>
|
||||
|
||||
#include "internals.h"
|
||||
|
||||
@@ -4704,16 +4705,16 @@ static void nand_resume(struct mtd_info *mtd)
|
||||
{
|
||||
struct nand_chip *chip = mtd_to_nand(mtd);
|
||||
|
||||
mutex_lock(&chip->lock);
|
||||
if (chip->suspended) {
|
||||
if (chip->ops.resume)
|
||||
chip->ops.resume(chip);
|
||||
chip->suspended = 0;
|
||||
} else {
|
||||
pr_err("%s called for a chip which is not in suspended state\n",
|
||||
__func__);
|
||||
scoped_guard(mutex, &chip->lock) {
|
||||
if (chip->suspended) {
|
||||
if (chip->ops.resume)
|
||||
chip->ops.resume(chip);
|
||||
chip->suspended = 0;
|
||||
} else {
|
||||
pr_err("%s called for a chip which is not in suspended state\n",
|
||||
__func__);
|
||||
}
|
||||
}
|
||||
mutex_unlock(&chip->lock);
|
||||
|
||||
wake_up_all(&chip->resume_wq);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -337,16 +337,19 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
|
||||
if (iface != SSDR)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
/*
|
||||
* SDR dual and quad I/O operations over 104MHz require the HS bit to
|
||||
* enable a few more dummy cycles.
|
||||
*/
|
||||
op = spinand->op_templates->read_cache;
|
||||
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
|
||||
hs = false;
|
||||
else if (op->cmd.buswidth == 1 && op->addr.buswidth == 1 &&
|
||||
op->dummy.buswidth == 1 && op->data.buswidth == 1)
|
||||
else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
|
||||
hs = false;
|
||||
else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
|
||||
hs = false;
|
||||
else if (!op->max_freq)
|
||||
hs = true;
|
||||
else
|
||||
hs = false;
|
||||
hs = true;
|
||||
|
||||
ret = spinand_read_reg_op(spinand, W25N0XJW_SR4, &sr4);
|
||||
if (ret)
|
||||
@@ -485,7 +488,7 @@ static const struct spinand_info winbond_spinand_table[] = {
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
|
||||
&write_cache_variants,
|
||||
&update_cache_variants),
|
||||
0,
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&w25n01jw_ooblayout, NULL),
|
||||
SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
|
||||
SPINAND_INFO("W25N01KV", /* 3.3V */
|
||||
@@ -549,7 +552,7 @@ static const struct spinand_info winbond_spinand_table[] = {
|
||||
SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
|
||||
&write_cache_variants,
|
||||
&update_cache_variants),
|
||||
0,
|
||||
SPINAND_HAS_QE_BIT,
|
||||
SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
|
||||
SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
|
||||
SPINAND_INFO("W25N02KV", /* 3.3V */
|
||||
|
||||
@@ -477,8 +477,9 @@ struct spinand_ecc_info {
|
||||
const struct mtd_ooblayout_ops *ooblayout;
|
||||
};
|
||||
|
||||
#define SPINAND_HAS_QE_BIT BIT(0)
|
||||
#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
|
||||
/* SPI NAND flags */
|
||||
#define SPINAND_HAS_QE_BIT BIT(0)
|
||||
#define SPINAND_HAS_CR_FEAT_BIT BIT(1)
|
||||
#define SPINAND_HAS_PROG_PLANE_SELECT_BIT BIT(2)
|
||||
#define SPINAND_HAS_READ_PLANE_SELECT_BIT BIT(3)
|
||||
#define SPINAND_NO_RAW_ACCESS BIT(4)
|
||||
|
||||
Reference in New Issue
Block a user