mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (47 commits) ehea: Fix napi list corruption on ifconfig down igbvf: Allow VF driver to correctly recognize failure to set mac 3c59x: Fix build failure with gcc 3.2 sky2: Avoid transmits during sky2_down() iwlagn: do not send key clear commands when rfkill enabled libertas: Read buffer overflow drivers/net/wireless: introduce missing kfree drivers/net/wireless/iwlwifi: introduce missing kfree zd1211rw: fix unaligned access in zd_mac_rx cfg80211: fix regression on beacon world roaming feature cfg80211: add two missing NULL pointer checks ixgbe: Patch to modify 82598 PCIe completion timeout values bluetooth: rfcomm_init bug fix mlx4_en: Fix double pci unmapping. mISDN: Fix handling of receive buffer size in L1oIP pcnet32: VLB support fixes pcnet32: remove superfluous NULL pointer check in pcnet32_probe1() net: restore the original spinlock to protect unicast list netxen: fix coherent dma mask setting mISDN: Read buffer overflow ...
This commit is contained in:
commit
ae83060026
55 files changed
+364
-165
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@@ -449,8 +449,8 @@ printk(KERN_INFO "i = %u\n", i);
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</para>
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<programlisting>
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__u32 ipaddress;
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printk(KERN_INFO "my ip: %d.%d.%d.%d\n", NIPQUAD(ipaddress));
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__be32 ipaddress;
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printk(KERN_INFO "my ip: %pI4\n", &ipaddress);
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</programlisting>
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<para>
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@@ -1480,7 +1480,7 @@ l1oip_init(void)
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return -ENOMEM;
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l1oip_cnt = 0;
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while (type[l1oip_cnt] && l1oip_cnt < MAX_CARDS) {
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while (l1oip_cnt < MAX_CARDS && type[l1oip_cnt]) {
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switch (type[l1oip_cnt] & 0xff) {
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case 1:
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pri = 0;
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+3
-1
@@ -832,7 +832,9 @@ static int corkscrew_open(struct net_device *dev)
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skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
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vp->rx_ring[i].addr = isa_virt_to_bus(skb->data);
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}
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vp->rx_ring[i - 1].next = isa_virt_to_bus(&vp->rx_ring[0]); /* Wrap the ring. */
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if (i != 0)
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vp->rx_ring[i - 1].next =
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isa_virt_to_bus(&vp->rx_ring[0]); /* Wrap the ring. */
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outl(isa_virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr);
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}
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if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
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+6
-4
@@ -2721,13 +2721,15 @@ dump_tx_ring(struct net_device *dev)
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&vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
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issue_and_wait(dev, DownStall);
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for (i = 0; i < TX_RING_SIZE; i++) {
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pr_err(" %d: @%p length %8.8x status %8.8x\n", i,
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&vp->tx_ring[i],
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unsigned int length;
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|
||||
#if DO_ZEROCOPY
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le32_to_cpu(vp->tx_ring[i].frag[0].length),
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length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
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#else
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||||
le32_to_cpu(vp->tx_ring[i].length),
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length = le32_to_cpu(vp->tx_ring[i].length);
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#endif
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pr_err(" %d: @%p length %8.8x status %8.8x\n",
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i, &vp->tx_ring[i], length,
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le32_to_cpu(vp->tx_ring[i].status));
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}
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if (!stalled)
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||||
|
||||
@@ -1474,13 +1474,13 @@ static void eexp_hw_init586(struct net_device *dev)
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outw(0x0000, ioaddr + 0x800c);
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outw(0x0000, ioaddr + 0x800e);
|
||||
|
||||
for (i = 0; i < (sizeof(start_code)); i+=32) {
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for (i = 0; i < ARRAY_SIZE(start_code) * 2; i+=32) {
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int j;
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||||
outw(i, ioaddr + SM_PTR);
|
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for (j = 0; j < 16; j+=2)
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||||
for (j = 0; j < 16 && (i+j)/2 < ARRAY_SIZE(start_code); j+=2)
|
||||
outw(start_code[(i+j)/2],
|
||||
ioaddr+0x4000+j);
|
||||
for (j = 0; j < 16; j+=2)
|
||||
for (j = 0; j < 16 && (i+j+16)/2 < ARRAY_SIZE(start_code); j+=2)
|
||||
outw(start_code[(i+j+16)/2],
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ioaddr+0x8000+j);
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}
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|
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@@ -40,7 +40,7 @@
|
||||
#include <asm/io.h>
|
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|
||||
#define DRV_NAME "ehea"
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#define DRV_VERSION "EHEA_0101"
|
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#define DRV_VERSION "EHEA_0102"
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||||
|
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/* eHEA capability flags */
|
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#define DLPAR_PORT_ADD_REM 1
|
||||
|
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@@ -1545,6 +1545,9 @@ static int ehea_clean_portres(struct ehea_port *port, struct ehea_port_res *pr)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
if (pr->qp)
|
||||
netif_napi_del(&pr->napi);
|
||||
|
||||
ret = ehea_destroy_qp(pr->qp);
|
||||
|
||||
if (!ret) {
|
||||
|
||||
@@ -366,9 +366,8 @@ static int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->rxic = mk_ic_value(
|
||||
gfar_usecs2ticks(priv, cvals->rx_coalesce_usecs),
|
||||
cvals->rx_max_coalesced_frames);
|
||||
priv->rxic = mk_ic_value(cvals->rx_max_coalesced_frames,
|
||||
gfar_usecs2ticks(priv, cvals->rx_coalesce_usecs));
|
||||
|
||||
/* Set up tx coalescing */
|
||||
if ((cvals->tx_coalesce_usecs == 0) ||
|
||||
@@ -390,9 +389,8 @@ static int gfar_scoalesce(struct net_device *dev, struct ethtool_coalesce *cvals
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
priv->txic = mk_ic_value(
|
||||
gfar_usecs2ticks(priv, cvals->tx_coalesce_usecs),
|
||||
cvals->tx_max_coalesced_frames);
|
||||
priv->txic = mk_ic_value(cvals->tx_max_coalesced_frames,
|
||||
gfar_usecs2ticks(priv, cvals->tx_coalesce_usecs));
|
||||
|
||||
gfar_write(&priv->regs->rxic, 0);
|
||||
if (priv->rxcoalescing)
|
||||
|
||||
@@ -274,6 +274,8 @@ static s32 e1000_set_vfta_vf(struct e1000_hw *hw, u16 vid, bool set)
|
||||
|
||||
err = mbx->ops.read_posted(hw, msgbuf, 2);
|
||||
|
||||
msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
|
||||
|
||||
/* if nacked the vlan was rejected */
|
||||
if (!err && (msgbuf[0] == (E1000_VF_SET_VLAN | E1000_VT_MSGTYPE_NACK)))
|
||||
err = -E1000_ERR_MAC_INIT;
|
||||
@@ -317,6 +319,8 @@ static void e1000_rar_set_vf(struct e1000_hw *hw, u8 * addr, u32 index)
|
||||
if (!ret_val)
|
||||
ret_val = mbx->ops.read_posted(hw, msgbuf, 3);
|
||||
|
||||
msgbuf[0] &= ~E1000_VT_MSGTYPE_CTS;
|
||||
|
||||
/* if nacked the address was rejected, use "perm_addr" */
|
||||
if (!ret_val &&
|
||||
(msgbuf[0] == (E1000_VF_SET_MAC_ADDR | E1000_VT_MSGTYPE_NACK)))
|
||||
|
||||
@@ -96,6 +96,8 @@
|
||||
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
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#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
|
||||
|
||||
#define IXGBE_MAX_RSC_INT_RATE 162760
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||||
|
||||
/* wrapper around a pointer to a socket buffer,
|
||||
* so a DMA handle can be stored along with the buffer */
|
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struct ixgbe_tx_buffer {
|
||||
|
||||
@@ -49,6 +49,51 @@ static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
|
||||
static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
|
||||
u8 *eeprom_data);
|
||||
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||||
/**
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||||
* ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
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* @hw: pointer to the HW structure
|
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*
|
||||
* The defaults for 82598 should be in the range of 50us to 50ms,
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* however the hardware default for these parts is 500us to 1ms which is less
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* than the 10ms recommended by the pci-e spec. To address this we need to
|
||||
* increase the value to either 10ms to 250ms for capability version 1 config,
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* or 16ms to 55ms for version 2.
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**/
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void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
|
||||
{
|
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struct ixgbe_adapter *adapter = hw->back;
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u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
|
||||
u16 pcie_devctl2;
|
||||
|
||||
/* only take action if timeout value is defaulted to 0 */
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||||
if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
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goto out;
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||||
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||||
/*
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* if capababilities version is type 1 we can write the
|
||||
* timeout of 10ms to 250ms through the GCR register
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||||
*/
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if (!(gcr & IXGBE_GCR_CAP_VER2)) {
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gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
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goto out;
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||||
}
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||||
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||||
/*
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||||
* for version 2 capabilities we need to write the config space
|
||||
* directly in order to set the completion timeout value for
|
||||
* 16ms to 55ms
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||||
*/
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||||
pci_read_config_word(adapter->pdev,
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||||
IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
|
||||
pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
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||||
pci_write_config_word(adapter->pdev,
|
||||
IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
|
||||
out:
|
||||
/* disable completion timeout resend */
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||||
gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
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IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
|
||||
* @hw: pointer to hardware structure
|
||||
@@ -152,6 +197,26 @@ out:
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
|
||||
* @hw: pointer to hardware structure
|
||||
*
|
||||
* Starts the hardware using the generic start_hw function.
|
||||
* Then set pcie completion timeout
|
||||
**/
|
||||
s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
|
||||
{
|
||||
s32 ret_val = 0;
|
||||
|
||||
ret_val = ixgbe_start_hw_generic(hw);
|
||||
|
||||
/* set the completion timeout for interface */
|
||||
if (ret_val == 0)
|
||||
ixgbe_set_pcie_completion_timeout(hw);
|
||||
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* ixgbe_get_link_capabilities_82598 - Determines link capabilities
|
||||
* @hw: pointer to hardware structure
|
||||
@@ -1085,7 +1150,7 @@ out:
|
||||
static struct ixgbe_mac_operations mac_ops_82598 = {
|
||||
.init_hw = &ixgbe_init_hw_generic,
|
||||
.reset_hw = &ixgbe_reset_hw_82598,
|
||||
.start_hw = &ixgbe_start_hw_generic,
|
||||
.start_hw = &ixgbe_start_hw_82598,
|
||||
.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
|
||||
.get_media_type = &ixgbe_get_media_type_82598,
|
||||
.get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
|
||||
|
||||
@@ -1975,7 +1975,10 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
|
||||
* any other value means disable eitr, which is best
|
||||
* served by setting the interrupt rate very high
|
||||
*/
|
||||
adapter->eitr_param = IXGBE_MAX_INT_RATE;
|
||||
if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
|
||||
adapter->eitr_param = IXGBE_MAX_RSC_INT_RATE;
|
||||
else
|
||||
adapter->eitr_param = IXGBE_MAX_INT_RATE;
|
||||
adapter->itr_setting = 0;
|
||||
}
|
||||
|
||||
@@ -1999,13 +2002,13 @@ static int ixgbe_set_flags(struct net_device *netdev, u32 data)
|
||||
|
||||
ethtool_op_set_flags(netdev, data);
|
||||
|
||||
if (!(adapter->flags & IXGBE_FLAG2_RSC_CAPABLE))
|
||||
if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
|
||||
return 0;
|
||||
|
||||
/* if state changes we need to update adapter->flags and reset */
|
||||
if ((!!(data & ETH_FLAG_LRO)) !=
|
||||
(!!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED))) {
|
||||
adapter->flags ^= IXGBE_FLAG2_RSC_ENABLED;
|
||||
(!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
|
||||
adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
|
||||
if (netif_running(netdev))
|
||||
ixgbe_reinit_locked(adapter);
|
||||
else
|
||||
|
||||
@@ -780,7 +780,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
|
||||
prefetch(next_rxd);
|
||||
cleaned_count++;
|
||||
|
||||
if (adapter->flags & IXGBE_FLAG2_RSC_CAPABLE)
|
||||
if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
|
||||
rsc_count = ixgbe_get_rsc_count(rx_desc);
|
||||
|
||||
if (rsc_count) {
|
||||
@@ -2036,7 +2036,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
|
||||
IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
|
||||
}
|
||||
} else {
|
||||
if (!(adapter->flags & IXGBE_FLAG2_RSC_ENABLED) &&
|
||||
if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
|
||||
(netdev->mtu <= ETH_DATA_LEN))
|
||||
rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
|
||||
else
|
||||
@@ -2165,7 +2165,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
|
||||
IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
|
||||
}
|
||||
|
||||
if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED) {
|
||||
if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
|
||||
/* Enable 82599 HW-RSC */
|
||||
for (i = 0; i < adapter->num_rx_queues; i++) {
|
||||
j = adapter->rx_ring[i].reg_idx;
|
||||
@@ -3812,8 +3812,8 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
|
||||
adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
|
||||
} else if (hw->mac.type == ixgbe_mac_82599EB) {
|
||||
adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
|
||||
adapter->flags |= IXGBE_FLAG2_RSC_CAPABLE;
|
||||
adapter->flags |= IXGBE_FLAG2_RSC_ENABLED;
|
||||
adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
|
||||
adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
|
||||
adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
|
||||
adapter->ring_feature[RING_F_FDIR].indices =
|
||||
IXGBE_MAX_FDIR_INDICES;
|
||||
@@ -5360,12 +5360,19 @@ static int ixgbe_del_sanmac_netdev(struct net_device *dev)
|
||||
static void ixgbe_netpoll(struct net_device *netdev)
|
||||
{
|
||||
struct ixgbe_adapter *adapter = netdev_priv(netdev);
|
||||
int i;
|
||||
|
||||
disable_irq(adapter->pdev->irq);
|
||||
adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
|
||||
ixgbe_intr(adapter->pdev->irq, netdev);
|
||||
if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
|
||||
int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
|
||||
for (i = 0; i < num_q_vectors; i++) {
|
||||
struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
|
||||
ixgbe_msix_clean_many(0, q_vector);
|
||||
}
|
||||
} else {
|
||||
ixgbe_intr(adapter->pdev->irq, netdev);
|
||||
}
|
||||
adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
|
||||
enable_irq(adapter->pdev->irq);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -5611,7 +5618,7 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
|
||||
if (pci_using_dac)
|
||||
netdev->features |= NETIF_F_HIGHDMA;
|
||||
|
||||
if (adapter->flags & IXGBE_FLAG2_RSC_ENABLED)
|
||||
if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
|
||||
netdev->features |= NETIF_F_LRO;
|
||||
|
||||
/* make sure the EEPROM is good */
|
||||
|
||||
@@ -718,6 +718,12 @@
|
||||
#define IXGBE_ECC_STATUS_82599 0x110E0
|
||||
#define IXGBE_BAR_CTRL_82599 0x110F4
|
||||
|
||||
/* PCI Express Control */
|
||||
#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
|
||||
#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
|
||||
#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
|
||||
#define IXGBE_GCR_CAP_VER2 0x00040000
|
||||
|
||||
/* Time Sync Registers */
|
||||
#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
|
||||
#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
|
||||
@@ -1521,6 +1527,7 @@
|
||||
|
||||
/* PCI Bus Info */
|
||||
#define IXGBE_PCI_LINK_STATUS 0xB2
|
||||
#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
|
||||
#define IXGBE_PCI_LINK_WIDTH 0x3F0
|
||||
#define IXGBE_PCI_LINK_WIDTH_1 0x10
|
||||
#define IXGBE_PCI_LINK_WIDTH_2 0x20
|
||||
@@ -1531,6 +1538,7 @@
|
||||
#define IXGBE_PCI_LINK_SPEED_5000 0x2
|
||||
#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
|
||||
#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
|
||||
#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
|
||||
|
||||
/* Number of 100 microseconds we wait for PCI Express master disable */
|
||||
#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
|
||||
|
||||
@@ -249,6 +249,7 @@ static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
|
||||
pci_unmap_page(mdev->pdev,
|
||||
(dma_addr_t) be64_to_cpu(data->addr),
|
||||
frag->size, PCI_DMA_TODEVICE);
|
||||
++data;
|
||||
}
|
||||
}
|
||||
/* Stamp the freed descriptor */
|
||||
|
||||
@@ -221,7 +221,7 @@ netxen_napi_disable(struct netxen_adapter *adapter)
|
||||
}
|
||||
}
|
||||
|
||||
static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id)
|
||||
static int nx_set_dma_mask(struct netxen_adapter *adapter)
|
||||
{
|
||||
struct pci_dev *pdev = adapter->pdev;
|
||||
uint64_t mask, cmask;
|
||||
@@ -229,19 +229,17 @@ static int nx_set_dma_mask(struct netxen_adapter *adapter, uint8_t revision_id)
|
||||
adapter->pci_using_dac = 0;
|
||||
|
||||
mask = DMA_BIT_MASK(32);
|
||||
/*
|
||||
* Consistent DMA mask is set to 32 bit because it cannot be set to
|
||||
* 35 bits. For P3 also leave it at 32 bits for now. Only the rings
|
||||
* come off this pool.
|
||||
*/
|
||||
cmask = DMA_BIT_MASK(32);
|
||||
|
||||
if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
|
||||
#ifndef CONFIG_IA64
|
||||
if (revision_id >= NX_P3_B0)
|
||||
mask = DMA_BIT_MASK(39);
|
||||
else if (revision_id == NX_P2_C1)
|
||||
mask = DMA_BIT_MASK(35);
|
||||
#endif
|
||||
} else {
|
||||
mask = DMA_BIT_MASK(39);
|
||||
cmask = mask;
|
||||
}
|
||||
|
||||
if (pci_set_dma_mask(pdev, mask) == 0 &&
|
||||
pci_set_consistent_dma_mask(pdev, cmask) == 0) {
|
||||
adapter->pci_using_dac = 1;
|
||||
@@ -256,7 +254,7 @@ static int
|
||||
nx_update_dma_mask(struct netxen_adapter *adapter)
|
||||
{
|
||||
int change, shift, err;
|
||||
uint64_t mask, old_mask;
|
||||
uint64_t mask, old_mask, old_cmask;
|
||||
struct pci_dev *pdev = adapter->pdev;
|
||||
|
||||
change = 0;
|
||||
@@ -272,14 +270,29 @@ nx_update_dma_mask(struct netxen_adapter *adapter)
|
||||
|
||||
if (change) {
|
||||
old_mask = pdev->dma_mask;
|
||||
old_cmask = pdev->dev.coherent_dma_mask;
|
||||
|
||||
mask = (1ULL<<(32+shift)) - 1;
|
||||
|
||||
err = pci_set_dma_mask(pdev, mask);
|
||||
if (err)
|
||||
return pci_set_dma_mask(pdev, old_mask);
|
||||
goto err_out;
|
||||
|
||||
if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
|
||||
|
||||
err = pci_set_consistent_dma_mask(pdev, mask);
|
||||
if (err)
|
||||
goto err_out;
|
||||
}
|
||||
dev_info(&pdev->dev, "using %d-bit dma mask\n", 32+shift);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
pci_set_dma_mask(pdev, old_mask);
|
||||
pci_set_consistent_dma_mask(pdev, old_cmask);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void netxen_check_options(struct netxen_adapter *adapter)
|
||||
@@ -1006,7 +1019,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
revision_id = pdev->revision;
|
||||
adapter->ahw.revision_id = revision_id;
|
||||
|
||||
err = nx_set_dma_mask(adapter, revision_id);
|
||||
err = nx_set_dma_mask(adapter);
|
||||
if (err)
|
||||
goto err_out_free_netdev;
|
||||
|
||||
|
||||
+14
-16
@@ -1611,8 +1611,11 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
|
||||
if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
|
||||
&& pcnet32_dwio_check(ioaddr)) {
|
||||
a = &pcnet32_dwio;
|
||||
} else
|
||||
} else {
|
||||
if (pcnet32_debug & NETIF_MSG_PROBE)
|
||||
printk(KERN_ERR PFX "No access methods\n");
|
||||
goto err_release_region;
|
||||
}
|
||||
}
|
||||
|
||||
chip_version =
|
||||
@@ -1719,7 +1722,9 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
|
||||
ret = -ENOMEM;
|
||||
goto err_release_region;
|
||||
}
|
||||
SET_NETDEV_DEV(dev, &pdev->dev);
|
||||
|
||||
if (pdev)
|
||||
SET_NETDEV_DEV(dev, &pdev->dev);
|
||||
|
||||
if (pcnet32_debug & NETIF_MSG_PROBE)
|
||||
printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
|
||||
@@ -1818,7 +1823,6 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
|
||||
|
||||
spin_lock_init(&lp->lock);
|
||||
|
||||
SET_NETDEV_DEV(dev, &pdev->dev);
|
||||
lp->name = chipname;
|
||||
lp->shared_irq = shared;
|
||||
lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
|
||||
@@ -1852,12 +1856,6 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
|
||||
((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
|
||||
lp->options |= PCNET32_PORT_FD;
|
||||
|
||||
if (!a) {
|
||||
if (pcnet32_debug & NETIF_MSG_PROBE)
|
||||
printk(KERN_ERR PFX "No access methods\n");
|
||||
ret = -ENODEV;
|
||||
goto err_free_consistent;
|
||||
}
|
||||
lp->a = *a;
|
||||
|
||||
/* prior to register_netdev, dev->name is not yet correct */
|
||||
@@ -1973,14 +1971,13 @@ pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_ring:
|
||||
err_free_ring:
|
||||
pcnet32_free_ring(dev);
|
||||
err_free_consistent:
|
||||
pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
|
||||
lp->init_block, lp->init_dma_addr);
|
||||
err_free_netdev:
|
||||
err_free_netdev:
|
||||
free_netdev(dev);
|
||||
err_release_region:
|
||||
err_release_region:
|
||||
release_region(ioaddr, PCNET32_TOTAL_SIZE);
|
||||
return ret;
|
||||
}
|
||||
@@ -2089,6 +2086,7 @@ static void pcnet32_free_ring(struct net_device *dev)
|
||||
static int pcnet32_open(struct net_device *dev)
|
||||
{
|
||||
struct pcnet32_private *lp = netdev_priv(dev);
|
||||
struct pci_dev *pdev = lp->pci_dev;
|
||||
unsigned long ioaddr = dev->base_addr;
|
||||
u16 val;
|
||||
int i;
|
||||
@@ -2149,9 +2147,9 @@ static int pcnet32_open(struct net_device *dev)
|
||||
lp->a.write_csr(ioaddr, 124, val);
|
||||
|
||||
/* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
|
||||
if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
|
||||
(lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
|
||||
lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
|
||||
if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
|
||||
(pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
|
||||
pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
|
||||
if (lp->options & PCNET32_PORT_ASEL) {
|
||||
lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
|
||||
if (netif_msg_link(lp))
|
||||
|
||||
+18
-16
@@ -1384,7 +1384,7 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
|
||||
|
||||
/* create a fragment for each channel */
|
||||
bits = B;
|
||||
while (nfree > 0 && len > 0) {
|
||||
while (len > 0) {
|
||||
list = list->next;
|
||||
if (list == &ppp->channels) {
|
||||
i = 0;
|
||||
@@ -1431,29 +1431,31 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
|
||||
*otherwise divide it according to the speed
|
||||
*of the channel we are going to transmit on
|
||||
*/
|
||||
if (pch->speed == 0) {
|
||||
flen = totlen/nfree ;
|
||||
if (nbigger > 0) {
|
||||
flen++;
|
||||
nbigger--;
|
||||
}
|
||||
} else {
|
||||
flen = (((totfree - nzero)*(totlen + hdrlen*totfree)) /
|
||||
((totspeed*totfree)/pch->speed)) - hdrlen;
|
||||
if (nbigger > 0) {
|
||||
flen += ((totfree - nzero)*pch->speed)/totspeed;
|
||||
nbigger -= ((totfree - nzero)*pch->speed)/
|
||||
if (nfree > 0) {
|
||||
if (pch->speed == 0) {
|
||||
flen = totlen/nfree ;
|
||||
if (nbigger > 0) {
|
||||
flen++;
|
||||
nbigger--;
|
||||
}
|
||||
} else {
|
||||
flen = (((totfree - nzero)*(totlen + hdrlen*totfree)) /
|
||||
((totspeed*totfree)/pch->speed)) - hdrlen;
|
||||
if (nbigger > 0) {
|
||||
flen += ((totfree - nzero)*pch->speed)/totspeed;
|
||||
nbigger -= ((totfree - nzero)*pch->speed)/
|
||||
totspeed;
|
||||
}
|
||||
}
|
||||
nfree--;
|
||||
}
|
||||
nfree--;
|
||||
|
||||
/*
|
||||
*check if we are on the last channel or
|
||||
*we exceded the lenght of the data to
|
||||
*fragment
|
||||
*/
|
||||
if ((nfree == 0) || (flen > len))
|
||||
if ((nfree <= 0) || (flen > len))
|
||||
flen = len;
|
||||
/*
|
||||
*it is not worth to tx on slow channels:
|
||||
@@ -1467,7 +1469,7 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
|
||||
continue;
|
||||
}
|
||||
|
||||
mtu = pch->chan->mtu + 2 - hdrlen;
|
||||
mtu = pch->chan->mtu - hdrlen;
|
||||
if (mtu < 4)
|
||||
mtu = 4;
|
||||
if (flen > mtu)
|
||||
|
||||
@@ -1063,6 +1063,7 @@ static void *pppoe_seq_next(struct seq_file *seq, void *v, loff_t *pos)
|
||||
else {
|
||||
int hash = hash_item(po->pppoe_pa.sid, po->pppoe_pa.remote);
|
||||
|
||||
po = NULL;
|
||||
while (++hash < PPPOE_HASH_SIZE) {
|
||||
po = pn->hash_table[hash];
|
||||
if (po)
|
||||
|
||||
@@ -2680,6 +2680,7 @@ out_unregister_pppol2tp_proto:
|
||||
static void __exit pppol2tp_exit(void)
|
||||
{
|
||||
unregister_pppox_proto(PX_PROTO_OL2TP);
|
||||
unregister_pernet_gen_device(pppol2tp_net_id, &pppol2tp_net_ops);
|
||||
proto_unregister(&pppol2tp_sk_proto);
|
||||
}
|
||||
|
||||
|
||||
Loaded 20 of 55 files, more files were not shown because too many files have changed in this diff.
Show more
Reference in new issue
Block a user