linuxmsm/laptops-kernel
0
0
Fork 0
mirror of https://github.com/linux-msm/laptops-kernel.git synced 2026-08-13 14:19:53 -07:00
Code Issues Packages Projects Releases Wiki Activity

LoongArch: Add flush_icache_all()/local_flush_icache_all()

Browse Source 
LoongArch maintains ICache/DCache coherency by hardware, so we just need
"ibar 0" to avoid instruction hazard here.

Signed-off-by: Youling Tang <tangyouling@kylinos.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
Youling Tang
2026-04-22 15:45:12 +08:00
committed by Huacai Chen
parent 0c965d2784
commit adf346e500
2 changed files with 15 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/loongarch/include/asm/cacheflush.h
+15 -1
View File
@@ -32,8 +32,22 @@ static inline unsigned int cpu_last_level_cache_line_size(void)
}
asmlinkage void __flush_cache_all(void);
void local_flush_icache_range(unsigned long start, unsigned long end);
/*
* LoongArch maintains ICache/DCache coherency by hardware,
* we just need "ibar" to avoid instruction hazard here.
*/
static inline void local_flush_icache_all(void)
{
asm volatile ("ibar\t0\n"::);
}
static inline void local_flush_icache_range(unsigned long start, unsigned long end)
{
asm volatile ("ibar\t0\n"::);
}
#define flush_icache_all local_flush_icache_all
#define flush_icache_range local_flush_icache_range
#define flush_icache_user_range local_flush_icache_range
arch/loongarch/mm/cache.c
-10
View File
@@ -31,16 +31,6 @@ void cache_error_setup(void)
set_merr_handler(0x0, &except_vec_cex, 0x80);
}
/*
* LoongArch maintains ICache/DCache coherency by hardware,
* we just need "ibar" to avoid instruction hazard here.
*/
void local_flush_icache_range(unsigned long start, unsigned long end)
{
asm volatile ("\tibar 0\n"::);
}
EXPORT_SYMBOL(local_flush_icache_range);
static void flush_cache_leaf(unsigned int leaf)
{
int i, j, nr_nodes;