mirror of
https://github.com/linux-msm/laptops-kernel.git
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Merge tag 'pci-v5.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI updates from Bjorn Helgaas:
"Enumeration:
- Convert controller drivers to generic_handle_domain_irq() (Marc
Zyngier)
- Simplify VPD (Vital Product Data) access and search (Heiner
Kallweit)
- Update bnx2, bnx2x, bnxt, cxgb4, cxlflash, sfc, tg3 drivers to use
simplified VPD interfaces (Heiner Kallweit)
- Run Max Payload Size quirks before configuring MPS; work around
ASMedia ASM1062 SATA MPS issue (Marek Behún)
Resource management:
- Refactor pci_ioremap_bar() and pci_ioremap_wc_bar() (Krzysztof
Wilczyński)
- Optimize pci_resource_len() to reduce kernel size (Zhen Lei)
PCI device hotplug:
- Fix a double unmap in ibmphp (Vishal Aslot)
PCIe port driver:
- Enable Bandwidth Notification only if port supports it (Stuart
Hayes)
Sysfs/proc/syscalls:
- Add schedule point in proc_bus_pci_read() (Krzysztof Wilczyński)
- Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure (Krzysztof
Wilczyński)
- Return "int" from pciconfig_read() syscall (Krzysztof Wilczyński)
Virtualization:
- Extend "pci=noats" to also turn on Translation Blocking to protect
against some DMA attacks (Alex Williamson)
- Add sysfs mechanism to control the type of reset used between
device assignments to VMs (Amey Narkhede)
- Add support for ACPI _RST reset method (Shanker Donthineni)
- Add ACS quirks for Cavium multi-function devices (George Cherian)
- Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms (Wasim Khan)
- Allow HiSilicon AMBA devices that appear as fake PCI devices to use
PASID and SVA (Zhangfei Gao)
Endpoint framework:
- Add support for SR-IOV Endpoint devices (Kishon Vijay Abraham I)
- Zero-initialize endpoint test tool parameters so we don't use
random parameters (Shunyong Yang)
APM X-Gene PCIe controller driver:
- Remove redundant dev_err() call in xgene_msi_probe() (ErKun Yang)
Broadcom iProc PCIe controller driver:
- Don't fail devm_pci_alloc_host_bridge() on missing 'ranges' because
it's optional on BCMA devices (Rob Herring)
- Fix BCMA probe resource handling (Rob Herring)
Cadence PCIe driver:
- Work around J7200 Link training electrical issue by increasing
delays in LTSSM (Nadeem Athani)
Intel IXP4xx PCI controller driver:
- Depend on ARCH_IXP4XX to avoid useless config questions (Geert
Uytterhoeven)
Intel Keembay PCIe controller driver:
- Add Intel Keem Bay PCIe controller (Srikanth Thokala)
Marvell Aardvark PCIe controller driver:
- Work around config space completion handling issues (Evan Wang)
- Increase timeout for config access completions (Pali Rohár)
- Emulate CRS Software Visibility bit (Pali Rohár)
- Configure resources from DT 'ranges' property to fix I/O space
access (Pali Rohár)
- Serialize INTx mask/unmask (Pali Rohár)
MediaTek PCIe controller driver:
- Add MT7629 support in DT (Chuanjia Liu)
- Fix an MSI issue (Chuanjia Liu)
- Get syscon regmap ("mediatek,generic-pciecfg"), IRQ number
("pci_irq"), PCI domain ("linux,pci-domain") from DT properties if
present (Chuanjia Liu)
Microsoft Hyper-V host bridge driver:
- Add ARM64 support (Boqun Feng)
- Support "Create Interrupt v3" message (Sunil Muthuswamy)
NVIDIA Tegra PCIe controller driver:
- Use seq_puts(), move err_msg from stack to static, fix OF node leak
(Christophe JAILLET)
NVIDIA Tegra194 PCIe driver:
- Disable suspend when in Endpoint mode (Om Prakash Singh)
- Fix MSI-X address programming error (Om Prakash Singh)
- Disable interrupts during suspend to avoid spurious AER link down
(Om Prakash Singh)
Renesas R-Car PCIe controller driver:
- Work around hardware issue that prevents Link L1->L0 transition
(Marek Vasut)
- Fix runtime PM refcount leak (Dinghao Liu)
Rockchip DesignWare PCIe controller driver:
- Add Rockchip RK356X host controller driver (Simon Xue)
TI J721E PCIe driver:
- Add support for J7200 and AM64 (Kishon Vijay Abraham I)
Toshiba Visconti PCIe controller driver:
- Add Toshiba Visconti PCIe host controller driver (Nobuhiro
Iwamatsu)
Xilinx NWL PCIe controller driver:
- Enable PCIe reference clock via CCF (Hyun Kwon)
Miscellaneous:
- Convert sta2x11 from 'pci_' to 'dma_' API (Christophe JAILLET)
- Fix pci_dev_str_match_path() alloc while atomic bug (used for
kernel parameters that specify devices) (Dan Carpenter)
- Remove pointless Precision Time Management warning when PTM is
present but not enabled (Jakub Kicinski)
- Remove surplus "break" statements (Krzysztof Wilczyński)"
* tag 'pci-v5.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (132 commits)
PCI: ibmphp: Fix double unmap of io_mem
x86/PCI: sta2x11: switch from 'pci_' to 'dma_' API
PCI/VPD: Use unaligned access helpers
PCI/VPD: Clean up public VPD defines and inline functions
cxgb4: Use pci_vpd_find_id_string() to find VPD ID string
PCI/VPD: Add pci_vpd_find_id_string()
PCI/VPD: Include post-processing in pci_vpd_find_tag()
PCI/VPD: Stop exporting pci_vpd_find_info_keyword()
PCI/VPD: Stop exporting pci_vpd_find_tag()
PCI: Set dma-can-stall for HiSilicon chips
PCI: rockchip-dwc: Add Rockchip RK356X host controller driver
PCI: dwc: Remove surplus break statement after return
PCI: artpec6: Remove local code block from switch statement
PCI: artpec6: Remove surplus break statement after return
MAINTAINERS: Add entries for Toshiba Visconti PCIe controller
PCI: visconti: Add Toshiba Visconti PCIe host controller driver
PCI/portdrv: Enable Bandwidth Notification only if port supports it
PCI: Allow PASID on fake PCIe devices without TLP prefixes
PCI: mediatek: Use PCI domain to handle ports detection
PCI: mediatek: Add new method to get irq number
...
This commit is contained in:
Linus Torvalds
@@ -121,6 +121,23 @@ Description:
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child buses, and re-discover devices removed earlier
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from this part of the device tree.
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What: /sys/bus/pci/devices/.../reset_method
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Date: August 2021
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Contact: Amey Narkhede <ameynarkhede03@gmail.com>
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Description:
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Some devices allow an individual function to be reset
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without affecting other functions in the same slot.
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For devices that have this support, a file named
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reset_method is present in sysfs. Reading this file
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gives names of the supported and enabled reset methods and
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their ordering. Writing a space-separated list of names of
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reset methods sets the reset methods and ordering to be
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used when resetting the device. Writing an empty string
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disables the ability to reset the device. Writing
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"default" enables all supported reset methods in the
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default ordering.
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What: /sys/bus/pci/devices/.../reset
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Date: July 2009
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Contact: Michael S. Tsirkin <mst@redhat.com>
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@@ -43,6 +43,7 @@ entries corresponding to EPF driver will be created by the EPF core.
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.. <EPF Driver1>/
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... <EPF Device 11>/
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... <EPF Device 21>/
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... <EPF Device 31>/
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.. <EPF Driver2>/
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... <EPF Device 12>/
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... <EPF Device 22>/
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@@ -68,6 +69,7 @@ created)
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... subsys_vendor_id
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... subsys_id
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... interrupt_pin
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... <Symlink EPF Device 31>/
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... primary/
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... <Symlink EPC Device1>/
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... secondary/
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@@ -79,6 +81,13 @@ interface should be added in 'primary' directory and symlink of endpoint
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controller connected to secondary interface should be added in 'secondary'
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directory.
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The <EPF Device> directory can have a list of symbolic links
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(<Symlink EPF Device 31>) to other <EPF Device>. These symbolic links should
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be created by the user to represent the virtual functions that are bound to
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the physical function. In the above directory structure <EPF Device 11> is a
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physical function and <EPF Device 31> is a virtual function. An EPF device once
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it's linked to another EPF device, cannot be linked to a EPC device.
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EPC Device
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==========
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@@ -98,7 +107,8 @@ entries corresponding to EPC device will be created by the EPC core.
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The <EPC Device> directory will have a list of symbolic links to
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<EPF Device>. These symbolic links should be created by the user to
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represent the functions present in the endpoint device.
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represent the functions present in the endpoint device. Only <EPF Device>
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that represents a physical function can be linked to a EPC device.
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The <EPC Device> directory will also have a *start* field. Once
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"1" is written to this field, the endpoint device will be ready to
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@@ -0,0 +1,69 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel Keem Bay PCIe controller Endpoint mode
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maintainers:
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- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
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- Srikanth Thokala <srikanth.thokala@intel.com>
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properties:
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compatible:
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const: intel,keembay-pcie-ep
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reg:
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maxItems: 5
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reg-names:
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items:
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- const: dbi
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- const: dbi2
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- const: atu
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- const: addr_space
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- const: apb
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interrupts:
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maxItems: 4
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interrupt-names:
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items:
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- const: pcie
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- const: pcie_ev
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- const: pcie_err
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- const: pcie_mem_access
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num-lanes:
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description: Number of lanes to use.
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enum: [ 1, 2 ]
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pcie-ep@37000000 {
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compatible = "intel,keembay-pcie-ep";
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reg = <0x37000000 0x00001000>,
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<0x37100000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36000000 0x01000000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
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num-lanes = <2>;
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};
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@@ -0,0 +1,97 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/intel,keembay-pcie.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Intel Keem Bay PCIe controller Root Complex mode
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maintainers:
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- Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
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- Srikanth Thokala <srikanth.thokala@intel.com>
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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const: intel,keembay-pcie
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ranges:
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maxItems: 1
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reset-gpios:
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maxItems: 1
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: dbi
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- const: atu
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- const: config
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- const: apb
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: master
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- const: aux
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interrupts:
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maxItems: 3
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interrupt-names:
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items:
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- const: pcie
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- const: pcie_ev
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- const: pcie_err
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num-lanes:
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description: Number of lanes to use.
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enum: [ 1, 2 ]
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required:
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- compatible
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- reg
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- reg-names
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- ranges
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- clocks
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- clock-names
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- interrupts
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- interrupt-names
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- reset-gpios
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#define KEEM_BAY_A53_PCIE
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#define KEEM_BAY_A53_AUX_PCIE
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pcie@37000000 {
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compatible = "intel,keembay-pcie";
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reg = <0x37000000 0x00001000>,
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<0x37300000 0x00001000>,
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<0x36e00000 0x00200000>,
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<0x37800000 0x00000200>;
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reg-names = "dbi", "atu", "config", "apb";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x02000000 0 0x36000000 0x36000000 0 0x00e00000>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie", "pcie_ev", "pcie_err";
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clocks = <&scmi_clk KEEM_BAY_A53_PCIE>,
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<&scmi_clk KEEM_BAY_A53_AUX_PCIE>;
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clock-names = "master", "aux";
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reset-gpios = <&pca2 9 GPIO_ACTIVE_LOW>;
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num-lanes = <2>;
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};
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@@ -0,0 +1,39 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek PCIECFG controller
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|
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maintainers:
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- Chuanjia Liu <chuanjia.liu@mediatek.com>
|
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- Jianjun Wang <jianjun.wang@mediatek.com>
|
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|
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description: |
|
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The MediaTek PCIECFG controller controls some feature about
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LTSSM, ASPM and so on.
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|
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properties:
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compatible:
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items:
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- enum:
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- mediatek,generic-pciecfg
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- const: syscon
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reg:
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maxItems: 1
|
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|
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required:
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- compatible
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- reg
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additionalProperties: false
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|
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examples:
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- |
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pciecfg: pciecfg@1a140000 {
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compatible = "mediatek,generic-pciecfg", "syscon";
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reg = <0x1a140000 0x1000>;
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};
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...
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@@ -8,7 +8,7 @@ Required properties:
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"mediatek,mt7623-pcie"
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"mediatek,mt7629-pcie"
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- device_type: Must be "pci"
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- reg: Base addresses and lengths of the PCIe subsys and root ports.
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- reg: Base addresses and lengths of the root ports.
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- reg-names: Names of the above areas to use during resource lookup.
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- #address-cells: Address representation for root ports (must be 3)
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- #size-cells: Size representation for root ports (must be 2)
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@@ -47,9 +47,12 @@ Required properties for MT7623/MT2701:
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- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
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number of root ports.
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|
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Required properties for MT2712/MT7622:
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Required properties for MT2712/MT7622/MT7629:
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-interrupts: A list of interrupt outputs of the controller, must have one
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entry for each PCIe port
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- interrupt-names: Must include the following entries:
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- "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
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- linux,pci-domain: PCI domain ID. Should be unique for each host controller
|
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|
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In addition, the device tree node must have sub-nodes describing each
|
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PCIe port interface, having the following mandatory properties:
|
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@@ -143,130 +146,143 @@ Examples for MT7623:
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|
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Examples for MT2712:
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pcie: pcie@11700000 {
|
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pcie1: pcie@112ff000 {
|
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compatible = "mediatek,mt2712-pcie";
|
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device_type = "pci";
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reg = <0 0x11700000 0 0x1000>,
|
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<0 0x112ff000 0 0x1000>;
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reg-names = "port0", "port1";
|
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reg = <0 0x112ff000 0 0x1000>;
|
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reg-names = "port1";
|
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linux,pci-domain = <1>;
|
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#address-cells = <3>;
|
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#size-cells = <2>;
|
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
|
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<&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
|
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<&pericfg CLK_PERI_PCIE0>,
|
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
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interrupt-names = "pcie_irq";
|
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clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
|
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<&pericfg CLK_PERI_PCIE1>;
|
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clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
|
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phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy0", "pcie-phy1";
|
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clock-names = "sys_ck1", "ahb_ck1";
|
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phys = <&u3port1 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy1";
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
|
||||
status = "disabled";
|
||||
|
||||
pcie0: pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
pcie0: pcie@11700000 {
|
||||
compatible = "mediatek,mt2712-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x11700000 0 0x1000>;
|
||||
reg-names = "port0";
|
||||
linux,pci-domain = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pcie_irq";
|
||||
clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
|
||||
<&pericfg CLK_PERI_PCIE0>;
|
||||
clock-names = "sys_ck0", "ahb_ck0";
|
||||
phys = <&u3port0 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy0";
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Examples for MT7622:
|
||||
|
||||
pcie: pcie@1a140000 {
|
||||
pcie0: pcie@1a143000 {
|
||||
compatible = "mediatek,mt7622-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x1a140000 0 0x1000>,
|
||||
<0 0x1a143000 0 0x1000>,
|
||||
<0 0x1a145000 0 0x1000>;
|
||||
reg-names = "subsys", "port0", "port1";
|
||||
reg = <0 0x1a143000 0 0x1000>;
|
||||
reg-names = "port0";
|
||||
linux,pci-domain = <0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "pcie_irq";
|
||||
clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
|
||||
<&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P0_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P0_OBFF_EN>,
|
||||
<&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
<&pciesys CLK_PCIE_P0_PIPE_EN>,
|
||||
<&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
|
||||
"aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
|
||||
"obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
|
||||
phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy0", "pcie-phy1";
|
||||
<&pciesys CLK_PCIE_P0_PIPE_EN>;
|
||||
clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
|
||||
"axi_ck0", "obff_ck0", "pipe_ck0";
|
||||
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
|
||||
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
|
||||
status = "disabled";
|
||||
|
||||
pcie0: pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@1a145000 {
|
||||
compatible = "mediatek,mt7622-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x1a145000 0 0x1000>;
|
||||
reg-names = "port1";
|
||||
linux,pci-domain = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "pcie_irq";
|
||||
clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
||||
/* designer has connect RC1 with p0_ahb clock */
|
||||
<&pciesys CLK_PCIE_P0_AHB_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AUX_EN>,
|
||||
<&pciesys CLK_PCIE_P1_AXI_EN>,
|
||||
<&pciesys CLK_PCIE_P1_OBFF_EN>,
|
||||
<&pciesys CLK_PCIE_P1_PIPE_EN>;
|
||||
clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
|
||||
"axi_ck1", "obff_ck1", "pipe_ck1";
|
||||
|
||||
power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
|
||||
status = "disabled";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
|
||||
<0 0 0 2 &pcie_intc0 1>,
|
||||
<0 0 0 3 &pcie_intc0 2>,
|
||||
<0 0 0 4 &pcie_intc0 3>;
|
||||
pcie_intc0: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
|
||||
<0 0 0 2 &pcie_intc1 1>,
|
||||
<0 0 0 3 &pcie_intc1 2>,
|
||||
<0 0 0 4 &pcie_intc1 3>;
|
||||
pcie_intc1: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -23,6 +23,13 @@ properties:
|
||||
default: 1
|
||||
maximum: 255
|
||||
|
||||
max-virtual-functions:
|
||||
description: Array representing the number of virtual functions corresponding to each physical
|
||||
function
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
minItems: 1
|
||||
maxItems: 255
|
||||
|
||||
max-link-speed:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 1, 2, 3, 4 ]
|
||||
|
||||
@@ -35,6 +35,7 @@ Required properties:
|
||||
|
||||
Optional properties:
|
||||
- dma-coherent: present if DMA operations are coherent
|
||||
- clocks: Input clock specifier. Refer to common clock bindings
|
||||
|
||||
Example:
|
||||
++++++++
|
||||
|
||||
@@ -2733,11 +2733,13 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iwamatsu/linux-visconti.git
|
||||
F: Documentation/devicetree/bindings/arm/toshiba.yaml
|
||||
F: Documentation/devicetree/bindings/net/toshiba,visconti-dwmac.yaml
|
||||
F: Documentation/devicetree/bindings/gpio/toshiba,gpio-visconti.yaml
|
||||
F: Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.yaml
|
||||
F: Documentation/devicetree/bindings/pinctrl/toshiba,tmpv7700-pinctrl.yaml
|
||||
F: Documentation/devicetree/bindings/watchdog/toshiba,visconti-wdt.yaml
|
||||
F: arch/arm64/boot/dts/toshiba/
|
||||
F: drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
|
||||
F: drivers/gpio/gpio-visconti.c
|
||||
F: drivers/pci/controller/dwc/pcie-visconti.c
|
||||
F: drivers/pinctrl/visconti/
|
||||
F: drivers/watchdog/visconti_wdt.c
|
||||
N: visconti
|
||||
@@ -14541,6 +14543,13 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt
|
||||
F: drivers/pci/controller/dwc/pcie-histb.c
|
||||
|
||||
PCIE DRIVER FOR INTEL KEEM BAY
|
||||
M: Srikanth Thokala <srikanth.thokala@intel.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/pci/intel,keembay-pcie*
|
||||
F: drivers/pci/controller/dwc/pcie-keembay.c
|
||||
|
||||
PCIE DRIVER FOR INTEL LGM GW SOC
|
||||
M: Rahul Tanwar <rtanwar@maxlinear.com>
|
||||
L: linux-pci@vger.kernel.org
|
||||
|
||||
+22
-7
@@ -82,14 +82,29 @@ int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
|
||||
|
||||
int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
|
||||
{
|
||||
if (!acpi_disabled) {
|
||||
struct pci_config_window *cfg = bridge->bus->sysdata;
|
||||
struct acpi_device *adev = to_acpi_device(cfg->parent);
|
||||
struct device *bus_dev = &bridge->bus->dev;
|
||||
struct pci_config_window *cfg;
|
||||
struct acpi_device *adev;
|
||||
struct device *bus_dev;
|
||||
|
||||
ACPI_COMPANION_SET(&bridge->dev, adev);
|
||||
set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev)));
|
||||
}
|
||||
if (acpi_disabled)
|
||||
return 0;
|
||||
|
||||
cfg = bridge->bus->sysdata;
|
||||
|
||||
/*
|
||||
* On Hyper-V there is no corresponding ACPI device for a root bridge,
|
||||
* therefore ->parent is set as NULL by the driver. And set 'adev' as
|
||||
* NULL in this case because there is no proper ACPI device.
|
||||
*/
|
||||
if (!cfg->parent)
|
||||
adev = NULL;
|
||||
else
|
||||
adev = to_acpi_device(cfg->parent);
|
||||
|
||||
bus_dev = &bridge->bus->dev;
|
||||
|
||||
ACPI_COMPANION_SET(&bridge->dev, adev);
|
||||
set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev)));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <asm/pci_x86.h>
|
||||
#include <asm/numachip/numachip.h>
|
||||
|
||||
static u8 limit __read_mostly;
|
||||
|
||||
|
||||
@@ -146,8 +146,7 @@ static void sta2x11_map_ep(struct pci_dev *pdev)
|
||||
dev_err(dev, "sta2x11: could not set DMA offset\n");
|
||||
|
||||
dev->bus_dma_limit = max_amba_addr;
|
||||
pci_set_consistent_dma_mask(pdev, max_amba_addr);
|
||||
pci_set_dma_mask(pdev, max_amba_addr);
|
||||
dma_set_mask_and_coherent(&pdev->dev, max_amba_addr);
|
||||
|
||||
/* Configure AHB mapping */
|
||||
pci_write_config_dword(pdev, AHB_PEXLBASE(0), 0);
|
||||
|
||||
@@ -306,9 +306,7 @@ static int nitrox_device_flr(struct pci_dev *pdev)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* check flr support */
|
||||
if (pcie_has_flr(pdev))
|
||||
pcie_flr(pdev);
|
||||
pcie_reset_flr(pdev, PCI_RESET_DO_RESET);
|
||||
|
||||
pci_restore_state(pdev);
|
||||
|
||||
|
||||
@@ -69,6 +69,8 @@
|
||||
#define FLAG_USE_DMA BIT(0)
|
||||
|
||||
#define PCI_DEVICE_ID_TI_AM654 0xb00c
|
||||
#define PCI_DEVICE_ID_TI_J7200 0xb00f
|
||||
#define PCI_DEVICE_ID_TI_AM64 0xb010
|
||||
#define PCI_DEVICE_ID_LS1088A 0x80c0
|
||||
|
||||
#define is_am654_pci_dev(pdev) \
|
||||
@@ -970,6 +972,12 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
|
||||
.driver_data = (kernel_ulong_t)&j721e_data,
|
||||
},
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
|
||||
.driver_data = (kernel_ulong_t)&j721e_data,
|
||||
},
|
||||
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
|
||||
.driver_data = (kernel_ulong_t)&j721e_data,
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
|
||||
@@ -979,6 +987,7 @@ static struct pci_driver pci_endpoint_test_driver = {
|
||||
.id_table = pci_endpoint_test_tbl,
|
||||
.probe = pci_endpoint_test_probe,
|
||||
.remove = pci_endpoint_test_remove,
|
||||
.sriov_configure = pci_sriov_configure_simple,
|
||||
};
|
||||
module_pci_driver(pci_endpoint_test_driver);
|
||||
|
||||
|
||||
@@ -8038,9 +8038,9 @@ bnx2_get_pci_speed(struct bnx2 *bp)
|
||||
static void
|
||||
bnx2_read_vpd_fw_ver(struct bnx2 *bp)
|
||||
{
|
||||
unsigned int len;
|
||||
int rc, i, j;
|
||||
u8 *data;
|
||||
unsigned int block_end, rosize, len;
|
||||
|
||||
#define BNX2_VPD_NVRAM_OFFSET 0x300
|
||||
#define BNX2_VPD_LEN 128
|
||||
@@ -8057,38 +8057,21 @@ bnx2_read_vpd_fw_ver(struct bnx2 *bp)
|
||||
for (i = 0; i < BNX2_VPD_LEN; i += 4)
|
||||
swab32s((u32 *)&data[i]);
|
||||
|
||||
i = pci_vpd_find_tag(data, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
|
||||
if (i < 0)
|
||||
goto vpd_done;
|
||||
|
||||
rosize = pci_vpd_lrdt_size(&data[i]);
|
||||
i += PCI_VPD_LRDT_TAG_SIZE;
|
||||
block_end = i + rosize;
|
||||
|
||||
if (block_end > BNX2_VPD_LEN)
|
||||
goto vpd_done;
|
||||
|
||||
j = pci_vpd_find_info_keyword(data, i, rosize,
|
||||
PCI_VPD_RO_KEYWORD_MFR_ID);
|
||||
j = pci_vpd_find_ro_info_keyword(data, BNX2_VPD_LEN,
|
||||
PCI_VPD_RO_KEYWORD_MFR_ID, &len);
|
||||
if (j < 0)
|
||||
goto vpd_done;
|
||||
|
||||
len = pci_vpd_info_field_size(&data[j]);
|
||||
|
||||
j += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
if (j + len > block_end || len != 4 ||
|
||||
memcmp(&data[j], "1028", 4))
|
||||
if (len != 4 || memcmp(&data[j], "1028", 4))
|
||||
goto vpd_done;
|
||||
|
||||
j = pci_vpd_find_info_keyword(data, i, rosize,
|
||||
PCI_VPD_RO_KEYWORD_VENDOR0);
|
||||
j = pci_vpd_find_ro_info_keyword(data, BNX2_VPD_LEN,
|
||||
PCI_VPD_RO_KEYWORD_VENDOR0,
|
||||
&len);
|
||||
if (j < 0)
|
||||
goto vpd_done;
|
||||
|
||||
len = pci_vpd_info_field_size(&data[j]);
|
||||
|
||||
j += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
|
||||
if (len > BNX2_MAX_VER_SLEN)
|
||||
goto vpd_done;
|
||||
|
||||
memcpy(bp->fw_version, &data[j], len);
|
||||
|
||||
@@ -2407,7 +2407,6 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
|
||||
#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
|
||||
#endif
|
||||
|
||||
#define BNX2X_VPD_LEN 128
|
||||
#define VENDOR_ID_LEN 4
|
||||
|
||||
#define VF_ACQUIRE_THRESH 3
|
||||
|
||||
@@ -12189,86 +12189,35 @@ static int bnx2x_get_hwinfo(struct bnx2x *bp)
|
||||
|
||||
static void bnx2x_read_fwinfo(struct bnx2x *bp)
|
||||
{
|
||||
int cnt, i, block_end, rodi;
|
||||
char vpd_start[BNX2X_VPD_LEN+1];
|
||||
char str_id_reg[VENDOR_ID_LEN+1];
|
||||
char str_id_cap[VENDOR_ID_LEN+1];
|
||||
char *vpd_data;
|
||||
char *vpd_extended_data = NULL;
|
||||
u8 len;
|
||||
char str_id[VENDOR_ID_LEN + 1];
|
||||
unsigned int vpd_len, kw_len;
|
||||
u8 *vpd_data;
|
||||
int rodi;
|
||||
|
||||
cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
|
||||
memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
|
||||
|
||||
if (cnt < BNX2X_VPD_LEN)
|
||||
vpd_data = pci_vpd_alloc(bp->pdev, &vpd_len);
|
||||
if (IS_ERR(vpd_data))
|
||||
return;
|
||||
|
||||
rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len,
|
||||
PCI_VPD_RO_KEYWORD_MFR_ID, &kw_len);
|
||||
if (rodi < 0 || kw_len != VENDOR_ID_LEN)
|
||||
goto out_not_found;
|
||||
|
||||
/* VPD RO tag should be first tag after identifier string, hence
|
||||
* we should be able to find it in first BNX2X_VPD_LEN chars
|
||||
*/
|
||||
i = pci_vpd_find_tag(vpd_start, BNX2X_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
|
||||
if (i < 0)
|
||||
goto out_not_found;
|
||||
|
||||
block_end = i + PCI_VPD_LRDT_TAG_SIZE +
|
||||
pci_vpd_lrdt_size(&vpd_start[i]);
|
||||
|
||||
i += PCI_VPD_LRDT_TAG_SIZE;
|
||||
|
||||
if (block_end > BNX2X_VPD_LEN) {
|
||||
vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
|
||||
if (vpd_extended_data == NULL)
|
||||
goto out_not_found;
|
||||
|
||||
/* read rest of vpd image into vpd_extended_data */
|
||||
memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
|
||||
cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
|
||||
block_end - BNX2X_VPD_LEN,
|
||||
vpd_extended_data + BNX2X_VPD_LEN);
|
||||
if (cnt < (block_end - BNX2X_VPD_LEN))
|
||||
goto out_not_found;
|
||||
vpd_data = vpd_extended_data;
|
||||
} else
|
||||
vpd_data = vpd_start;
|
||||
|
||||
/* now vpd_data holds full vpd content in both cases */
|
||||
|
||||
rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
|
||||
PCI_VPD_RO_KEYWORD_MFR_ID);
|
||||
if (rodi < 0)
|
||||
goto out_not_found;
|
||||
|
||||
len = pci_vpd_info_field_size(&vpd_data[rodi]);
|
||||
|
||||
if (len != VENDOR_ID_LEN)
|
||||
goto out_not_found;
|
||||
|
||||
rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
|
||||
/* vendor specific info */
|
||||
snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
|
||||
snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
|
||||
if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
|
||||
!strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
|
||||
|
||||
rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
|
||||
PCI_VPD_RO_KEYWORD_VENDOR0);
|
||||
if (rodi >= 0) {
|
||||
len = pci_vpd_info_field_size(&vpd_data[rodi]);
|
||||
|
||||
rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
|
||||
if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
|
||||
memcpy(bp->fw_ver, &vpd_data[rodi], len);
|
||||
bp->fw_ver[len] = ' ';
|
||||
}
|
||||
snprintf(str_id, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
|
||||
if (!strncasecmp(str_id, &vpd_data[rodi], VENDOR_ID_LEN)) {
|
||||
rodi = pci_vpd_find_ro_info_keyword(vpd_data, vpd_len,
|
||||
PCI_VPD_RO_KEYWORD_VENDOR0,
|
||||
&kw_len);
|
||||
if (rodi >= 0 && kw_len < sizeof(bp->fw_ver)) {
|
||||
memcpy(bp->fw_ver, &vpd_data[rodi], kw_len);
|
||||
bp->fw_ver[kw_len] = ' ';
|
||||
}
|
||||
kfree(vpd_extended_data);
|
||||
return;
|
||||
}
|
||||
out_not_found:
|
||||
kfree(vpd_extended_data);
|
||||
return;
|
||||
kfree(vpd_data);
|
||||
}
|
||||
|
||||
static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
|
||||
|
||||
@@ -13100,66 +13100,35 @@ static int bnxt_init_mac_addr(struct bnxt *bp)
|
||||
return rc;
|
||||
}
|
||||
|
||||
#define BNXT_VPD_LEN 512
|
||||
static void bnxt_vpd_read_info(struct bnxt *bp)
|
||||
{
|
||||
struct pci_dev *pdev = bp->pdev;
|
||||
int i, len, pos, ro_size, size;
|
||||
ssize_t vpd_size;
|
||||
unsigned int vpd_size, kw_len;
|
||||
int pos, size;
|
||||
u8 *vpd_data;
|
||||
|
||||
vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL);
|
||||
if (!vpd_data)
|
||||
vpd_data = pci_vpd_alloc(pdev, &vpd_size);
|
||||
if (IS_ERR(vpd_data)) {
|
||||
pci_warn(pdev, "Unable to read VPD\n");
|
||||
return;
|
||||
|
||||
vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data);
|
||||
if (vpd_size <= 0) {
|
||||
netdev_err(bp->dev, "Unable to read VPD\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
i = pci_vpd_find_tag(vpd_data, vpd_size, PCI_VPD_LRDT_RO_DATA);
|
||||
if (i < 0) {
|
||||
netdev_err(bp->dev, "VPD READ-Only not found\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
i = pci_vpd_find_tag(vpd_data, vpd_size, PCI_VPD_LRDT_RO_DATA);
|
||||
if (i < 0) {
|
||||
netdev_err(bp->dev, "VPD READ-Only not found\n");
|
||||
goto exit;
|
||||
}
|
||||
|
||||
ro_size = pci_vpd_lrdt_size(&vpd_data[i]);
|
||||
i += PCI_VPD_LRDT_TAG_SIZE;
|
||||
if (i + ro_size > vpd_size)
|
||||
goto exit;
|
||||
|
||||
pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
|
||||
PCI_VPD_RO_KEYWORD_PARTNO);
|
||||
pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
|
||||
PCI_VPD_RO_KEYWORD_PARTNO, &kw_len);
|
||||
if (pos < 0)
|
||||
goto read_sn;
|
||||
|
||||
len = pci_vpd_info_field_size(&vpd_data[pos]);
|
||||
pos += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
if (len + pos > vpd_size)
|
||||
goto read_sn;
|
||||
|
||||
size = min(len, BNXT_VPD_FLD_LEN - 1);
|
||||
size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
|
||||
memcpy(bp->board_partno, &vpd_data[pos], size);
|
||||
|
||||
read_sn:
|
||||
pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
|
||||
PCI_VPD_RO_KEYWORD_SERIALNO);
|
||||
pos = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size,
|
||||
PCI_VPD_RO_KEYWORD_SERIALNO,
|
||||
&kw_len);
|
||||
if (pos < 0)
|
||||
goto exit;
|
||||
|
||||
len = pci_vpd_info_field_size(&vpd_data[pos]);
|
||||
pos += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
if (len + pos > vpd_size)
|
||||
goto exit;
|
||||
|
||||
size = min(len, BNXT_VPD_FLD_LEN - 1);
|
||||
size = min_t(int, kw_len, BNXT_VPD_FLD_LEN - 1);
|
||||
memcpy(bp->board_serialno, &vpd_data[pos], size);
|
||||
exit:
|
||||
kfree(vpd_data);
|
||||
|
||||
@@ -12788,7 +12788,7 @@ static void tg3_get_ethtool_stats(struct net_device *dev,
|
||||
memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
|
||||
}
|
||||
|
||||
static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
|
||||
static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen)
|
||||
{
|
||||
int i;
|
||||
__be32 *buf;
|
||||
@@ -12822,15 +12822,11 @@ static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
|
||||
offset = TG3_NVM_VPD_OFF;
|
||||
len = TG3_NVM_VPD_LEN;
|
||||
}
|
||||
} else {
|
||||
len = TG3_NVM_PCI_VPD_MAX_LEN;
|
||||
}
|
||||
|
||||
buf = kmalloc(len, GFP_KERNEL);
|
||||
if (buf == NULL)
|
||||
return NULL;
|
||||
buf = kmalloc(len, GFP_KERNEL);
|
||||
if (!buf)
|
||||
return NULL;
|
||||
|
||||
if (magic == TG3_EEPROM_MAGIC) {
|
||||
for (i = 0; i < len; i += 4) {
|
||||
/* The data is in little-endian format in NVRAM.
|
||||
* Use the big-endian read routines to preserve
|
||||
@@ -12841,12 +12837,9 @@ static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
|
||||
}
|
||||
*vpdlen = len;
|
||||
} else {
|
||||
ssize_t cnt;
|
||||
|
||||
cnt = pci_read_vpd(tp->pdev, 0, len, (u8 *)buf);
|
||||
if (cnt < 0)
|
||||
goto error;
|
||||
*vpdlen = cnt;
|
||||
buf = pci_vpd_alloc(tp->pdev, vpdlen);
|
||||
if (IS_ERR(buf))
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return buf;
|
||||
@@ -12868,9 +12861,10 @@ error:
|
||||
|
||||
static int tg3_test_nvram(struct tg3 *tp)
|
||||
{
|
||||
u32 csum, magic, len;
|
||||
u32 csum, magic;
|
||||
__be32 *buf;
|
||||
int i, j, k, err = 0, size;
|
||||
unsigned int len;
|
||||
|
||||
if (tg3_flag(tp, NO_NVRAM))
|
||||
return 0;
|
||||
@@ -13013,33 +13007,10 @@ static int tg3_test_nvram(struct tg3 *tp)
|
||||
if (!buf)
|
||||
return -ENOMEM;
|
||||
|
||||
i = pci_vpd_find_tag((u8 *)buf, len, PCI_VPD_LRDT_RO_DATA);
|
||||
if (i > 0) {
|
||||
j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
|
||||
if (j < 0)
|
||||
goto out;
|
||||
|
||||
if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
|
||||
goto out;
|
||||
|
||||
i += PCI_VPD_LRDT_TAG_SIZE;
|
||||
j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
|
||||
PCI_VPD_RO_KEYWORD_CHKSUM);
|
||||
if (j > 0) {
|
||||
u8 csum8 = 0;
|
||||
|
||||
j += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
|
||||
for (i = 0; i <= j; i++)
|
||||
csum8 += ((u8 *)buf)[i];
|
||||
|
||||
if (csum8)
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
err = 0;
|
||||
|
||||
err = pci_vpd_check_csum(buf, len);
|
||||
/* go on if no checksum found */
|
||||
if (err == 1)
|
||||
err = 0;
|
||||
out:
|
||||
kfree(buf);
|
||||
return err;
|
||||
@@ -15624,64 +15595,36 @@ skip_phy_reset:
|
||||
static void tg3_read_vpd(struct tg3 *tp)
|
||||
{
|
||||
u8 *vpd_data;
|
||||
unsigned int block_end, rosize, len;
|
||||
u32 vpdlen;
|
||||
int j, i = 0;
|
||||
unsigned int len, vpdlen;
|
||||
int i;
|
||||
|
||||
vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
|
||||
if (!vpd_data)
|
||||
goto out_no_vpd;
|
||||
|
||||
i = pci_vpd_find_tag(vpd_data, vpdlen, PCI_VPD_LRDT_RO_DATA);
|
||||
i = pci_vpd_find_ro_info_keyword(vpd_data, vpdlen,
|
||||
PCI_VPD_RO_KEYWORD_MFR_ID, &len);
|
||||
if (i < 0)
|
||||
goto out_not_found;
|
||||
goto partno;
|
||||
|
||||
rosize = pci_vpd_lrdt_size(&vpd_data[i]);
|
||||
block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
|
||||
i += PCI_VPD_LRDT_TAG_SIZE;
|
||||
if (len != 4 || memcmp(vpd_data + i, "1028", 4))
|
||||
goto partno;
|
||||
|
||||
if (block_end > vpdlen)
|
||||
goto out_not_found;
|
||||
i = pci_vpd_find_ro_info_keyword(vpd_data, vpdlen,
|
||||
PCI_VPD_RO_KEYWORD_VENDOR0, &len);
|
||||
if (i < 0)
|
||||
goto partno;
|
||||
|
||||
j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
|
||||
PCI_VPD_RO_KEYWORD_MFR_ID);
|
||||
if (j > 0) {
|
||||
len = pci_vpd_info_field_size(&vpd_data[j]);
|
||||
|
||||
j += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
if (j + len > block_end || len != 4 ||
|
||||
memcmp(&vpd_data[j], "1028", 4))
|
||||
goto partno;
|
||||
|
||||
j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
|
||||
PCI_VPD_RO_KEYWORD_VENDOR0);
|
||||
if (j < 0)
|
||||
goto partno;
|
||||
|
||||
len = pci_vpd_info_field_size(&vpd_data[j]);
|
||||
|
||||
j += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
if (j + len > block_end)
|
||||
goto partno;
|
||||
|
||||
if (len >= sizeof(tp->fw_ver))
|
||||
len = sizeof(tp->fw_ver) - 1;
|
||||
memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
|
||||
snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
|
||||
&vpd_data[j]);
|
||||
}
|
||||
memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
|
||||
snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i);
|
||||
|
||||
partno:
|
||||
i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
|
||||
PCI_VPD_RO_KEYWORD_PARTNO);
|
||||
i = pci_vpd_find_ro_info_keyword(vpd_data, vpdlen,
|
||||
PCI_VPD_RO_KEYWORD_PARTNO, &len);
|
||||
if (i < 0)
|
||||
goto out_not_found;
|
||||
|
||||
len = pci_vpd_info_field_size(&vpd_data[i]);
|
||||
|
||||
i += PCI_VPD_INFO_FLD_HDR_SIZE;
|
||||
if (len > TG3_BPN_SIZE ||
|
||||
(len + i) > vpdlen)
|
||||
if (len > TG3_BPN_SIZE)
|
||||
goto out_not_found;
|
||||
|
||||
memcpy(tp->board_part_number, &vpd_data[i], len);
|
||||
|
||||
@@ -2101,7 +2101,6 @@
|
||||
/* Hardware Legacy NVRAM layout */
|
||||
#define TG3_NVM_VPD_OFF 0x100
|
||||
#define TG3_NVM_VPD_LEN 256
|
||||
#define TG3_NVM_PCI_VPD_MAX_LEN 512
|
||||
|
||||
/* Hardware Selfboot NVRAM layout */
|
||||
#define TG3_NVM_HWSB_CFG1 0x00000004
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user