mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This is the main pull request for MIPS:
- a number of fixes that didn't make the 3.19 release.
- a number of cleanups.
- preliminary support for Cavium's Octeon 3 SOCs which feature up to
48 MIPS64 R3 cores with FPU and hardware virtualization.
- support for MIPS R6 processors.
Revision 6 of the MIPS architecture is a major revision of the MIPS
architecture which does away with many of original sins of the
architecture such as branch delay slots. This and other changes in
R6 require major changes throughout the entire MIPS core
architecture code and make up for the lion share of this pull
request.
- finally some preparatory work for eXtendend Physical Address
support, which allows support of up to 40 bit of physical address
space on 32 bit processors"
[ Ahh, MIPS can't leave the PAE brain damage alone. It's like
every CPU architect has to make that mistake, but pee in the snow
by changing the TLA. But whether it's called PAE, LPAE or XPA,
it's horrid crud - Linus ]
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (114 commits)
MIPS: sead3: Corrected get_c0_perfcount_int
MIPS: mm: Remove dead macro definitions
MIPS: OCTEON: irq: add CIB and other fixes
MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs.
MIPS: OCTEON: More OCTEONIII support
MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.
MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup.
MIPS: OCTEON: Update octeon-model.h code for new SoCs.
MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX
MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h
MIPS: OCTEON: Implement the core-16057 workaround
MIPS: OCTEON: Delete unused COP2 saving code
MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
MIPS: OCTEON: Save and restore CP2 SHA3 state
MIPS: OCTEON: Fix FP context save.
MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs
MIPS: boot: Provide more uImage options
MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h
MIPS: ip22-gio: Remove legacy suspend/resume support
mips: pci: Add ifdef around pci_proc_domain
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,43 @@
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* Cavium Interrupt Bus widget
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|
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Properties:
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- compatible: "cavium,octeon-7130-cib"
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Compatibility with cn70XX SoCs.
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- interrupt-controller: This is an interrupt controller.
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- reg: Two elements consisting of the addresses of the RAW and EN
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registers of the CIB block
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- cavium,max-bits: The index (zero based) of the highest numbered bit
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in the CIB block.
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- interrupt-parent: Always the CIU on the SoC.
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- interrupts: The CIU line to which the CIB block is connected.
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- #interrupt-cells: Must be <2>. The first cell is the bit within the
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CIB. The second cell specifies the triggering semantics of the
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line.
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Example:
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interrupt-controller@107000000e000 {
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compatible = "cavium,octeon-7130-cib";
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reg = <0x10700 0x0000e000 0x0 0x8>, /* RAW */
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<0x10700 0x0000e100 0x0 0x8>; /* EN */
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cavium,max-bits = <23>;
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interrupt-controller;
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interrupt-parent = <&ciu>;
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interrupts = <1 24>;
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/* Interrupts are specified by two parts:
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* 1) Bit number in the CIB* registers
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* 2) Triggering (1 - edge rising
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* 2 - edge falling
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* 4 - level active high
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* 8 - level active low)
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*/
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#interrupt-cells = <2>;
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};
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+69
-4
@@ -54,6 +54,7 @@ config MIPS
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select CPU_PM if CPU_IDLE
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select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
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select ARCH_BINFMT_ELF_STATE
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select SYSCTL_EXCEPTION_TRACE
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menu "Machine selection"
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@@ -376,8 +377,10 @@ config MIPS_MALTA
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS32_R3_5
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select SYS_HAS_CPU_MIPS32_R6
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select SYS_HAS_CPU_MIPS64_R1
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select SYS_HAS_CPU_MIPS64_R2
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select SYS_HAS_CPU_MIPS64_R6
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select SYS_HAS_CPU_NEVADA
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select SYS_HAS_CPU_RM7000
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select SYS_SUPPORTS_32BIT_KERNEL
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@@ -1033,6 +1036,9 @@ config MIPS_MACHINE
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config NO_IOPORT_MAP
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def_bool n
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config GENERIC_CSUM
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bool
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config GENERIC_ISA_DMA
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bool
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select ZONE_DMA if GENERIC_ISA_DMA_SUPPORT_BROKEN=n
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@@ -1146,6 +1152,9 @@ config SOC_PNX8335
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bool
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select SOC_PNX833X
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config MIPS_SPRAM
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bool
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config SWAP_IO_SPACE
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bool
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@@ -1304,6 +1313,22 @@ config CPU_MIPS32_R2
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specific type of processor in your system, choose those that one
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otherwise CPU_MIPS32_R1 is a safe bet for any MIPS32 system.
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config CPU_MIPS32_R6
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bool "MIPS32 Release 6 (EXPERIMENTAL)"
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depends on SYS_HAS_CPU_MIPS32_R6
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select CPU_HAS_PREFETCH
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_MSA
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select GENERIC_CSUM
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select HAVE_KVM
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select MIPS_O32_FP64_SUPPORT
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help
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Choose this option to build a kernel for release 6 or later of the
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MIPS32 architecture. New MIPS processors, starting with the Warrior
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family, are based on a MIPS32r6 processor. If you own an older
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processor, you probably need to select MIPS32r1 or MIPS32r2 instead.
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|
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config CPU_MIPS64_R1
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bool "MIPS64 Release 1"
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depends on SYS_HAS_CPU_MIPS64_R1
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@@ -1339,6 +1364,21 @@ config CPU_MIPS64_R2
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specific type of processor in your system, choose those that one
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otherwise CPU_MIPS64_R1 is a safe bet for any MIPS64 system.
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config CPU_MIPS64_R6
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bool "MIPS64 Release 6 (EXPERIMENTAL)"
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depends on SYS_HAS_CPU_MIPS64_R6
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select CPU_HAS_PREFETCH
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select CPU_SUPPORTS_32BIT_KERNEL
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select CPU_SUPPORTS_64BIT_KERNEL
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select CPU_SUPPORTS_HIGHMEM
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select CPU_SUPPORTS_MSA
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select GENERIC_CSUM
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help
|
||||
Choose this option to build a kernel for release 6 or later of the
|
||||
MIPS64 architecture. New MIPS processors, starting with the Warrior
|
||||
family, are based on a MIPS64r6 processor. If you own an older
|
||||
processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
|
||||
|
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config CPU_R3000
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bool "R3000"
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depends on SYS_HAS_CPU_R3000
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@@ -1539,7 +1579,7 @@ endchoice
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config CPU_MIPS32_3_5_FEATURES
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bool "MIPS32 Release 3.5 Features"
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depends on SYS_HAS_CPU_MIPS32_R3_5
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depends on CPU_MIPS32_R2
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depends on CPU_MIPS32_R2 || CPU_MIPS32_R6
|
||||
help
|
||||
Choose this option to build a kernel for release 2 or later of the
|
||||
MIPS32 architecture including features from the 3.5 release such as
|
||||
@@ -1659,12 +1699,18 @@ config SYS_HAS_CPU_MIPS32_R2
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config SYS_HAS_CPU_MIPS32_R3_5
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bool
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config SYS_HAS_CPU_MIPS32_R6
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bool
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config SYS_HAS_CPU_MIPS64_R1
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bool
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config SYS_HAS_CPU_MIPS64_R2
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bool
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config SYS_HAS_CPU_MIPS64_R6
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bool
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config SYS_HAS_CPU_R3000
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bool
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@@ -1764,11 +1810,11 @@ endmenu
|
||||
#
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config CPU_MIPS32
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bool
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2
|
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default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
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|
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config CPU_MIPS64
|
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bool
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||||
default y if CPU_MIPS64_R1 || CPU_MIPS64_R2
|
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default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
|
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|
||||
#
|
||||
# These two indicate the revision of the architecture, either Release 1 or Release 2
|
||||
@@ -1780,6 +1826,12 @@ config CPU_MIPSR1
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||||
config CPU_MIPSR2
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bool
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||||
default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
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||||
select MIPS_SPRAM
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config CPU_MIPSR6
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bool
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default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
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select MIPS_SPRAM
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|
||||
config EVA
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bool
|
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@@ -2013,6 +2065,19 @@ config MIPS_MT_FPAFF
|
||||
default y
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||||
depends on MIPS_MT_SMP
|
||||
|
||||
config MIPSR2_TO_R6_EMULATOR
|
||||
bool "MIPS R2-to-R6 emulator"
|
||||
depends on CPU_MIPSR6 && !SMP
|
||||
default y
|
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help
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Choose this option if you want to run non-R6 MIPS userland code.
|
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Even if you say 'Y' here, the emulator will still be disabled by
|
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default. You can enable it using the 'mipsr2emul' kernel option.
|
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The only reason this is a build-time option is to save ~14K from the
|
||||
final kernel image.
|
||||
comment "MIPS R2-to-R6 emulator is only available for UP kernels"
|
||||
depends on SMP && CPU_MIPSR6
|
||||
|
||||
config MIPS_VPE_LOADER
|
||||
bool "VPE loader support."
|
||||
depends on SYS_SUPPORTS_MULTITHREADING && MODULES
|
||||
@@ -2148,7 +2213,7 @@ config CPU_HAS_SMARTMIPS
|
||||
here.
|
||||
|
||||
config CPU_MICROMIPS
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||||
depends on 32BIT && SYS_SUPPORTS_MICROMIPS
|
||||
depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6
|
||||
bool "microMIPS"
|
||||
help
|
||||
When this option is enabled the kernel will be built using the
|
||||
|
||||
@@ -122,17 +122,4 @@ config SPINLOCK_TEST
|
||||
help
|
||||
Add several files to the debugfs to test spinlock speed.
|
||||
|
||||
config FP32XX_HYBRID_FPRS
|
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bool "Run FP32 & FPXX code with hybrid FPRs"
|
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depends on MIPS_O32_FP64_SUPPORT
|
||||
help
|
||||
The hybrid FPR scheme is normally used only when a program needs to
|
||||
execute a mix of FP32 & FP64A code, since the trapping & emulation
|
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that it entails is expensive. When enabled, this option will lead
|
||||
to the kernel running programs which use the FP32 & FPXX FP ABIs
|
||||
using the hybrid FPR scheme, which can be useful for debugging
|
||||
purposes.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
endmenu
|
||||
|
||||
+37
-18
@@ -122,26 +122,8 @@ predef-le += -DMIPSEL -D_MIPSEL -D__MIPSEL -D__MIPSEL__
|
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cflags-$(CONFIG_CPU_BIG_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' && echo -EB $(undef-all) $(predef-be))
|
||||
cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += $(shell $(CC) -dumpmachine |grep -q 'mips.*el-.*' || echo -EL $(undef-all) $(predef-le))
|
||||
|
||||
# For smartmips configurations, there are hundreds of warnings due to ISA overrides
|
||||
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards
|
||||
# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
|
||||
# similar directives in the kernel will spam the build logs with the following warnings:
|
||||
# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
|
||||
# or
|
||||
# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
|
||||
# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
|
||||
# been fixed properly.
|
||||
cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,-msmartmips) -Wa,--no-warn
|
||||
cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,-mmicromips)
|
||||
|
||||
cflags-$(CONFIG_SB1XXX_CORELIS) += $(call cc-option,-mno-sched-prolog) \
|
||||
-fno-omit-frame-pointer
|
||||
|
||||
ifeq ($(CONFIG_CPU_HAS_MSA),y)
|
||||
toolchain-msa := $(call cc-option-yn,-mhard-float -mfp64 -Wa$(comma)-mmsa)
|
||||
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
|
||||
endif
|
||||
|
||||
#
|
||||
# CPU-dependent compiler/assembler options for optimization.
|
||||
#
|
||||
@@ -156,10 +138,12 @@ cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS
|
||||
-Wa,-mips32 -Wa,--trap
|
||||
cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
|
||||
-Wa,-mips32r2 -Wa,--trap
|
||||
cflags-$(CONFIG_CPU_MIPS32_R6) += -march=mips32r6 -Wa,--trap
|
||||
cflags-$(CONFIG_CPU_MIPS64_R1) += $(call cc-option,-march=mips64,-mips64 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
|
||||
-Wa,-mips64 -Wa,--trap
|
||||
cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
|
||||
-Wa,-mips64r2 -Wa,--trap
|
||||
cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap
|
||||
cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap
|
||||
cflags-$(CONFIG_CPU_R5432) += $(call cc-option,-march=r5400,-march=r5000) \
|
||||
-Wa,--trap
|
||||
@@ -182,6 +166,16 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
|
||||
endif
|
||||
cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
|
||||
cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap
|
||||
#
|
||||
# binutils from v2.25 on and gcc starting from v4.9.0 treat -march=loongson3a
|
||||
# as MIPS64 R1; older versions as just R1. This leaves the possibility open
|
||||
# that GCC might generate R2 code for -march=loongson3a which then is rejected
|
||||
# by GAS. The cc-option can't probe for this behaviour so -march=loongson3a
|
||||
# can't easily be used safely within the kbuild framework.
|
||||
#
|
||||
cflags-$(CONFIG_CPU_LOONGSON3) += \
|
||||
$(call cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) \
|
||||
-Wa,-mips64r2 -Wa,--trap
|
||||
|
||||
cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
|
||||
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
|
||||
@@ -194,6 +188,23 @@ KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds
|
||||
endif
|
||||
endif
|
||||
|
||||
# For smartmips configurations, there are hundreds of warnings due to ISA overrides
|
||||
# in assembly and header files. smartmips is only supported for MIPS32r1 onwards
|
||||
# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or
|
||||
# similar directives in the kernel will spam the build logs with the following warnings:
|
||||
# Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
|
||||
# or
|
||||
# Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
|
||||
# Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has
|
||||
# been fixed properly.
|
||||
mips-cflags := "$(cflags-y)"
|
||||
cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn
|
||||
cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips)
|
||||
ifeq ($(CONFIG_CPU_HAS_MSA),y)
|
||||
toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa)
|
||||
cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA
|
||||
endif
|
||||
|
||||
#
|
||||
# Firmware support
|
||||
#
|
||||
@@ -287,7 +298,11 @@ boot-y += vmlinux.ecoff
|
||||
boot-y += vmlinux.srec
|
||||
ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)
|
||||
boot-y += uImage
|
||||
boot-y += uImage.bin
|
||||
boot-y += uImage.bz2
|
||||
boot-y += uImage.gz
|
||||
boot-y += uImage.lzma
|
||||
boot-y += uImage.lzo
|
||||
endif
|
||||
|
||||
# compressed boot image targets (arch/mips/boot/compressed/)
|
||||
@@ -386,7 +401,11 @@ define archhelp
|
||||
echo ' vmlinuz.bin - Raw binary zboot image'
|
||||
echo ' vmlinuz.srec - SREC zboot image'
|
||||
echo ' uImage - U-Boot image'
|
||||
echo ' uImage.bin - U-Boot image (uncompressed)'
|
||||
echo ' uImage.bz2 - U-Boot image (bz2)'
|
||||
echo ' uImage.gz - U-Boot image (gzip)'
|
||||
echo ' uImage.lzma - U-Boot image (lzma)'
|
||||
echo ' uImage.lzo - U-Boot image (lzo)'
|
||||
echo ' dtbs - Device-tree blobs for enabled boards'
|
||||
echo
|
||||
echo ' These will be default as appropriate for a configured platform.'
|
||||
|
||||
@@ -127,12 +127,20 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
|
||||
t = 396000000;
|
||||
else {
|
||||
t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
|
||||
if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
|
||||
t &= 0x3f;
|
||||
t *= parent_rate;
|
||||
}
|
||||
|
||||
return t;
|
||||
}
|
||||
|
||||
void __init alchemy_set_lpj(void)
|
||||
{
|
||||
preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);
|
||||
preset_lpj /= 2 * HZ;
|
||||
}
|
||||
|
||||
static struct clk_ops alchemy_clkops_cpu = {
|
||||
.recalc_rate = alchemy_clk_cpu_recalc,
|
||||
};
|
||||
@@ -315,17 +323,26 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
|
||||
|
||||
/* lrclk: external synchronous static bus clock ***********************/
|
||||
|
||||
static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
|
||||
static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
|
||||
{
|
||||
/* MEM_STCFG0[15:13] = divisor.
|
||||
/* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
|
||||
* otherwise lrclk=pclk/4.
|
||||
* All other variants: MEM_STCFG0[15:13] = divisor.
|
||||
* L/RCLK = periph_clk / (divisor + 1)
|
||||
* On Au1000, Au1500, Au1100 it's called LCLK,
|
||||
* on later models it's called RCLK, but it's the same thing.
|
||||
*/
|
||||
struct clk *c;
|
||||
unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
|
||||
unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
|
||||
|
||||
v = (v & 7) + 1;
|
||||
switch (t) {
|
||||
case ALCHEMY_CPU_AU1000:
|
||||
case ALCHEMY_CPU_AU1500:
|
||||
v = 4 + ((v >> 11) & 1);
|
||||
break;
|
||||
default: /* all other models */
|
||||
v = ((v >> 13) & 7) + 1;
|
||||
}
|
||||
c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
|
||||
pn, 0, 1, v);
|
||||
if (!IS_ERR(c))
|
||||
@@ -1066,7 +1083,7 @@ static int __init alchemy_clk_init(void)
|
||||
ERRCK(c)
|
||||
|
||||
/* L/RCLK: external static bus clock for synchronous mode */
|
||||
c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
|
||||
c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
|
||||
ERRCK(c)
|
||||
|
||||
/* Frequency dividers 0-5 */
|
||||
|
||||
@@ -34,10 +34,12 @@
|
||||
#include <au1000.h>
|
||||
|
||||
extern void __init board_setup(void);
|
||||
extern void set_cpuspec(void);
|
||||
extern void __init alchemy_set_lpj(void);
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
alchemy_set_lpj();
|
||||
|
||||
if (au1xxx_cpu_needs_config_od())
|
||||
/* Various early Au1xx0 errata corrected by this */
|
||||
set_c0_config(1 << 19); /* Set Config[OD] */
|
||||
|
||||
@@ -180,7 +180,7 @@ static int __init intc_of_init(struct device_node *node,
|
||||
|
||||
static struct of_device_id of_irq_ids[] __initdata = {
|
||||
{ .compatible = "mti,cpu-interrupt-controller",
|
||||
.data = mips_cpu_intc_init },
|
||||
.data = mips_cpu_irq_of_init },
|
||||
{ .compatible = "brcm,bcm3384-intc",
|
||||
.data = intc_of_init },
|
||||
{},
|
||||
|
||||
+47
-2
@@ -23,6 +23,12 @@ strip-flags := $(addprefix --remove-section=,$(drop-sections))
|
||||
|
||||
hostprogs-y := elf2ecoff
|
||||
|
||||
suffix-y := bin
|
||||
suffix-$(CONFIG_KERNEL_BZIP2) := bz2
|
||||
suffix-$(CONFIG_KERNEL_GZIP) := gz
|
||||
suffix-$(CONFIG_KERNEL_LZMA) := lzma
|
||||
suffix-$(CONFIG_KERNEL_LZO) := lzo
|
||||
|
||||
targets := vmlinux.ecoff
|
||||
quiet_cmd_ecoff = ECOFF $@
|
||||
cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
|
||||
@@ -44,14 +50,53 @@ $(obj)/vmlinux.srec: $(VMLINUX) FORCE
|
||||
UIMAGE_LOADADDR = $(VMLINUX_LOAD_ADDRESS)
|
||||
UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS)
|
||||
|
||||
#
|
||||
# Compressed vmlinux images
|
||||
#
|
||||
|
||||
extra-y += vmlinux.bin.bz2
|
||||
extra-y += vmlinux.bin.gz
|
||||
extra-y += vmlinux.bin.lzma
|
||||
extra-y += vmlinux.bin.lzo
|
||||
|
||||
$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,bzip2)
|
||||
|
||||
$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,gzip)
|
||||
|
||||
$(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,lzma)
|
||||
|
||||
$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,lzo)
|
||||
|
||||
#
|
||||
# Compressed u-boot images
|
||||
#
|
||||
|
||||
targets += uImage
|
||||
targets += uImage.bin
|
||||
targets += uImage.bz2
|
||||
targets += uImage.gz
|
||||
targets += uImage.lzma
|
||||
targets += uImage.lzo
|
||||
|
||||
$(obj)/uImage.bin: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,uimage,none)
|
||||
|
||||
$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2 FORCE
|
||||
$(call if_changed,uimage,bzip2)
|
||||
|
||||
$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
|
||||
$(call if_changed,uimage,gzip)
|
||||
|
||||
targets += uImage
|
||||
$(obj)/uImage: $(obj)/uImage.gz FORCE
|
||||
$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma FORCE
|
||||
$(call if_changed,uimage,lzma)
|
||||
|
||||
$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE
|
||||
$(call if_changed,uimage,lzo)
|
||||
|
||||
$(obj)/uImage: $(obj)/uImage.$(suffix-y)
|
||||
@ln -sf $(notdir $<) $@
|
||||
@echo ' Image $@ is ready'
|
||||
|
||||
@@ -268,7 +268,6 @@ int main(int argc, char *argv[])
|
||||
Elf32_Ehdr ex;
|
||||
Elf32_Phdr *ph;
|
||||
Elf32_Shdr *sh;
|
||||
char *shstrtab;
|
||||
int i, pad;
|
||||
struct sect text, data, bss;
|
||||
struct filehdr efh;
|
||||
@@ -336,9 +335,6 @@ int main(int argc, char *argv[])
|
||||
"sh");
|
||||
if (must_convert_endian)
|
||||
convert_elf_shdrs(sh, ex.e_shnum);
|
||||
/* Read in the section string table. */
|
||||
shstrtab = saveRead(infile, sh[ex.e_shstrndx].sh_offset,
|
||||
sh[ex.e_shstrndx].sh_size, "shstrtab");
|
||||
|
||||
/* Figure out if we can cram the program header into an ECOFF
|
||||
header... Basically, we can't handle anything but loadable
|
||||
|
||||
@@ -18,7 +18,7 @@
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/cvmx-ipd-defs.h>
|
||||
#include <asm/octeon/cvmx-mio-defs.h>
|
||||
|
||||
#include <asm/octeon/cvmx-rst-defs.h>
|
||||
|
||||
static u64 f;
|
||||
static u64 rdiv;
|
||||
@@ -39,11 +39,20 @@ void __init octeon_setup_delays(void)
|
||||
|
||||
if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
|
||||
union cvmx_mio_rst_boot rst_boot;
|
||||
|
||||
rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
|
||||
rdiv = rst_boot.s.c_mul; /* CPU clock */
|
||||
sdiv = rst_boot.s.pnr_mul; /* I/O clock */
|
||||
f = (0x8000000000000000ull / sdiv) * 2;
|
||||
} else if (current_cpu_type() == CPU_CAVIUM_OCTEON3) {
|
||||
union cvmx_rst_boot rst_boot;
|
||||
|
||||
rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
|
||||
rdiv = rst_boot.s.c_mul; /* CPU clock */
|
||||
sdiv = rst_boot.s.pnr_mul; /* I/O clock */
|
||||
f = (0x8000000000000000ull / sdiv) * 2;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -276,7 +276,7 @@ void __init plat_swiotlb_setup(void)
|
||||
continue;
|
||||
|
||||
/* These addresses map low for PCI. */
|
||||
if (e->addr > 0x410000000ull && !OCTEON_IS_MODEL(OCTEON_CN6XXX))
|
||||
if (e->addr > 0x410000000ull && !OCTEON_IS_OCTEON2())
|
||||
continue;
|
||||
|
||||
addr_size += e->size;
|
||||
@@ -308,7 +308,7 @@ void __init plat_swiotlb_setup(void)
|
||||
#endif
|
||||
#ifdef CONFIG_USB_OCTEON_OHCI
|
||||
/* OCTEON II ohci is only 32-bit. */
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && max_addr >= 0x100000000ul)
|
||||
if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
|
||||
swiotlbsize = 64 * (1<<20);
|
||||
#endif
|
||||
swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
|
||||
|
||||
@@ -767,7 +767,7 @@ enum cvmx_helper_board_usb_clock_types __cvmx_helper_board_usb_get_clock_type(vo
|
||||
break;
|
||||
}
|
||||
/* Most boards except NIC10e use a 12MHz crystal */
|
||||
if (OCTEON_IS_MODEL(OCTEON_FAM_2))
|
||||
if (OCTEON_IS_OCTEON2())
|
||||
return USB_CLOCK_TYPE_CRYSTAL_12;
|
||||
return USB_CLOCK_TYPE_REF_48;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -41,6 +41,7 @@
|
||||
#include <asm/octeon/octeon.h>
|
||||
#include <asm/octeon/pci-octeon.h>
|
||||
#include <asm/octeon/cvmx-mio-defs.h>
|
||||
#include <asm/octeon/cvmx-rst-defs.h>
|
||||
|
||||
extern struct plat_smp_ops octeon_smp_ops;
|
||||
|
||||
@@ -579,12 +580,10 @@ void octeon_user_io_init(void)
|
||||
/* R/W If set, CVMSEG is available for loads/stores in user
|
||||
* mode. */
|
||||
cvmmemctl.s.cvmsegenau = 0;
|
||||
/* R/W Size of local memory in cache blocks, 54 (6912 bytes)
|
||||
* is max legal value. */
|
||||
cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
|
||||
|
||||
write_c0_cvmmemctl(cvmmemctl.u64);
|
||||
|
||||
/* Setup of CVMSEG is done in kernel-entry-init.h */
|
||||
if (smp_processor_id() == 0)
|
||||
pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
|
||||
CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
|
||||
@@ -615,6 +614,7 @@ void __init prom_init(void)
|
||||
const char *arg;
|
||||
char *p;
|
||||
int i;
|
||||
u64 t;
|
||||
int argc;
|
||||
#ifdef CONFIG_CAVIUM_RESERVE32
|
||||
int64_t addr = -1;
|
||||
@@ -654,15 +654,56 @@ void __init prom_init(void)
|
||||
sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
|
||||
sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
|
||||
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
|
||||
if (OCTEON_IS_OCTEON2()) {
|
||||
/* I/O clock runs at a different rate than the CPU. */
|
||||
union cvmx_mio_rst_boot rst_boot;
|
||||
rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
|
||||
octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
|
||||
} else if (OCTEON_IS_OCTEON3()) {
|
||||
/* I/O clock runs at a different rate than the CPU. */
|
||||
union cvmx_rst_boot rst_boot;
|
||||
rst_boot.u64 = cvmx_read_csr(CVMX_RST_BOOT);
|
||||
octeon_io_clock_rate = 50000000 * rst_boot.s.pnr_mul;
|
||||
} else {
|
||||
octeon_io_clock_rate = sysinfo->cpu_clock_hz;
|
||||
}
|
||||
|
||||
t = read_c0_cvmctl();
|
||||
if ((t & (1ull << 27)) == 0) {
|
||||
/*
|
||||
* Setup the multiplier save/restore code if
|
||||
* CvmCtl[NOMUL] clear.
|
||||
*/
|
||||
void *save;
|
||||
void *save_end;
|
||||
void *restore;
|
||||
void *restore_end;
|
||||
int save_len;
|
||||
int restore_len;
|
||||
int save_max = (char *)octeon_mult_save_end -
|
||||
(char *)octeon_mult_save;
|
||||
int restore_max = (char *)octeon_mult_restore_end -
|
||||
(char *)octeon_mult_restore;
|
||||
if (current_cpu_data.cputype == CPU_CAVIUM_OCTEON3) {
|
||||
save = octeon_mult_save3;
|
||||
save_end = octeon_mult_save3_end;
|
||||
restore = octeon_mult_restore3;
|
||||
restore_end = octeon_mult_restore3_end;
|
||||
} else {
|
||||
save = octeon_mult_save2;
|
||||
save_end = octeon_mult_save2_end;
|
||||
restore = octeon_mult_restore2;
|
||||
restore_end = octeon_mult_restore2_end;
|
||||
}
|
||||
save_len = (char *)save_end - (char *)save;
|
||||
restore_len = (char *)restore_end - (char *)restore;
|
||||
if (!WARN_ON(save_len > save_max ||
|
||||
restore_len > restore_max)) {
|
||||
memcpy(octeon_mult_save, save, save_len);
|
||||
memcpy(octeon_mult_restore, restore, restore_len);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Only enable the LED controller if we're running on a CN38XX, CN58XX,
|
||||
* or CN56XX. The CN30XX and CN31XX don't have an LED controller.
|
||||
@@ -1004,7 +1045,7 @@ EXPORT_SYMBOL(prom_putchar);
|
||||
|
||||
void prom_free_prom_memory(void)
|
||||
{
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
|
||||
if (CAVIUM_OCTEON_DCACHE_PREFETCH_WAR) {
|
||||
/* Check for presence of Core-14449 fix. */
|
||||
u32 insn;
|
||||
u32 *foo;
|
||||
@@ -1026,8 +1067,9 @@ void prom_free_prom_memory(void)
|
||||
panic("No PREF instruction at Core-14449 probe point.");
|
||||
|
||||
if (((insn >> 16) & 0x1f) != 28)
|
||||
panic("Core-14449 WAR not in place (%04x).\n"
|
||||
"Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn);
|
||||
panic("OCTEON II DCache prefetch workaround not in place (%04x).\n"
|
||||
"Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).",
|
||||
insn);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,193 @@
|
||||
CONFIG_MIPS_MALTA=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_MIPS32_R6=y
|
||||
CONFIG_PAGE_SIZE_16KB=y
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_SYSCTL_SYSCALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PCI=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_XFRM_USER=m
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_NET_IPIP=m
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_PIMSM_V1=y
|
||||
CONFIG_IP_PIMSM_V2=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
CONFIG_INET_AH=m
|
||||
CONFIG_INET_ESP=m
|
||||
CONFIG_INET_IPCOMP=m
|
||||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_INET6_AH=m
|
||||
CONFIG_INET6_ESP=m
|
||||
CONFIG_INET6_IPCOMP=m
|
||||
CONFIG_IPV6_TUNNEL=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_ATALK=m
|
||||
CONFIG_DEV_APPLETALK=m
|
||||
CONFIG_IPDDP=m
|
||||
CONFIG_IPDDP_ENCAP=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_NET_SCH_CBQ=m
|
||||
CONFIG_NET_SCH_HTB=m
|
||||
CONFIG_NET_SCH_HFSC=m
|
||||
CONFIG_NET_SCH_PRIO=m
|
||||
CONFIG_NET_SCH_RED=m
|
||||
CONFIG_NET_SCH_SFQ=m
|
||||
CONFIG_NET_SCH_TEQL=m
|
||||
CONFIG_NET_SCH_TBF=m
|
||||
CONFIG_NET_SCH_GRED=m
|
||||
CONFIG_NET_SCH_DSMARK=m
|
||||
CONFIG_NET_SCH_NETEM=m
|
||||
CONFIG_NET_SCH_INGRESS=m
|
||||
CONFIG_NET_CLS_BASIC=m
|
||||
CONFIG_NET_CLS_TCINDEX=m
|
||||
CONFIG_NET_CLS_ROUTE4=m
|
||||
CONFIG_NET_CLS_FW=m
|
||||
CONFIG_NET_CLS_U32=m
|
||||
CONFIG_NET_CLS_RSVP=m
|
||||
CONFIG_NET_CLS_RSVP6=m
|
||||
CONFIG_NET_CLS_ACT=y
|
||||
CONFIG_NET_ACT_POLICE=y
|
||||
CONFIG_NET_CLS_IND=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_IDE=y
|
||||
# CONFIG_IDE_PROC_FS is not set
|
||||
# CONFIG_IDEPCI_PCIBUS_ORDER is not set
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_PIIX=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_3COM is not set
|
||||
# CONFIG_NET_VENDOR_ADAPTEC is not set
|
||||
# CONFIG_NET_VENDOR_ALTEON is not set
|
||||
CONFIG_PCNET32=y
|
||||
# CONFIG_NET_VENDOR_ATHEROS is not set
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_BROCADE is not set
|
||||
# CONFIG_NET_VENDOR_CHELSIO is not set
|
||||
# CONFIG_NET_VENDOR_CISCO is not set
|
||||
# CONFIG_NET_VENDOR_DEC is not set
|
||||
# CONFIG_NET_VENDOR_DLINK is not set
|
||||
# CONFIG_NET_VENDOR_EMULEX is not set
|
||||
# CONFIG_NET_VENDOR_EXAR is not set
|
||||
# CONFIG_NET_VENDOR_HP is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MELLANOX is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_MYRI is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_NVIDIA is not set
|
||||
# CONFIG_NET_VENDOR_OKI is not set
|
||||
# CONFIG_NET_PACKET_ENGINE is not set
|
||||
# CONFIG_NET_VENDOR_QLOGIC is not set
|
||||
# CONFIG_NET_VENDOR_REALTEK is not set
|
||||
# CONFIG_NET_VENDOR_RDC is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SILAN is not set
|
||||
# CONFIG_NET_VENDOR_SIS is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_SUN is not set
|
||||
# CONFIG_NET_VENDOR_TEHUTI is not set
|
||||
# CONFIG_NET_VENDOR_TI is not set
|
||||
# CONFIG_NET_VENDOR_TOSHIBA is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_LEGACY_PTY_COUNT=4
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
CONFIG_FB_MATROX=y
|
||||
CONFIG_FB_MATROX_G=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_UHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_IDE_DISK=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_CMOS=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_XFS_FS=y
|
||||
CONFIG_XFS_QUOTA=y
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QFMT_V2=y
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CIFS=m
|
||||
CONFIG_CIFS_WEAK_PW_HASH=y
|
||||
CONFIG_CIFS_XATTR=y
|
||||
CONFIG_CIFS_POSIX=y
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CRYPTO_NULL=m
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MICHAEL_MIC=m
|
||||
CONFIG_CRYPTO_SHA512=m
|
||||
CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAST5=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
CONFIG_CRYPTO_SERPENT=m
|
||||
CONFIG_CRYPTO_TEA=m
|
||||
CONFIG_CRYPTO_TWOFISH=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
+16
-10
@@ -9,6 +9,7 @@
|
||||
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
|
||||
* Copyright (C) 1999 Silicon Graphics, Inc.
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irqflags.h>
|
||||
@@ -19,50 +20,55 @@
|
||||
#include <asm/sgialib.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
VOID
|
||||
VOID __noreturn
|
||||
ArcHalt(VOID)
|
||||
{
|
||||
bc_disable();
|
||||
local_irq_disable();
|
||||
ARC_CALL0(halt);
|
||||
never: goto never;
|
||||
|
||||
unreachable();
|
||||
}
|
||||
|
||||
VOID
|
||||
VOID __noreturn
|
||||
ArcPowerDown(VOID)
|
||||
{
|
||||
bc_disable();
|
||||
local_irq_disable();
|
||||
ARC_CALL0(pdown);
|
||||
never: goto never;
|
||||
|
||||
unreachable();
|
||||
}
|
||||
|
||||
/* XXX is this a soft reset basically? XXX */
|
||||
VOID
|
||||
VOID __noreturn
|
||||
ArcRestart(VOID)
|
||||
{
|
||||
bc_disable();
|
||||
local_irq_disable();
|
||||
ARC_CALL0(restart);
|
||||
never: goto never;
|
||||
|
||||
unreachable();
|
||||
}
|
||||
|
||||
VOID
|
||||
VOID __noreturn
|
||||
ArcReboot(VOID)
|
||||
{
|
||||
bc_disable();
|
||||
local_irq_disable();
|
||||
ARC_CALL0(reboot);
|
||||
never: goto never;
|
||||
|
||||
unreachable();
|
||||
}
|
||||
|
||||
VOID
|
||||
VOID __noreturn
|
||||
ArcEnterInteractiveMode(VOID)
|
||||
{
|
||||
bc_disable();
|
||||
local_irq_disable();
|
||||
ARC_CALL0(imode);
|
||||
never: goto never;
|
||||
|
||||
unreachable();
|
||||
}
|
||||
|
||||
LONG
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
# MIPS headers
|
||||
generic-(CONFIG_GENERIC_CSUM) += checksum.h
|
||||
generic-y += cputime.h
|
||||
generic-y += current.h
|
||||
generic-y += dma-contiguous.h
|
||||
|
||||
@@ -19,7 +19,7 @@
|
||||
#include <asm/asmmacro-64.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
.macro local_irq_enable reg=t0
|
||||
ei
|
||||
irq_enable_hazard
|
||||
@@ -104,7 +104,8 @@
|
||||
.endm
|
||||
|
||||
.macro fpu_save_double thread status tmp
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
sll \tmp, \status, 5
|
||||
bgez \tmp, 10f
|
||||
fpu_save_16odd \thread
|
||||
@@ -160,7 +161,8 @@
|
||||
.endm
|
||||
|
||||
.macro fpu_restore_double thread status tmp
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
|
||||
#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
|
||||
defined(CONFIG_CPU_MIPS32_R6)
|
||||
sll \tmp, \status, 5
|
||||
bgez \tmp, 10f # 16 register mode?
|
||||
|
||||
@@ -170,16 +172,16 @@
|
||||
fpu_restore_16even \thread \tmp
|
||||
.endm
|
||||
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
.macro _EXT rd, rs, p, s
|
||||
ext \rd, \rs, \p, \s
|
||||
.endm
|
||||
#else /* !CONFIG_CPU_MIPSR2 */
|
||||
#else /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
|
||||
.macro _EXT rd, rs, p, s
|
||||
srl \rd, \rs, \p
|
||||
andi \rd, \rd, (1 << \s) - 1
|
||||
.endm
|
||||
#endif /* !CONFIG_CPU_MIPSR2 */
|
||||
#endif /* !CONFIG_CPU_MIPSR2 || !CONFIG_CPU_MIPSR6 */
|
||||
|
||||
/*
|
||||
* Temporary until all gas have MT ASE support
|
||||
@@ -304,7 +306,7 @@
|
||||
.set push
|
||||
.set noat
|
||||
SET_HARDFLOAT
|
||||
add $1, \base, \off
|
||||
addu $1, \base, \off
|
||||
.word LDD_MSA_INSN | (\wd << 6)
|
||||
.set pop
|
||||
.endm
|
||||
@@ -313,7 +315,7 @@
|
||||
.set push
|
||||
.set noat
|
||||
SET_HARDFLOAT
|
||||
add $1, \base, \off
|
||||
addu $1, \base, \off
|
||||
.word STD_MSA_INSN | (\wd << 6)
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
@@ -54,19 +54,19 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \
|
||||
" sc %0, %1 \n" \
|
||||
" beqzl %0, 1b \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i)); \
|
||||
} else if (kernel_uses_llsc) { \
|
||||
int temp; \
|
||||
\
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set arch=r4000 \n" \
|
||||
" .set "MIPS_ISA_LEVEL" \n" \
|
||||
" ll %0, %1 # atomic_" #op "\n" \
|
||||
" " #asm_op " %0, %2 \n" \
|
||||
" sc %0, %1 \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i)); \
|
||||
} while (unlikely(!temp)); \
|
||||
} else { \
|
||||
@@ -97,20 +97,20 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \
|
||||
" " #asm_op " %0, %1, %3 \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (result), "=&r" (temp), \
|
||||
"+" GCC_OFF12_ASM() (v->counter) \
|
||||
"+" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i)); \
|
||||
} else if (kernel_uses_llsc) { \
|
||||
int temp; \
|
||||
\
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set arch=r4000 \n" \
|
||||
" .set "MIPS_ISA_LEVEL" \n" \
|
||||
" ll %1, %2 # atomic_" #op "_return \n" \
|
||||
" " #asm_op " %0, %1, %3 \n" \
|
||||
" sc %0, %2 \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (result), "=&r" (temp), \
|
||||
"+" GCC_OFF12_ASM() (v->counter) \
|
||||
"+" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i)); \
|
||||
} while (unlikely(!result)); \
|
||||
\
|
||||
@@ -171,14 +171,14 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
|
||||
"1: \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (result), "=&r" (temp),
|
||||
"+" GCC_OFF12_ASM() (v->counter)
|
||||
: "Ir" (i), GCC_OFF12_ASM() (v->counter)
|
||||
"+" GCC_OFF_SMALL_ASM() (v->counter)
|
||||
: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
|
||||
: "memory");
|
||||
} else if (kernel_uses_llsc) {
|
||||
int temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_LEVEL" \n"
|
||||
"1: ll %1, %2 # atomic_sub_if_positive\n"
|
||||
" subu %0, %1, %3 \n"
|
||||
" bltz %0, 1f \n"
|
||||
@@ -190,7 +190,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
|
||||
"1: \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (result), "=&r" (temp),
|
||||
"+" GCC_OFF12_ASM() (v->counter)
|
||||
"+" GCC_OFF_SMALL_ASM() (v->counter)
|
||||
: "Ir" (i));
|
||||
} else {
|
||||
unsigned long flags;
|
||||
@@ -333,19 +333,19 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \
|
||||
" scd %0, %1 \n" \
|
||||
" beqzl %0, 1b \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i)); \
|
||||
} else if (kernel_uses_llsc) { \
|
||||
long temp; \
|
||||
\
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set arch=r4000 \n" \
|
||||
" .set "MIPS_ISA_LEVEL" \n" \
|
||||
" lld %0, %1 # atomic64_" #op "\n" \
|
||||
" " #asm_op " %0, %2 \n" \
|
||||
" scd %0, %1 \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter) \
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i)); \
|
||||
} while (unlikely(!temp)); \
|
||||
} else { \
|
||||
@@ -376,21 +376,21 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \
|
||||
" " #asm_op " %0, %1, %3 \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (result), "=&r" (temp), \
|
||||
"+" GCC_OFF12_ASM() (v->counter) \
|
||||
"+" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i)); \
|
||||
} else if (kernel_uses_llsc) { \
|
||||
long temp; \
|
||||
\
|
||||
do { \
|
||||
__asm__ __volatile__( \
|
||||
" .set arch=r4000 \n" \
|
||||
" .set "MIPS_ISA_LEVEL" \n" \
|
||||
" lld %1, %2 # atomic64_" #op "_return\n" \
|
||||
" " #asm_op " %0, %1, %3 \n" \
|
||||
" scd %0, %2 \n" \
|
||||
" .set mips0 \n" \
|
||||
: "=&r" (result), "=&r" (temp), \
|
||||
"=" GCC_OFF12_ASM() (v->counter) \
|
||||
: "Ir" (i), GCC_OFF12_ASM() (v->counter) \
|
||||
"=" GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter) \
|
||||
: "memory"); \
|
||||
} while (unlikely(!result)); \
|
||||
\
|
||||
@@ -452,14 +452,14 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
|
||||
"1: \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (result), "=&r" (temp),
|
||||
"=" GCC_OFF12_ASM() (v->counter)
|
||||
: "Ir" (i), GCC_OFF12_ASM() (v->counter)
|
||||
"=" GCC_OFF_SMALL_ASM() (v->counter)
|
||||
: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)
|
||||
: "memory");
|
||||
} else if (kernel_uses_llsc) {
|
||||
long temp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_LEVEL" \n"
|
||||
"1: lld %1, %2 # atomic64_sub_if_positive\n"
|
||||
" dsubu %0, %1, %3 \n"
|
||||
" bltz %0, 1f \n"
|
||||
@@ -471,7 +471,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
|
||||
"1: \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (result), "=&r" (temp),
|
||||
"+" GCC_OFF12_ASM() (v->counter)
|
||||
"+" GCC_OFF_SMALL_ASM() (v->counter)
|
||||
: "Ir" (i));
|
||||
} else {
|
||||
unsigned long flags;
|
||||
|
||||
@@ -79,28 +79,28 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
" " __SC "%0, %1 \n"
|
||||
" beqzl %0, 1b \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "=" GCC_OFF12_ASM() (*m)
|
||||
: "ir" (1UL << bit), GCC_OFF12_ASM() (*m));
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m));
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" " __LL "%0, %1 # set_bit \n"
|
||||
" " __INS "%0, %3, %2, 1 \n"
|
||||
" " __SC "%0, %1 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (bit), "r" (~0));
|
||||
} while (unlikely(!temp));
|
||||
#endif /* CONFIG_CPU_MIPSR2 */
|
||||
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
|
||||
} else if (kernel_uses_llsc) {
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_ARCH_LEVEL" \n"
|
||||
" " __LL "%0, %1 # set_bit \n"
|
||||
" or %0, %2 \n"
|
||||
" " __SC "%0, %1 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (1UL << bit));
|
||||
} while (unlikely(!temp));
|
||||
} else
|
||||
@@ -131,28 +131,28 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
" " __SC "%0, %1 \n"
|
||||
" beqzl %0, 1b \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (~(1UL << bit)));
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" " __LL "%0, %1 # clear_bit \n"
|
||||
" " __INS "%0, $0, %2, 1 \n"
|
||||
" " __SC "%0, %1 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (bit));
|
||||
} while (unlikely(!temp));
|
||||
#endif /* CONFIG_CPU_MIPSR2 */
|
||||
#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
|
||||
} else if (kernel_uses_llsc) {
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_ARCH_LEVEL" \n"
|
||||
" " __LL "%0, %1 # clear_bit \n"
|
||||
" and %0, %2 \n"
|
||||
" " __SC "%0, %1 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (~(1UL << bit)));
|
||||
} while (unlikely(!temp));
|
||||
} else
|
||||
@@ -197,7 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
" " __SC "%0, %1 \n"
|
||||
" beqzl %0, 1b \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (1UL << bit));
|
||||
} else if (kernel_uses_llsc) {
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
|
||||
@@ -205,12 +205,12 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_ARCH_LEVEL" \n"
|
||||
" " __LL "%0, %1 # change_bit \n"
|
||||
" xor %0, %2 \n"
|
||||
" " __SC "%0, %1 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)
|
||||
: "ir" (1UL << bit));
|
||||
} while (unlikely(!temp));
|
||||
} else
|
||||
@@ -245,7 +245,7 @@ static inline int test_and_set_bit(unsigned long nr,
|
||||
" beqzl %2, 1b \n"
|
||||
" and %2, %0, %3 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "r" (1UL << bit)
|
||||
: "memory");
|
||||
} else if (kernel_uses_llsc) {
|
||||
@@ -254,12 +254,12 @@ static inline int test_and_set_bit(unsigned long nr,
|
||||
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_ARCH_LEVEL" \n"
|
||||
" " __LL "%0, %1 # test_and_set_bit \n"
|
||||
" or %2, %0, %3 \n"
|
||||
" " __SC "%2, %1 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "r" (1UL << bit)
|
||||
: "memory");
|
||||
} while (unlikely(!res));
|
||||
@@ -308,12 +308,12 @@ static inline int test_and_set_bit_lock(unsigned long nr,
|
||||
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_ARCH_LEVEL" \n"
|
||||
" " __LL "%0, %1 # test_and_set_bit \n"
|
||||
" or %2, %0, %3 \n"
|
||||
" " __SC "%2, %1 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "r" (1UL << bit)
|
||||
: "memory");
|
||||
} while (unlikely(!res));
|
||||
@@ -355,10 +355,10 @@ static inline int test_and_clear_bit(unsigned long nr,
|
||||
" beqzl %2, 1b \n"
|
||||
" and %2, %0, %3 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "r" (1UL << bit)
|
||||
: "memory");
|
||||
#ifdef CONFIG_CPU_MIPSR2
|
||||
#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
|
||||
} else if (kernel_uses_llsc && __builtin_constant_p(nr)) {
|
||||
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
|
||||
unsigned long temp;
|
||||
@@ -369,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr,
|
||||
" " __EXT "%2, %0, %3, 1 \n"
|
||||
" " __INS "%0, $0, %3, 1 \n"
|
||||
" " __SC "%0, %1 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "ir" (bit)
|
||||
: "memory");
|
||||
} while (unlikely(!temp));
|
||||
@@ -380,13 +380,13 @@ static inline int test_and_clear_bit(unsigned long nr,
|
||||
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_ARCH_LEVEL" \n"
|
||||
" " __LL "%0, %1 # test_and_clear_bit \n"
|
||||
" or %2, %0, %3 \n"
|
||||
" xor %2, %3 \n"
|
||||
" " __SC "%2, %1 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "r" (1UL << bit)
|
||||
: "memory");
|
||||
} while (unlikely(!res));
|
||||
@@ -428,7 +428,7 @@ static inline int test_and_change_bit(unsigned long nr,
|
||||
" beqzl %2, 1b \n"
|
||||
" and %2, %0, %3 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "r" (1UL << bit)
|
||||
: "memory");
|
||||
} else if (kernel_uses_llsc) {
|
||||
@@ -437,12 +437,12 @@ static inline int test_and_change_bit(unsigned long nr,
|
||||
|
||||
do {
|
||||
__asm__ __volatile__(
|
||||
" .set arch=r4000 \n"
|
||||
" .set "MIPS_ISA_ARCH_LEVEL" \n"
|
||||
" " __LL "%0, %1 # test_and_change_bit \n"
|
||||
" xor %2, %0, %3 \n"
|
||||
" " __SC "\t%2, %1 \n"
|
||||
" .set mips0 \n"
|
||||
: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)
|
||||
: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)
|
||||
: "r" (1UL << bit)
|
||||
: "memory");
|
||||
} while (unlikely(!res));
|
||||
@@ -485,7 +485,7 @@ static inline unsigned long __fls(unsigned long word)
|
||||
__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
|
||||
__asm__(
|
||||
" .set push \n"
|
||||
" .set mips32 \n"
|
||||
" .set "MIPS_ISA_LEVEL" \n"
|
||||
" clz %0, %1 \n"
|
||||
" .set pop \n"
|
||||
: "=r" (num)
|
||||
@@ -498,7 +498,7 @@ static inline unsigned long __fls(unsigned long word)
|
||||
__builtin_constant_p(cpu_has_mips64) && cpu_has_mips64) {
|
||||
__asm__(
|
||||
" .set push \n"
|
||||
" .set mips64 \n"
|
||||
" .set "MIPS_ISA_LEVEL" \n"
|
||||
" dclz %0, %1 \n"
|
||||
" .set pop \n"
|
||||
: "=r" (num)
|
||||
@@ -562,7 +562,7 @@ static inline int fls(int x)
|
||||
if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
|
||||
__asm__(
|
||||
" .set push \n"
|
||||
" .set mips32 \n"
|
||||
" .set "MIPS_ISA_LEVEL" \n"
|
||||
" clz %0, %1 \n"
|
||||
" .set pop \n"
|
||||
: "=r" (x)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user