mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
rapidio/tsi721: add DMA engine support
Adds support for DMA Engine API into Tsi721 mport driver. Includes following changes for Tsi721 driver: - Modifies BDMA register offset definitions to support per-channel handling - Separates BDMA channel reserved for RIO Maintenance requests - Adds DMA Engine callback routines Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Vinod Koul <vinod.koul@intel.com> Cc: Li Yang <leoli@freescale.com> Cc: Matt Porter <mporter@kernel.crashing.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Alexandre Bounine
committed by
Linus Torvalds
Linus Torvalds
parent
e42d98ebe7
commit
9eaa3d9bb2
@@ -3,3 +3,6 @@
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#
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obj-$(CONFIG_RAPIDIO_TSI721) += tsi721.o
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ifeq ($(CONFIG_RAPIDIO_DMA_ENGINE),y)
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obj-$(CONFIG_RAPIDIO_TSI721) += tsi721_dma.o
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endif
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@@ -108,6 +108,7 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
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u16 destid, u8 hopcount, u32 offset, int len,
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u32 *data, int do_wr)
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{
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void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id);
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struct tsi721_dma_desc *bd_ptr;
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u32 rd_count, swr_ptr, ch_stat;
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int i, err = 0;
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@@ -116,10 +117,9 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
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if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32)))
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return -EINVAL;
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bd_ptr = priv->bdma[TSI721_DMACH_MAINT].bd_base;
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bd_ptr = priv->mdma.bd_base;
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rd_count = ioread32(
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priv->regs + TSI721_DMAC_DRDCNT(TSI721_DMACH_MAINT));
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rd_count = ioread32(regs + TSI721_DMAC_DRDCNT);
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/* Initialize DMA descriptor */
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bd_ptr[0].type_id = cpu_to_le32((DTYPE2 << 29) | (op << 19) | destid);
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@@ -134,19 +134,18 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
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mb();
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/* Start DMA operation */
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iowrite32(rd_count + 2,
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priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
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ioread32(priv->regs + TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
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iowrite32(rd_count + 2, regs + TSI721_DMAC_DWRCNT);
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ioread32(regs + TSI721_DMAC_DWRCNT);
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i = 0;
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/* Wait until DMA transfer is finished */
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while ((ch_stat = ioread32(priv->regs +
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TSI721_DMAC_STS(TSI721_DMACH_MAINT))) & TSI721_DMAC_STS_RUN) {
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while ((ch_stat = ioread32(regs + TSI721_DMAC_STS))
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& TSI721_DMAC_STS_RUN) {
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udelay(1);
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if (++i >= 5000000) {
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dev_dbg(&priv->pdev->dev,
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"%s : DMA[%d] read timeout ch_status=%x\n",
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__func__, TSI721_DMACH_MAINT, ch_stat);
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__func__, priv->mdma.ch_id, ch_stat);
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if (!do_wr)
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*data = 0xffffffff;
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err = -EIO;
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@@ -162,13 +161,10 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
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__func__, ch_stat);
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dev_dbg(&priv->pdev->dev, "OP=%d : destid=%x hc=%x off=%x\n",
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do_wr ? MAINT_WR : MAINT_RD, destid, hopcount, offset);
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iowrite32(TSI721_DMAC_INT_ALL,
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priv->regs + TSI721_DMAC_INT(TSI721_DMACH_MAINT));
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iowrite32(TSI721_DMAC_CTL_INIT,
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priv->regs + TSI721_DMAC_CTL(TSI721_DMACH_MAINT));
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iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
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iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
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udelay(10);
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iowrite32(0, priv->regs +
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TSI721_DMAC_DWRCNT(TSI721_DMACH_MAINT));
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iowrite32(0, regs + TSI721_DMAC_DWRCNT);
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udelay(1);
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if (!do_wr)
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*data = 0xffffffff;
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@@ -184,8 +180,8 @@ static int tsi721_maint_dma(struct tsi721_device *priv, u32 sys_size,
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* NOTE: Skipping check and clear FIFO entries because we are waiting
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* for transfer to be completed.
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*/
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swr_ptr = ioread32(priv->regs + TSI721_DMAC_DSWP(TSI721_DMACH_MAINT));
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iowrite32(swr_ptr, priv->regs + TSI721_DMAC_DSRP(TSI721_DMACH_MAINT));
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swr_ptr = ioread32(regs + TSI721_DMAC_DSWP);
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iowrite32(swr_ptr, regs + TSI721_DMAC_DSRP);
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err_out:
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return err;
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@@ -541,6 +537,22 @@ static irqreturn_t tsi721_irqhandler(int irq, void *ptr)
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tsi721_pw_handler(mport);
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}
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#ifdef CONFIG_RAPIDIO_DMA_ENGINE
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if (dev_int & TSI721_DEV_INT_BDMA_CH) {
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int ch;
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if (dev_ch_int & TSI721_INT_BDMA_CHAN_M) {
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dev_dbg(&priv->pdev->dev,
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"IRQ from DMA channel 0x%08x\n", dev_ch_int);
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for (ch = 0; ch < TSI721_DMA_MAXCH; ch++) {
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if (!(dev_ch_int & TSI721_INT_BDMA_CHAN(ch)))
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continue;
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tsi721_bdma_handler(&priv->bdma[ch]);
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}
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}
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}
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#endif
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return IRQ_HANDLED;
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}
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@@ -553,18 +565,26 @@ static void tsi721_interrupts_init(struct tsi721_device *priv)
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priv->regs + TSI721_SR_CHINT(IDB_QUEUE));
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iowrite32(TSI721_SR_CHINT_IDBQRCV,
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priv->regs + TSI721_SR_CHINTE(IDB_QUEUE));
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iowrite32(TSI721_INT_SR2PC_CHAN(IDB_QUEUE),
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priv->regs + TSI721_DEV_CHAN_INTE);
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/* Enable SRIO MAC interrupts */
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iowrite32(TSI721_RIO_EM_DEV_INT_EN_INT,
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priv->regs + TSI721_RIO_EM_DEV_INT_EN);
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/* Enable interrupts from channels in use */
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#ifdef CONFIG_RAPIDIO_DMA_ENGINE
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intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE) |
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(TSI721_INT_BDMA_CHAN_M &
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~TSI721_INT_BDMA_CHAN(TSI721_DMACH_MAINT));
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#else
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intr = TSI721_INT_SR2PC_CHAN(IDB_QUEUE);
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#endif
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iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE);
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if (priv->flags & TSI721_USING_MSIX)
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intr = TSI721_DEV_INT_SRIO;
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else
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intr = TSI721_DEV_INT_SR2PC_CH | TSI721_DEV_INT_SRIO |
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TSI721_DEV_INT_SMSG_CH;
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TSI721_DEV_INT_SMSG_CH | TSI721_DEV_INT_BDMA_CH;
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iowrite32(intr, priv->regs + TSI721_DEV_INTE);
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ioread32(priv->regs + TSI721_DEV_INTE);
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@@ -715,12 +735,29 @@ static int tsi721_enable_msix(struct tsi721_device *priv)
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TSI721_MSIX_OMSG_INT(i);
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}
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#ifdef CONFIG_RAPIDIO_DMA_ENGINE
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/*
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* Initialize MSI-X entries for Block DMA Engine:
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* this driver supports XXX DMA channels
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* (one is reserved for SRIO maintenance transactions)
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*/
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for (i = 0; i < TSI721_DMA_CHNUM; i++) {
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entries[TSI721_VECT_DMA0_DONE + i].entry =
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TSI721_MSIX_DMACH_DONE(i);
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entries[TSI721_VECT_DMA0_INT + i].entry =
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TSI721_MSIX_DMACH_INT(i);
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}
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#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
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err = pci_enable_msix(priv->pdev, entries, ARRAY_SIZE(entries));
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if (err) {
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if (err > 0)
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dev_info(&priv->pdev->dev,
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"Only %d MSI-X vectors available, "
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"not using MSI-X\n", err);
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else
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dev_err(&priv->pdev->dev,
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"Failed to enable MSI-X (err=%d)\n", err);
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return err;
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}
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@@ -760,6 +797,22 @@ static int tsi721_enable_msix(struct tsi721_device *priv)
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i, pci_name(priv->pdev));
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}
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#ifdef CONFIG_RAPIDIO_DMA_ENGINE
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for (i = 0; i < TSI721_DMA_CHNUM; i++) {
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priv->msix[TSI721_VECT_DMA0_DONE + i].vector =
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entries[TSI721_VECT_DMA0_DONE + i].vector;
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snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name,
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IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s",
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i, pci_name(priv->pdev));
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priv->msix[TSI721_VECT_DMA0_INT + i].vector =
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entries[TSI721_VECT_DMA0_INT + i].vector;
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snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name,
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IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s",
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i, pci_name(priv->pdev));
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}
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#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
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return 0;
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}
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#endif /* CONFIG_PCI_MSI */
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@@ -888,20 +941,34 @@ static void tsi721_doorbell_free(struct tsi721_device *priv)
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priv->idb_base = NULL;
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}
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static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
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/**
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* tsi721_bdma_maint_init - Initialize maintenance request BDMA channel.
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* @priv: pointer to tsi721 private data
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*
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* Initialize BDMA channel allocated for RapidIO maintenance read/write
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* request generation
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* Returns %0 on success or %-ENOMEM on failure.
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*/
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static int tsi721_bdma_maint_init(struct tsi721_device *priv)
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{
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struct tsi721_dma_desc *bd_ptr;
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u64 *sts_ptr;
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dma_addr_t bd_phys, sts_phys;
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int sts_size;
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int bd_num = priv->bdma[chnum].bd_num;
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int bd_num = 2;
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void __iomem *regs;
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dev_dbg(&priv->pdev->dev, "Init Block DMA Engine, CH%d\n", chnum);
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dev_dbg(&priv->pdev->dev,
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"Init Block DMA Engine for Maintenance requests, CH%d\n",
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TSI721_DMACH_MAINT);
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/*
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* Initialize DMA channel for maintenance requests
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*/
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priv->mdma.ch_id = TSI721_DMACH_MAINT;
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regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT);
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/* Allocate space for DMA descriptors */
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bd_ptr = dma_zalloc_coherent(&priv->pdev->dev,
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bd_num * sizeof(struct tsi721_dma_desc),
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@@ -909,8 +976,9 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
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if (!bd_ptr)
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return -ENOMEM;
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priv->bdma[chnum].bd_phys = bd_phys;
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priv->bdma[chnum].bd_base = bd_ptr;
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priv->mdma.bd_num = bd_num;
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priv->mdma.bd_phys = bd_phys;
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priv->mdma.bd_base = bd_ptr;
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dev_dbg(&priv->pdev->dev, "DMA descriptors @ %p (phys = %llx)\n",
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bd_ptr, (unsigned long long)bd_phys);
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@@ -927,13 +995,13 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
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dma_free_coherent(&priv->pdev->dev,
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bd_num * sizeof(struct tsi721_dma_desc),
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bd_ptr, bd_phys);
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priv->bdma[chnum].bd_base = NULL;
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priv->mdma.bd_base = NULL;
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return -ENOMEM;
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}
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priv->bdma[chnum].sts_phys = sts_phys;
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priv->bdma[chnum].sts_base = sts_ptr;
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priv->bdma[chnum].sts_size = sts_size;
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priv->mdma.sts_phys = sts_phys;
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priv->mdma.sts_base = sts_ptr;
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priv->mdma.sts_size = sts_size;
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dev_dbg(&priv->pdev->dev,
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"desc status FIFO @ %p (phys = %llx) size=0x%x\n",
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@@ -946,83 +1014,61 @@ static int tsi721_bdma_ch_init(struct tsi721_device *priv, int chnum)
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bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32);
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/* Setup DMA descriptor pointers */
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iowrite32(((u64)bd_phys >> 32),
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priv->regs + TSI721_DMAC_DPTRH(chnum));
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iowrite32(((u64)bd_phys >> 32), regs + TSI721_DMAC_DPTRH);
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iowrite32(((u64)bd_phys & TSI721_DMAC_DPTRL_MASK),
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priv->regs + TSI721_DMAC_DPTRL(chnum));
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regs + TSI721_DMAC_DPTRL);
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/* Setup descriptor status FIFO */
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iowrite32(((u64)sts_phys >> 32),
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priv->regs + TSI721_DMAC_DSBH(chnum));
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iowrite32(((u64)sts_phys >> 32), regs + TSI721_DMAC_DSBH);
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iowrite32(((u64)sts_phys & TSI721_DMAC_DSBL_MASK),
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priv->regs + TSI721_DMAC_DSBL(chnum));
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regs + TSI721_DMAC_DSBL);
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iowrite32(TSI721_DMAC_DSSZ_SIZE(sts_size),
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priv->regs + TSI721_DMAC_DSSZ(chnum));
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regs + TSI721_DMAC_DSSZ);
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/* Clear interrupt bits */
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iowrite32(TSI721_DMAC_INT_ALL,
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priv->regs + TSI721_DMAC_INT(chnum));
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iowrite32(TSI721_DMAC_INT_ALL, regs + TSI721_DMAC_INT);
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ioread32(priv->regs + TSI721_DMAC_INT(chnum));
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ioread32(regs + TSI721_DMAC_INT);
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/* Toggle DMA channel initialization */
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iowrite32(TSI721_DMAC_CTL_INIT, priv->regs + TSI721_DMAC_CTL(chnum));
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ioread32(priv->regs + TSI721_DMAC_CTL(chnum));
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iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
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ioread32(regs + TSI721_DMAC_CTL);
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udelay(10);
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return 0;
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}
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static int tsi721_bdma_ch_free(struct tsi721_device *priv, int chnum)
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static int tsi721_bdma_maint_free(struct tsi721_device *priv)
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{
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u32 ch_stat;
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struct tsi721_bdma_maint *mdma = &priv->mdma;
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void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id);
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if (priv->bdma[chnum].bd_base == NULL)
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if (mdma->bd_base == NULL)
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return 0;
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/* Check if DMA channel still running */
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ch_stat = ioread32(priv->regs + TSI721_DMAC_STS(chnum));
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ch_stat = ioread32(regs + TSI721_DMAC_STS);
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if (ch_stat & TSI721_DMAC_STS_RUN)
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return -EFAULT;
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/* Put DMA channel into init state */
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iowrite32(TSI721_DMAC_CTL_INIT,
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priv->regs + TSI721_DMAC_CTL(chnum));
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iowrite32(TSI721_DMAC_CTL_INIT, regs + TSI721_DMAC_CTL);
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/* Free space allocated for DMA descriptors */
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dma_free_coherent(&priv->pdev->dev,
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priv->bdma[chnum].bd_num * sizeof(struct tsi721_dma_desc),
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priv->bdma[chnum].bd_base, priv->bdma[chnum].bd_phys);
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priv->bdma[chnum].bd_base = NULL;
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mdma->bd_num * sizeof(struct tsi721_dma_desc),
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mdma->bd_base, mdma->bd_phys);
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mdma->bd_base = NULL;
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/* Free space allocated for status FIFO */
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dma_free_coherent(&priv->pdev->dev,
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priv->bdma[chnum].sts_size * sizeof(struct tsi721_dma_sts),
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priv->bdma[chnum].sts_base, priv->bdma[chnum].sts_phys);
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priv->bdma[chnum].sts_base = NULL;
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mdma->sts_size * sizeof(struct tsi721_dma_sts),
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mdma->sts_base, mdma->sts_phys);
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mdma->sts_base = NULL;
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return 0;
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}
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static int tsi721_bdma_init(struct tsi721_device *priv)
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{
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/* Initialize BDMA channel allocated for RapidIO maintenance read/write
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* request generation
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*/
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priv->bdma[TSI721_DMACH_MAINT].bd_num = 2;
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if (tsi721_bdma_ch_init(priv, TSI721_DMACH_MAINT)) {
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dev_err(&priv->pdev->dev, "Unable to initialize maintenance DMA"
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" channel %d, aborting\n", TSI721_DMACH_MAINT);
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return -ENOMEM;
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}
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return 0;
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}
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static void tsi721_bdma_free(struct tsi721_device *priv)
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{
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tsi721_bdma_ch_free(priv, TSI721_DMACH_MAINT);
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}
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/* Enable Inbound Messaging Interrupts */
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static void
|
||||
tsi721_imsg_interrupt_enable(struct tsi721_device *priv, int ch,
|
||||
@@ -2035,7 +2081,8 @@ static void tsi721_disable_ints(struct tsi721_device *priv)
|
||||
|
||||
/* Disable all BDMA Channel interrupts */
|
||||
for (ch = 0; ch < TSI721_DMA_MAXCH; ch++)
|
||||
iowrite32(0, priv->regs + TSI721_DMAC_INTE(ch));
|
||||
iowrite32(0,
|
||||
priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE);
|
||||
|
||||
/* Disable all general BDMA interrupts */
|
||||
iowrite32(0, priv->regs + TSI721_BDMA_INTE);
|
||||
@@ -2104,6 +2151,7 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
|
||||
mport->phy_type = RIO_PHY_SERIAL;
|
||||
mport->priv = (void *)priv;
|
||||
mport->phys_efptr = 0x100;
|
||||
priv->mport = mport;
|
||||
|
||||
INIT_LIST_HEAD(&mport->dbells);
|
||||
|
||||
@@ -2129,17 +2177,21 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
|
||||
if (!err) {
|
||||
tsi721_interrupts_init(priv);
|
||||
ops->pwenable = tsi721_pw_enable;
|
||||
} else
|
||||
} else {
|
||||
dev_err(&pdev->dev, "Unable to get assigned PCI IRQ "
|
||||
"vector %02X err=0x%x\n", pdev->irq, err);
|
||||
goto err_exit;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
tsi721_register_dma(priv);
|
||||
#endif
|
||||
/* Enable SRIO link */
|
||||
iowrite32(ioread32(priv->regs + TSI721_DEVCTL) |
|
||||
TSI721_DEVCTL_SRBOOT_CMPL,
|
||||
priv->regs + TSI721_DEVCTL);
|
||||
|
||||
rio_register_mport(mport);
|
||||
priv->mport = mport;
|
||||
|
||||
if (mport->host_deviceid >= 0)
|
||||
iowrite32(RIO_PORT_GEN_HOST | RIO_PORT_GEN_MASTER |
|
||||
@@ -2149,6 +2201,11 @@ static int __devinit tsi721_setup_mport(struct tsi721_device *priv)
|
||||
iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR));
|
||||
|
||||
return 0;
|
||||
|
||||
err_exit:
|
||||
kfree(mport);
|
||||
kfree(ops);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __devinit tsi721_probe(struct pci_dev *pdev,
|
||||
@@ -2294,7 +2351,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
|
||||
tsi721_init_pc2sr_mapping(priv);
|
||||
tsi721_init_sr2pc_mapping(priv);
|
||||
|
||||
if (tsi721_bdma_init(priv)) {
|
||||
if (tsi721_bdma_maint_init(priv)) {
|
||||
dev_err(&pdev->dev, "BDMA initialization failed, aborting\n");
|
||||
err = -ENOMEM;
|
||||
goto err_unmap_bars;
|
||||
@@ -2319,7 +2376,7 @@ static int __devinit tsi721_probe(struct pci_dev *pdev,
|
||||
err_free_consistent:
|
||||
tsi721_doorbell_free(priv);
|
||||
err_free_bdma:
|
||||
tsi721_bdma_free(priv);
|
||||
tsi721_bdma_maint_free(priv);
|
||||
err_unmap_bars:
|
||||
if (priv->regs)
|
||||
iounmap(priv->regs);
|
||||
|
||||
@@ -167,6 +167,8 @@
|
||||
#define TSI721_DEV_INTE 0x29840
|
||||
#define TSI721_DEV_INT 0x29844
|
||||
#define TSI721_DEV_INTSET 0x29848
|
||||
#define TSI721_DEV_INT_BDMA_CH 0x00002000
|
||||
#define TSI721_DEV_INT_BDMA_NCH 0x00001000
|
||||
#define TSI721_DEV_INT_SMSG_CH 0x00000800
|
||||
#define TSI721_DEV_INT_SMSG_NCH 0x00000400
|
||||
#define TSI721_DEV_INT_SR2PC_CH 0x00000200
|
||||
@@ -181,6 +183,8 @@
|
||||
#define TSI721_INT_IMSG_CHAN(x) (1 << (16 + (x)))
|
||||
#define TSI721_INT_OMSG_CHAN_M 0x0000ff00
|
||||
#define TSI721_INT_OMSG_CHAN(x) (1 << (8 + (x)))
|
||||
#define TSI721_INT_BDMA_CHAN_M 0x000000ff
|
||||
#define TSI721_INT_BDMA_CHAN(x) (1 << (x))
|
||||
|
||||
/*
|
||||
* PC2SR block registers
|
||||
@@ -235,14 +239,16 @@
|
||||
* x = 0..7
|
||||
*/
|
||||
|
||||
#define TSI721_DMAC_DWRCNT(x) (0x51000 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DRDCNT(x) (0x51004 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_BASE(x) (0x51000 + (x) * 0x1000)
|
||||
|
||||
#define TSI721_DMAC_CTL(x) (0x51008 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DWRCNT 0x000
|
||||
#define TSI721_DMAC_DRDCNT 0x004
|
||||
|
||||
#define TSI721_DMAC_CTL 0x008
|
||||
#define TSI721_DMAC_CTL_SUSP 0x00000002
|
||||
#define TSI721_DMAC_CTL_INIT 0x00000001
|
||||
|
||||
#define TSI721_DMAC_INT(x) (0x5100c + (x) * 0x1000)
|
||||
#define TSI721_DMAC_INT 0x00c
|
||||
#define TSI721_DMAC_INT_STFULL 0x00000010
|
||||
#define TSI721_DMAC_INT_DONE 0x00000008
|
||||
#define TSI721_DMAC_INT_SUSP 0x00000004
|
||||
@@ -250,34 +256,33 @@
|
||||
#define TSI721_DMAC_INT_IOFDONE 0x00000001
|
||||
#define TSI721_DMAC_INT_ALL 0x0000001f
|
||||
|
||||
#define TSI721_DMAC_INTSET(x) (0x51010 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_INTSET 0x010
|
||||
|
||||
#define TSI721_DMAC_STS(x) (0x51014 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_STS 0x014
|
||||
#define TSI721_DMAC_STS_ABORT 0x00400000
|
||||
#define TSI721_DMAC_STS_RUN 0x00200000
|
||||
#define TSI721_DMAC_STS_CS 0x001f0000
|
||||
|
||||
#define TSI721_DMAC_INTE(x) (0x51018 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_INTE 0x018
|
||||
|
||||
#define TSI721_DMAC_DPTRL(x) (0x51024 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DPTRL 0x024
|
||||
#define TSI721_DMAC_DPTRL_MASK 0xffffffe0
|
||||
|
||||
#define TSI721_DMAC_DPTRH(x) (0x51028 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DPTRH 0x028
|
||||
|
||||
#define TSI721_DMAC_DSBL(x) (0x5102c + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSBL 0x02c
|
||||
#define TSI721_DMAC_DSBL_MASK 0xffffffc0
|
||||
|
||||
#define TSI721_DMAC_DSBH(x) (0x51030 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSBH 0x030
|
||||
|
||||
#define TSI721_DMAC_DSSZ(x) (0x51034 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSSZ 0x034
|
||||
#define TSI721_DMAC_DSSZ_SIZE_M 0x0000000f
|
||||
#define TSI721_DMAC_DSSZ_SIZE(size) (__fls(size) - 4)
|
||||
|
||||
|
||||
#define TSI721_DMAC_DSRP(x) (0x51038 + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSRP 0x038
|
||||
#define TSI721_DMAC_DSRP_MASK 0x0007ffff
|
||||
|
||||
#define TSI721_DMAC_DSWP(x) (0x5103c + (x) * 0x1000)
|
||||
#define TSI721_DMAC_DSWP 0x03c
|
||||
#define TSI721_DMAC_DSWP_MASK 0x0007ffff
|
||||
|
||||
#define TSI721_BDMA_INTE 0x5f000
|
||||
@@ -612,6 +617,8 @@ enum dma_rtype {
|
||||
#define TSI721_DMACH_MAINT 0 /* DMA channel for maint requests */
|
||||
#define TSI721_DMACH_MAINT_NBD 32 /* Number of BDs for maint requests */
|
||||
|
||||
#define TSI721_DMACH_DMA 1 /* DMA channel for data transfers */
|
||||
|
||||
#define MSG_DMA_ENTRY_INX_TO_SIZE(x) ((0x10 << (x)) & 0xFFFF0)
|
||||
|
||||
enum tsi721_smsg_int_flag {
|
||||
@@ -626,7 +633,48 @@ enum tsi721_smsg_int_flag {
|
||||
|
||||
/* Structures */
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
|
||||
struct tsi721_tx_desc {
|
||||
struct dma_async_tx_descriptor txd;
|
||||
struct tsi721_dma_desc *hw_desc;
|
||||
u16 destid;
|
||||
/* low 64-bits of 66-bit RIO address */
|
||||
u64 rio_addr;
|
||||
/* upper 2-bits of 66-bit RIO address */
|
||||
u8 rio_addr_u;
|
||||
bool interrupt;
|
||||
struct list_head desc_node;
|
||||
struct list_head tx_list;
|
||||
};
|
||||
|
||||
struct tsi721_bdma_chan {
|
||||
int id;
|
||||
void __iomem *regs;
|
||||
int bd_num; /* number of buffer descriptors */
|
||||
void *bd_base; /* start of DMA descriptors */
|
||||
dma_addr_t bd_phys;
|
||||
void *sts_base; /* start of DMA BD status FIFO */
|
||||
dma_addr_t sts_phys;
|
||||
int sts_size;
|
||||
u32 sts_rdptr;
|
||||
u32 wr_count;
|
||||
u32 wr_count_next;
|
||||
|
||||
struct dma_chan dchan;
|
||||
struct tsi721_tx_desc *tx_desc;
|
||||
spinlock_t lock;
|
||||
struct list_head active_list;
|
||||
struct list_head queue;
|
||||
struct list_head free_list;
|
||||
dma_cookie_t completed_cookie;
|
||||
struct tasklet_struct tasklet;
|
||||
};
|
||||
|
||||
#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
|
||||
|
||||
struct tsi721_bdma_maint {
|
||||
int ch_id; /* BDMA channel number */
|
||||
int bd_num; /* number of buffer descriptors */
|
||||
void *bd_base; /* start of DMA descriptors */
|
||||
dma_addr_t bd_phys;
|
||||
@@ -721,6 +769,24 @@ enum tsi721_msix_vect {
|
||||
TSI721_VECT_IMB1_INT,
|
||||
TSI721_VECT_IMB2_INT,
|
||||
TSI721_VECT_IMB3_INT,
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
TSI721_VECT_DMA0_DONE,
|
||||
TSI721_VECT_DMA1_DONE,
|
||||
TSI721_VECT_DMA2_DONE,
|
||||
TSI721_VECT_DMA3_DONE,
|
||||
TSI721_VECT_DMA4_DONE,
|
||||
TSI721_VECT_DMA5_DONE,
|
||||
TSI721_VECT_DMA6_DONE,
|
||||
TSI721_VECT_DMA7_DONE,
|
||||
TSI721_VECT_DMA0_INT,
|
||||
TSI721_VECT_DMA1_INT,
|
||||
TSI721_VECT_DMA2_INT,
|
||||
TSI721_VECT_DMA3_INT,
|
||||
TSI721_VECT_DMA4_INT,
|
||||
TSI721_VECT_DMA5_INT,
|
||||
TSI721_VECT_DMA6_INT,
|
||||
TSI721_VECT_DMA7_INT,
|
||||
#endif /* CONFIG_RAPIDIO_DMA_ENGINE */
|
||||
TSI721_VECT_MAX
|
||||
};
|
||||
|
||||
@@ -754,7 +820,11 @@ struct tsi721_device {
|
||||
u32 pw_discard_count;
|
||||
|
||||
/* BDMA Engine */
|
||||
struct tsi721_bdma_maint mdma; /* Maintenance rd/wr request channel */
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
struct tsi721_bdma_chan bdma[TSI721_DMA_CHNUM];
|
||||
#endif
|
||||
|
||||
/* Inbound Messaging */
|
||||
int imsg_init[TSI721_IMSG_CHNUM];
|
||||
@@ -765,4 +835,9 @@ struct tsi721_device {
|
||||
struct tsi721_omsg_ring omsg_ring[TSI721_OMSG_CHNUM];
|
||||
};
|
||||
|
||||
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
||||
extern void tsi721_bdma_handler(struct tsi721_bdma_chan *bdma_chan);
|
||||
extern int __devinit tsi721_register_dma(struct tsi721_device *priv);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user