Merge branch 'for-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next

Johan Hedberg says:

====================
pull request: bluetooth-next 2015-05-28

Here's a set of patches intended for 4.2. The majority of the changes
are on the 802.15.4 side of things rather than Bluetooth related:

 - All sorts of cleanups & fixes to ieee802154 and related drivers
 - Rework of tx power support in ieee802154 and its drivers
 - Support for setting ieee802154 tx power through nl802154
 - New IDs for the btusb driver
 - Various cleanups & smaller fixes to btusb
 - New btrtl driver for Realtec devices
 - Fix suspend/resume for Realtek devices

Please let me know if there are any issues pulling. Thanks.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller committed 2015-05-30 23:26:45 -07:00
commit 9d52bf0a23
46 files changed
+2379 -1138

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+11 -21
View File
@@ -30,8 +30,8 @@ int sd = socket(PF_IEEE802154, SOCK_DGRAM, 0);
The address family, socket addresses etc. are defined in the
include/net/af_ieee802154.h header or in the special header
in our userspace package (see either linux-zigbee sourceforge download page
or git tree at git://linux-zigbee.git.sourceforge.net/gitroot/linux-zigbee).
in the userspace package (see either http://wpan.cakelab.org/ or the
git tree at https://github.com/linux-wpan/wpan-tools).
One can use SOCK_RAW for passing raw data towards device xmit function. YMMV.
@@ -49,15 +49,6 @@ Like with WiFi, there are several types of devices implementing IEEE 802.15.4.
Those types of devices require different approach to be hooked into Linux kernel.
MLME - MAC Level Management
============================
Most of IEEE 802.15.4 MLME interfaces are directly mapped on netlink commands.
See the include/net/nl802154.h header. Our userspace tools package
(see above) provides CLI configuration utility for radio interfaces and simple
coordinator for IEEE 802.15.4 networks as an example users of MLME protocol.
HardMAC
=======
@@ -75,8 +66,6 @@ net_device with a pointer to struct ieee802154_mlme_ops instance. The fields
assoc_req, assoc_resp, disassoc_req, start_req, and scan_req are optional.
All other fields are required.
We provide an example of simple HardMAC driver at drivers/ieee802154/fakehard.c
SoftMAC
=======
@@ -89,7 +78,8 @@ stack interface for network sniffers (e.g. WireShark).
This layer is going to be extended soon.
See header include/net/mac802154.h and several drivers in drivers/ieee802154/.
See header include/net/mac802154.h and several drivers in
drivers/net/ieee802154/.
Device drivers API
@@ -114,18 +104,17 @@ Moreover IEEE 802.15.4 device operations structure should be filled.
Fake drivers
============
In addition there are two drivers available which simulate real devices with
HardMAC (fakehard) and SoftMAC (fakelb - IEEE 802.15.4 loopback driver)
interfaces. This option provides possibility to test and debug stack without
usage of real hardware.
In addition there is a driver available which simulates a real device with
SoftMAC (fakelb - IEEE 802.15.4 loopback driver) interface. This option
provides possibility to test and debug stack without usage of real hardware.
See sources in drivers/ieee802154 folder for more details.
See sources in drivers/net/ieee802154 folder for more details.
6LoWPAN Linux implementation
============================
The IEEE 802.15.4 standard specifies an MTU of 128 bytes, yielding about 80
The IEEE 802.15.4 standard specifies an MTU of 127 bytes, yielding about 80
octets of actual MAC payload once security is turned on, on a wireless link
with a link throughput of 250 kbps or less. The 6LoWPAN adaptation format
[RFC4944] was specified to carry IPv6 datagrams over such constrained links,
@@ -140,7 +129,8 @@ In Semptember 2011 the standard update was published - [RFC6282].
It deprecates HC1 and HC2 compression and defines IPHC encoding format which is
used in this Linux implementation.
All the code related to 6lowpan you may find in files: net/ieee802154/6lowpan.*
All the code related to 6lowpan you may find in files: net/6lowpan/*
and net/ieee802154/6lowpan/*
To setup 6lowpan interface you need (busybox release > 1.17.0):
1. Add IEEE802.15.4 interface and initialize PANid;
+15
View File
@@ -9,6 +9,10 @@ config BT_BCM
tristate
select FW_LOADER
config BT_RTL
tristate
select FW_LOADER
config BT_HCIBTUSB
tristate "HCI USB driver"
depends on USB
@@ -32,6 +36,17 @@ config BT_HCIBTUSB_BCM
Say Y here to compile support for Broadcom protocol.
config BT_HCIBTUSB_RTL
bool "Realtek protocol support"
depends on BT_HCIBTUSB
select BT_RTL
default y
help
The Realtek protocol support enables firmware and configuration
download support for Realtek Bluetooth controllers.
Say Y here to compile support for Realtek protocol.
config BT_HCIBTSDIO
tristate "HCI SDIO driver"
depends on MMC
+1
View File
@@ -21,6 +21,7 @@ obj-$(CONFIG_BT_MRVL) += btmrvl.o
obj-$(CONFIG_BT_MRVL_SDIO) += btmrvl_sdio.o
obj-$(CONFIG_BT_WILINK) += btwilink.o
obj-$(CONFIG_BT_BCM) += btbcm.o
obj-$(CONFIG_BT_RTL) += btrtl.o
btmrvl-y := btmrvl_main.o
btmrvl-$(CONFIG_DEBUG_FS) += btmrvl_debugfs.o
-6
View File
@@ -55,12 +55,6 @@ int btbcm_check_bdaddr(struct hci_dev *hdev)
}
bda = (struct hci_rp_read_bd_addr *)skb->data;
if (bda->status) {
BT_ERR("%s: BCM: Device address result failed (%02x)",
hdev->name, bda->status);
kfree_skb(skb);
return -bt_to_errno(bda->status);
}
/* The address 00:20:70:02:A0:00 indicates a BCM20702A0 controller
* with no configured address.
-6
View File
@@ -53,12 +53,6 @@ int btintel_check_bdaddr(struct hci_dev *hdev)
}
bda = (struct hci_rp_read_bd_addr *)skb->data;
if (bda->status) {
BT_ERR("%s: Intel device address result failed (%02x)",
hdev->name, bda->status);
kfree_skb(skb);
return -bt_to_errno(bda->status);
}
/* For some Intel based controllers, the default Bluetooth device
* address 00:03:19:9E:8B:00 can be found. These controllers are
+1 -1
View File
@@ -1217,7 +1217,7 @@ static void btmrvl_sdio_dump_firmware(struct btmrvl_private *priv)
unsigned int reg, reg_start, reg_end;
enum rdwr_status stat;
u8 *dbg_ptr, *end_ptr, *fw_dump_data, *fw_dump_ptr;
u8 dump_num, idx, i, read_reg, doneflag = 0;
u8 dump_num = 0, idx, i, read_reg, doneflag = 0;
u32 memory_size, fw_dump_len = 0;
/* dump sdio register first */
+390
View File
@@ -0,0 +1,390 @@
/*
* Bluetooth support for Realtek devices
*
* Copyright (C) 2015 Endless Mobile, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/module.h>
#include <linux/firmware.h>
#include <asm/unaligned.h>
#include <linux/usb.h>
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
#include "btrtl.h"
#define VERSION "0.1"
#define RTL_EPATCH_SIGNATURE "Realtech"
#define RTL_ROM_LMP_3499 0x3499
#define RTL_ROM_LMP_8723A 0x1200
#define RTL_ROM_LMP_8723B 0x8723
#define RTL_ROM_LMP_8821A 0x8821
#define RTL_ROM_LMP_8761A 0x8761
static int rtl_read_rom_version(struct hci_dev *hdev, u8 *version)
{
struct rtl_rom_version_evt *rom_version;
struct sk_buff *skb;
/* Read RTL ROM version command */
skb = __hci_cmd_sync(hdev, 0xfc6d, 0, NULL, HCI_INIT_TIMEOUT);
if (IS_ERR(skb)) {
BT_ERR("%s: Read ROM version failed (%ld)",
hdev->name, PTR_ERR(skb));
return PTR_ERR(skb);
}
if (skb->len != sizeof(*rom_version)) {
BT_ERR("%s: RTL version event length mismatch", hdev->name);
kfree_skb(skb);
return -EIO;
}
rom_version = (struct rtl_rom_version_evt *)skb->data;
BT_INFO("%s: rom_version status=%x version=%x",
hdev->name, rom_version->status, rom_version->version);
*version = rom_version->version;
kfree_skb(skb);
return 0;
}
static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver,
const struct firmware *fw,
unsigned char **_buf)
{
const u8 extension_sig[] = { 0x51, 0x04, 0xfd, 0x77 };
struct rtl_epatch_header *epatch_info;
unsigned char *buf;
int i, ret, len;
size_t min_size;
u8 opcode, length, data, rom_version = 0;
int project_id = -1;
const unsigned char *fwptr, *chip_id_base;
const unsigned char *patch_length_base, *patch_offset_base;
u32 patch_offset = 0;
u16 patch_length, num_patches;
const u16 project_id_to_lmp_subver[] = {
RTL_ROM_LMP_8723A,
RTL_ROM_LMP_8723B,
RTL_ROM_LMP_8821A,
RTL_ROM_LMP_8761A
};
ret = rtl_read_rom_version(hdev, &rom_version);
if (ret)
return ret;
min_size = sizeof(struct rtl_epatch_header) + sizeof(extension_sig) + 3;
if (fw->size < min_size)
return -EINVAL;
fwptr = fw->data + fw->size - sizeof(extension_sig);
if (memcmp(fwptr, extension_sig, sizeof(extension_sig)) != 0) {
BT_ERR("%s: extension section signature mismatch", hdev->name);
return -EINVAL;
}
/* Loop from the end of the firmware parsing instructions, until
* we find an instruction that identifies the "project ID" for the
* hardware supported by this firwmare file.
* Once we have that, we double-check that that project_id is suitable
* for the hardware we are working with.
*/
while (fwptr >= fw->data + (sizeof(struct rtl_epatch_header) + 3)) {
opcode = *--fwptr;
length = *--fwptr;
data = *--fwptr;
BT_DBG("check op=%x len=%x data=%x", opcode, length, data);
if (opcode == 0xff) /* EOF */
break;
if (length == 0) {
BT_ERR("%s: found instruction with length 0",
hdev->name);
return -EINVAL;
}
if (opcode == 0 && length == 1) {
project_id = data;
break;
}
fwptr -= length;
}
if (project_id < 0) {
BT_ERR("%s: failed to find version instruction", hdev->name);
return -EINVAL;
}
if (project_id >= ARRAY_SIZE(project_id_to_lmp_subver)) {
BT_ERR("%s: unknown project id %d", hdev->name, project_id);
return -EINVAL;
}
if (lmp_subver != project_id_to_lmp_subver[project_id]) {
BT_ERR("%s: firmware is for %x but this is a %x", hdev->name,
project_id_to_lmp_subver[project_id], lmp_subver);
return -EINVAL;
}
epatch_info = (struct rtl_epatch_header *)fw->data;
if (memcmp(epatch_info->signature, RTL_EPATCH_SIGNATURE, 8) != 0) {
BT_ERR("%s: bad EPATCH signature", hdev->name);
return -EINVAL;
}
num_patches = le16_to_cpu(epatch_info->num_patches);
BT_DBG("fw_version=%x, num_patches=%d",
le32_to_cpu(epatch_info->fw_version), num_patches);
/* After the rtl_epatch_header there is a funky patch metadata section.
* Assuming 2 patches, the layout is:
* ChipID1 ChipID2 PatchLength1 PatchLength2 PatchOffset1 PatchOffset2
*
* Find the right patch for this chip.
*/
min_size += 8 * num_patches;
if (fw->size < min_size)
return -EINVAL;
chip_id_base = fw->data + sizeof(struct rtl_epatch_header);
patch_length_base = chip_id_base + (sizeof(u16) * num_patches);
patch_offset_base = patch_length_base + (sizeof(u16) * num_patches);
for (i = 0; i < num_patches; i++) {
u16 chip_id = get_unaligned_le16(chip_id_base +
(i * sizeof(u16)));
if (chip_id == rom_version + 1) {
patch_length = get_unaligned_le16(patch_length_base +
(i * sizeof(u16)));
patch_offset = get_unaligned_le32(patch_offset_base +
(i * sizeof(u32)));
break;
}
}
if (!patch_offset) {
BT_ERR("%s: didn't find patch for chip id %d",
hdev->name, rom_version);
return -EINVAL;
}
BT_DBG("length=%x offset=%x index %d", patch_length, patch_offset, i);
min_size = patch_offset + patch_length;
if (fw->size < min_size)
return -EINVAL;
/* Copy the firmware into a new buffer and write the version at
* the end.
*/
len = patch_length;
buf = kmemdup(fw->data + patch_offset, patch_length, GFP_KERNEL);
if (!buf)
return -ENOMEM;
memcpy(buf + patch_length - 4, &epatch_info->fw_version, 4);
*_buf = buf;
return len;
}
static int rtl_download_firmware(struct hci_dev *hdev,
const unsigned char *data, int fw_len)
{
struct rtl_download_cmd *dl_cmd;
int frag_num = fw_len / RTL_FRAG_LEN + 1;
int frag_len = RTL_FRAG_LEN;
int ret = 0;
int i;
dl_cmd = kmalloc(sizeof(struct rtl_download_cmd), GFP_KERNEL);
if (!dl_cmd)
return -ENOMEM;
for (i = 0; i < frag_num; i++) {
struct sk_buff *skb;
BT_DBG("download fw (%d/%d)", i, frag_num);
dl_cmd->index = i;
if (i == (frag_num - 1)) {
dl_cmd->index |= 0x80; /* data end */
frag_len = fw_len % RTL_FRAG_LEN;
}
memcpy(dl_cmd->data, data, frag_len);
/* Send download command */
skb = __hci_cmd_sync(hdev, 0xfc20, frag_len + 1, dl_cmd,
HCI_INIT_TIMEOUT);
if (IS_ERR(skb)) {
BT_ERR("%s: download fw command failed (%ld)",
hdev->name, PTR_ERR(skb));
ret = -PTR_ERR(skb);
goto out;
}
if (skb->len != sizeof(struct rtl_download_response)) {
BT_ERR("%s: download fw event length mismatch",
hdev->name);
kfree_skb(skb);
ret = -EIO;
goto out;
}
kfree_skb(skb);
data += RTL_FRAG_LEN;
}
out:
kfree(dl_cmd);
return ret;
}
static int btrtl_setup_rtl8723a(struct hci_dev *hdev)
{
const struct firmware *fw;
int ret;
BT_INFO("%s: rtl: loading rtl_bt/rtl8723a_fw.bin", hdev->name);
ret = request_firmware(&fw, "rtl_bt/rtl8723a_fw.bin", &hdev->dev);
if (ret < 0) {
BT_ERR("%s: Failed to load rtl_bt/rtl8723a_fw.bin", hdev->name);
return ret;
}
if (fw->size < 8) {
ret = -EINVAL;
goto out;
}
/* Check that the firmware doesn't have the epatch signature
* (which is only for RTL8723B and newer).
*/
if (!memcmp(fw->data, RTL_EPATCH_SIGNATURE, 8)) {
BT_ERR("%s: unexpected EPATCH signature!", hdev->name);
ret = -EINVAL;
goto out;
}
ret = rtl_download_firmware(hdev, fw->data, fw->size);
out:
release_firmware(fw);
return ret;
}
static int btrtl_setup_rtl8723b(struct hci_dev *hdev, u16 lmp_subver,
const char *fw_name)
{
unsigned char *fw_data = NULL;
const struct firmware *fw;
int ret;
BT_INFO("%s: rtl: loading %s", hdev->name, fw_name);
ret = request_firmware(&fw, fw_name, &hdev->dev);
if (ret < 0) {
BT_ERR("%s: Failed to load %s", hdev->name, fw_name);
return ret;
}
ret = rtl8723b_parse_firmware(hdev, lmp_subver, fw, &fw_data);
if (ret < 0)
goto out;
ret = rtl_download_firmware(hdev, fw_data, ret);
kfree(fw_data);
if (ret < 0)
goto out;
out:
release_firmware(fw);
return ret;
}
static struct sk_buff *btrtl_read_local_version(struct hci_dev *hdev)
{
struct sk_buff *skb;
skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_VERSION, 0, NULL,
HCI_INIT_TIMEOUT);
if (IS_ERR(skb)) {
BT_ERR("%s: HCI_OP_READ_LOCAL_VERSION failed (%ld)",
hdev->name, PTR_ERR(skb));
return skb;
}
if (skb->len != sizeof(struct hci_rp_read_local_version)) {
BT_ERR("%s: HCI_OP_READ_LOCAL_VERSION event length mismatch",
hdev->name);
kfree_skb(skb);
return ERR_PTR(-EIO);
}
return skb;
}
int btrtl_setup_realtek(struct hci_dev *hdev)
{
struct sk_buff *skb;
struct hci_rp_read_local_version *resp;
u16 lmp_subver;
skb = btrtl_read_local_version(hdev);
if (IS_ERR(skb))
return -PTR_ERR(skb);
resp = (struct hci_rp_read_local_version *)skb->data;
BT_INFO("%s: rtl: examining hci_ver=%02x hci_rev=%04x lmp_ver=%02x "
"lmp_subver=%04x", hdev->name, resp->hci_ver, resp->hci_rev,
resp->lmp_ver, resp->lmp_subver);
lmp_subver = le16_to_cpu(resp->lmp_subver);
kfree_skb(skb);
/* Match a set of subver values that correspond to stock firmware,
* which is not compatible with standard btusb.
* If matched, upload an alternative firmware that does conform to
* standard btusb. Once that firmware is uploaded, the subver changes
* to a different value.
*/
switch (lmp_subver) {
case RTL_ROM_LMP_8723A:
case RTL_ROM_LMP_3499:
return btrtl_setup_rtl8723a(hdev);
case RTL_ROM_LMP_8723B:
return btrtl_setup_rtl8723b(hdev, lmp_subver,
"rtl_bt/rtl8723b_fw.bin");
case RTL_ROM_LMP_8821A:
return btrtl_setup_rtl8723b(hdev, lmp_subver,
"rtl_bt/rtl8821a_fw.bin");
case RTL_ROM_LMP_8761A:
return btrtl_setup_rtl8723b(hdev, lmp_subver,
"rtl_bt/rtl8761a_fw.bin");
default:
BT_INFO("rtl: assuming no firmware upload needed.");
return 0;
}
}
EXPORT_SYMBOL_GPL(btrtl_setup_realtek);
MODULE_AUTHOR("Daniel Drake <drake@endlessm.com>");
MODULE_DESCRIPTION("Bluetooth support for Realtek devices ver " VERSION);
MODULE_VERSION(VERSION);
MODULE_LICENSE("GPL");
+52
View File
@@ -0,0 +1,52 @@
/*
* Bluetooth support for Realtek devices
*
* Copyright (C) 2015 Endless Mobile, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#define RTL_FRAG_LEN 252
struct rtl_download_cmd {
__u8 index;
__u8 data[RTL_FRAG_LEN];
} __packed;
struct rtl_download_response {
__u8 status;
__u8 index;
} __packed;
struct rtl_rom_version_evt {
__u8 status;
__u8 version;
} __packed;
struct rtl_epatch_header {
__u8 signature[8];
__le32 fw_version;
__le16 num_patches;
} __packed;
#if IS_ENABLED(CONFIG_BT_RTL)
int btrtl_setup_realtek(struct hci_dev *hdev);
#else
static inline int btrtl_setup_realtek(struct hci_dev *hdev)
{
return -EOPNOTSUPP;
}
#endif
+23 -411
View File
File diff suppressed because it is too large. Load diff
+1 -1
View File
@@ -22,7 +22,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#define DEBUG
#include <linux/platform_device.h>
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
+2 -2
View File
@@ -47,8 +47,8 @@
#include "hci_uart.h"
static bool txcrc = 1;
static bool hciextn = 1;
static bool txcrc = true;
static bool hciextn = true;
#define BCSP_TXWINSIZE 4
+10
View File
@@ -53,3 +53,13 @@ config IEEE802154_CC2520
This driver can also be built as a module. To do so, say M here.
the module will be called 'cc2520'.
config IEEE802154_ATUSB
tristate "ATUSB transceiver driver"
depends on IEEE802154_DRIVERS && MAC802154 && USB
---help---
Say Y here to enable the ATUSB IEEE 802.15.4 wireless
controller.
This driver can also be built as a module. To do so say M here.
The module will be called 'atusb'.
+1
View File
@@ -2,3 +2,4 @@ obj-$(CONFIG_IEEE802154_FAKELB) += fakelb.o
obj-$(CONFIG_IEEE802154_AT86RF230) += at86rf230.o
obj-$(CONFIG_IEEE802154_MRF24J40) += mrf24j40.o
obj-$(CONFIG_IEEE802154_CC2520) += cc2520.o
obj-$(CONFIG_IEEE802154_ATUSB) += atusb.o
+142 -236
View File
@@ -35,6 +35,8 @@
#include <net/mac802154.h>
#include <net/cfg802154.h>
#include "at86rf230.h"
struct at86rf230_local;
/* at86rf2xx chip depend data.
* All timings are in us.
@@ -50,7 +52,7 @@ struct at86rf2xx_chip_data {
int rssi_base_val;
int (*set_channel)(struct at86rf230_local *, u8, u8);
int (*get_desense_steps)(struct at86rf230_local *, s32);
int (*set_txpower)(struct at86rf230_local *, s32);
};
#define AT86RF2XX_MAX_BUF (127 + 3)
@@ -102,200 +104,6 @@ struct at86rf230_local {
struct at86rf230_state_change tx;
};
#define RG_TRX_STATUS (0x01)
#define SR_TRX_STATUS 0x01, 0x1f, 0
#define SR_RESERVED_01_3 0x01, 0x20, 5
#define SR_CCA_STATUS 0x01, 0x40, 6
#define SR_CCA_DONE 0x01, 0x80, 7
#define RG_TRX_STATE (0x02)
#define SR_TRX_CMD 0x02, 0x1f, 0
#define SR_TRAC_STATUS 0x02, 0xe0, 5
#define RG_TRX_CTRL_0 (0x03)
#define SR_CLKM_CTRL 0x03, 0x07, 0
#define SR_CLKM_SHA_SEL 0x03, 0x08, 3
#define SR_PAD_IO_CLKM 0x03, 0x30, 4
#define SR_PAD_IO 0x03, 0xc0, 6
#define RG_TRX_CTRL_1 (0x04)
#define SR_IRQ_POLARITY 0x04, 0x01, 0
#define SR_IRQ_MASK_MODE 0x04, 0x02, 1
#define SR_SPI_CMD_MODE 0x04, 0x0c, 2
#define SR_RX_BL_CTRL 0x04, 0x10, 4
#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
#define SR_PA_EXT_EN 0x04, 0x80, 7
#define RG_PHY_TX_PWR (0x05)
#define SR_TX_PWR 0x05, 0x0f, 0
#define SR_PA_LT 0x05, 0x30, 4
#define SR_PA_BUF_LT 0x05, 0xc0, 6
#define RG_PHY_RSSI (0x06)
#define SR_RSSI 0x06, 0x1f, 0
#define SR_RND_VALUE 0x06, 0x60, 5
#define SR_RX_CRC_VALID 0x06, 0x80, 7
#define RG_PHY_ED_LEVEL (0x07)
#define SR_ED_LEVEL 0x07, 0xff, 0
#define RG_PHY_CC_CCA (0x08)
#define SR_CHANNEL 0x08, 0x1f, 0
#define SR_CCA_MODE 0x08, 0x60, 5
#define SR_CCA_REQUEST 0x08, 0x80, 7
#define RG_CCA_THRES (0x09)
#define SR_CCA_ED_THRES 0x09, 0x0f, 0
#define SR_RESERVED_09_1 0x09, 0xf0, 4
#define RG_RX_CTRL (0x0a)
#define SR_PDT_THRES 0x0a, 0x0f, 0
#define SR_RESERVED_0a_1 0x0a, 0xf0, 4
#define RG_SFD_VALUE (0x0b)
#define SR_SFD_VALUE 0x0b, 0xff, 0
#define RG_TRX_CTRL_2 (0x0c)
#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
#define SR_SUB_MODE 0x0c, 0x04, 2
#define SR_BPSK_QPSK 0x0c, 0x08, 3
#define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
#define SR_RESERVED_0c_5 0x0c, 0x60, 5
#define SR_RX_SAFE_MODE 0x0c, 0x80, 7
#define RG_ANT_DIV (0x0d)
#define SR_ANT_CTRL 0x0d, 0x03, 0
#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
#define SR_ANT_DIV_EN 0x0d, 0x08, 3
#define SR_RESERVED_0d_2 0x0d, 0x70, 4
#define SR_ANT_SEL 0x0d, 0x80, 7
#define RG_IRQ_MASK (0x0e)
#define SR_IRQ_MASK 0x0e, 0xff, 0
#define RG_IRQ_STATUS (0x0f)
#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
#define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
#define SR_IRQ_5_AMI 0x0f, 0x20, 5
#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
#define RG_VREG_CTRL (0x10)
#define SR_RESERVED_10_6 0x10, 0x03, 0
#define SR_DVDD_OK 0x10, 0x04, 2
#define SR_DVREG_EXT 0x10, 0x08, 3
#define SR_RESERVED_10_3 0x10, 0x30, 4
#define SR_AVDD_OK 0x10, 0x40, 6
#define SR_AVREG_EXT 0x10, 0x80, 7
#define RG_BATMON (0x11)
#define SR_BATMON_VTH 0x11, 0x0f, 0
#define SR_BATMON_HR 0x11, 0x10, 4
#define SR_BATMON_OK 0x11, 0x20, 5
#define SR_RESERVED_11_1 0x11, 0xc0, 6
#define RG_XOSC_CTRL (0x12)
#define SR_XTAL_TRIM 0x12, 0x0f, 0
#define SR_XTAL_MODE 0x12, 0xf0, 4
#define RG_RX_SYN (0x15)
#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
#define SR_RESERVED_15_2 0x15, 0x70, 4
#define SR_RX_PDT_DIS 0x15, 0x80, 7
#define RG_XAH_CTRL_1 (0x17)
#define SR_RESERVED_17_8 0x17, 0x01, 0
#define SR_AACK_PROM_MODE 0x17, 0x02, 1
#define SR_AACK_ACK_TIME 0x17, 0x04, 2
#define SR_RESERVED_17_5 0x17, 0x08, 3
#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
#define SR_CSMA_LBT_MODE 0x17, 0x40, 6
#define SR_RESERVED_17_1 0x17, 0x80, 7
#define RG_FTN_CTRL (0x18)
#define SR_RESERVED_18_2 0x18, 0x7f, 0
#define SR_FTN_START 0x18, 0x80, 7
#define RG_PLL_CF (0x1a)
#define SR_RESERVED_1a_2 0x1a, 0x7f, 0
#define SR_PLL_CF_START 0x1a, 0x80, 7
#define RG_PLL_DCU (0x1b)
#define SR_RESERVED_1b_3 0x1b, 0x3f, 0
#define SR_RESERVED_1b_2 0x1b, 0x40, 6
#define SR_PLL_DCU_START 0x1b, 0x80, 7
#define RG_PART_NUM (0x1c)
#define SR_PART_NUM 0x1c, 0xff, 0
#define RG_VERSION_NUM (0x1d)
#define SR_VERSION_NUM 0x1d, 0xff, 0
#define RG_MAN_ID_0 (0x1e)
#define SR_MAN_ID_0 0x1e, 0xff, 0
#define RG_MAN_ID_1 (0x1f)
#define SR_MAN_ID_1 0x1f, 0xff, 0
#define RG_SHORT_ADDR_0 (0x20)
#define SR_SHORT_ADDR_0 0x20, 0xff, 0
#define RG_SHORT_ADDR_1 (0x21)
#define SR_SHORT_ADDR_1 0x21, 0xff, 0
#define RG_PAN_ID_0 (0x22)
#define SR_PAN_ID_0 0x22, 0xff, 0
#define RG_PAN_ID_1 (0x23)
#define SR_PAN_ID_1 0x23, 0xff, 0
#define RG_IEEE_ADDR_0 (0x24)
#define SR_IEEE_ADDR_0 0x24, 0xff, 0
#define RG_IEEE_ADDR_1 (0x25)
#define SR_IEEE_ADDR_1 0x25, 0xff, 0
#define RG_IEEE_ADDR_2 (0x26)
#define SR_IEEE_ADDR_2 0x26, 0xff, 0
#define RG_IEEE_ADDR_3 (0x27)
#define SR_IEEE_ADDR_3 0x27, 0xff, 0
#define RG_IEEE_ADDR_4 (0x28)
#define SR_IEEE_ADDR_4 0x28, 0xff, 0
#define RG_IEEE_ADDR_5 (0x29)
#define SR_IEEE_ADDR_5 0x29, 0xff, 0
#define RG_IEEE_ADDR_6 (0x2a)
#define SR_IEEE_ADDR_6 0x2a, 0xff, 0
#define RG_IEEE_ADDR_7 (0x2b)
#define SR_IEEE_ADDR_7 0x2b, 0xff, 0
#define RG_XAH_CTRL_0 (0x2c)
#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
#define RG_CSMA_SEED_0 (0x2d)
#define SR_CSMA_SEED_0 0x2d, 0xff, 0
#define RG_CSMA_SEED_1 (0x2e)
#define SR_CSMA_SEED_1 0x2e, 0x07, 0
#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
#define SR_AACK_DIS_ACK 0x2e, 0x10, 4
#define SR_AACK_SET_PD 0x2e, 0x20, 5
#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
#define RG_CSMA_BE (0x2f)
#define SR_MIN_BE 0x2f, 0x0f, 0
#define SR_MAX_BE 0x2f, 0xf0, 4
#define CMD_REG 0x80
#define CMD_REG_MASK 0x3f
#define CMD_WRITE 0x40
#define CMD_FB 0x20
#define IRQ_BAT_LOW (1 << 7)
#define IRQ_TRX_UR (1 << 6)
#define IRQ_AMI (1 << 5)
#define IRQ_CCA_ED (1 << 4)
#define IRQ_TRX_END (1 << 3)
#define IRQ_RX_START (1 << 2)
#define IRQ_PLL_UNL (1 << 1)
#define IRQ_PLL_LOCK (1 << 0)
#define IRQ_ACTIVE_HIGH 0
#define IRQ_ACTIVE_LOW 1
#define STATE_P_ON 0x00 /* BUSY */
#define STATE_BUSY_RX 0x01
#define STATE_BUSY_TX 0x02
#define STATE_FORCE_TRX_OFF 0x03
#define STATE_FORCE_TX_ON 0x04 /* IDLE */
/* 0x05 */ /* INVALID_PARAMETER */
#define STATE_RX_ON 0x06
/* 0x07 */ /* SUCCESS */
#define STATE_TRX_OFF 0x08
#define STATE_TX_ON 0x09
/* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
#define STATE_SLEEP 0x0F
#define STATE_PREP_DEEP_SLEEP 0x10
#define STATE_BUSY_RX_AACK 0x11
#define STATE_BUSY_TX_ARET 0x12
#define STATE_RX_AACK_ON 0x16
#define STATE_TX_ARET_ON 0x19
#define STATE_RX_ON_NOCLK 0x1C
#define STATE_RX_AACK_ON_NOCLK 0x1D
#define STATE_BUSY_RX_AACK_NOCLK 0x1E
#define STATE_TRANSITION_IN_PROGRESS 0x1F
#define TRX_STATE_MASK (0x1F)
#define AT86RF2XX_NUMREGS 0x3F
static void
@@ -1010,7 +818,7 @@ at86rf230_xmit_start(void *context)
if (lp->is_tx_from_off) {
lp->is_tx_from_off = false;
at86rf230_async_state_change(lp, ctx, STATE_TX_ARET_ON,
at86rf230_xmit_tx_on,
at86rf230_write_frame,
false);
} else {
at86rf230_async_state_change(lp, ctx, STATE_TX_ON,
@@ -1076,6 +884,50 @@ at86rf23x_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
return at86rf230_write_subreg(lp, SR_CHANNEL, channel);
}
#define AT86RF2XX_MAX_ED_LEVELS 0xF
static const s32 at86rf23x_ed_levels[AT86RF2XX_MAX_ED_LEVELS + 1] = {
-9100, -8900, -8700, -8500, -8300, -8100, -7900, -7700, -7500, -7300,
-7100, -6900, -6700, -6500, -6300, -6100,
};
static const s32 at86rf212_ed_levels_100[AT86RF2XX_MAX_ED_LEVELS + 1] = {
-10000, -9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200,
-8000, -7800, -7600, -7400, -7200, -7000,
};
static const s32 at86rf212_ed_levels_98[AT86RF2XX_MAX_ED_LEVELS + 1] = {
-9800, -9600, -9400, -9200, -9000, -8800, -8600, -8400, -8200, -8000,
-7800, -7600, -7400, -7200, -7000, -6800,
};
static inline int
at86rf212_update_cca_ed_level(struct at86rf230_local *lp, int rssi_base_val)
{
unsigned int cca_ed_thres;
int rc;
rc = at86rf230_read_subreg(lp, SR_CCA_ED_THRES, &cca_ed_thres);
if (rc < 0)
return rc;
switch (rssi_base_val) {
case -98:
lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_98;
lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_98);
lp->hw->phy->cca_ed_level = at86rf212_ed_levels_98[cca_ed_thres];
break;
case -100:
lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
lp->hw->phy->cca_ed_level = at86rf212_ed_levels_100[cca_ed_thres];
break;
default:
WARN_ON(1);
}
return 0;
}
static int
at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
{
@@ -1098,6 +950,10 @@ at86rf212_set_channel(struct at86rf230_local *lp, u8 page, u8 channel)
if (rc < 0)
return rc;
rc = at86rf212_update_cca_ed_level(lp, lp->data->rssi_base_val);
if (rc < 0)
return rc;
/* This sets the symbol_duration according frequency on the 212.
* TODO move this handling while set channel and page in cfg802154.
* We can do that, this timings are according 802.15.4 standard.
@@ -1193,23 +1049,56 @@ at86rf230_set_hw_addr_filt(struct ieee802154_hw *hw,
return 0;
}
#define AT86RF23X_MAX_TX_POWERS 0xF
static const s32 at86rf233_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
400, 370, 340, 300, 250, 200, 100, 0, -100, -200, -300, -400, -600,
-800, -1200, -1700,
};
static const s32 at86rf231_powers[AT86RF23X_MAX_TX_POWERS + 1] = {
300, 280, 230, 180, 130, 70, 0, -100, -200, -300, -400, -500, -700,
-900, -1200, -1700,
};
#define AT86RF212_MAX_TX_POWERS 0x1F
static const s32 at86rf212_powers[AT86RF212_MAX_TX_POWERS + 1] = {
500, 400, 300, 200, 100, 0, -100, -200, -300, -400, -500, -600, -700,
-800, -900, -1000, -1100, -1200, -1300, -1400, -1500, -1600, -1700,
-1800, -1900, -2000, -2100, -2200, -2300, -2400, -2500, -2600,
};
static int
at86rf230_set_txpower(struct ieee802154_hw *hw, s8 db)
at86rf23x_set_txpower(struct at86rf230_local *lp, s32 mbm)
{
u32 i;
for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
if (lp->hw->phy->supported.tx_powers[i] == mbm)
return at86rf230_write_subreg(lp, SR_TX_PWR_23X, i);
}
return -EINVAL;
}
static int
at86rf212_set_txpower(struct at86rf230_local *lp, s32 mbm)
{
u32 i;
for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) {
if (lp->hw->phy->supported.tx_powers[i] == mbm)
return at86rf230_write_subreg(lp, SR_TX_PWR_212, i);
}
return -EINVAL;
}
static int
at86rf230_set_txpower(struct ieee802154_hw *hw, s32 mbm)
{
struct at86rf230_local *lp = hw->priv;
/* typical maximum output is 5dBm with RG_PHY_TX_PWR 0x60, lower five
* bits decrease power in 1dB steps. 0x60 represents extra PA gain of
* 0dB.
* thus, supported values for db range from -26 to 5, for 31dB of
* reduction to 0dB of reduction.
*/
if (db > 5 || db < -26)
return -EINVAL;
db = -(db - 5);
return __at86rf230_write(lp, RG_PHY_TX_PWR, 0x60 | db);
return lp->data->set_txpower(lp, mbm);
}
static int
@@ -1254,28 +1143,19 @@ at86rf230_set_cca_mode(struct ieee802154_hw *hw,
return at86rf230_write_subreg(lp, SR_CCA_MODE, val);
}
static int
at86rf212_get_desens_steps(struct at86rf230_local *lp, s32 level)
{
return (level - lp->data->rssi_base_val) * 100 / 207;
}
static int
at86rf23x_get_desens_steps(struct at86rf230_local *lp, s32 level)
{
return (level - lp->data->rssi_base_val) / 2;
}
static int
at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 level)
at86rf230_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm)
{
struct at86rf230_local *lp = hw->priv;
u32 i;
if (level < lp->data->rssi_base_val || level > 30)
return -EINVAL;
for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) {
if (hw->phy->supported.cca_ed_levels[i] == mbm)
return at86rf230_write_subreg(lp, SR_CCA_ED_THRES, i);
}
return at86rf230_write_subreg(lp, SR_CCA_ED_THRES,
lp->data->get_desense_steps(lp, level));
return -EINVAL;
}
static int
@@ -1365,7 +1245,7 @@ static struct at86rf2xx_chip_data at86rf233_data = {
.t_p_ack = 545,
.rssi_base_val = -91,
.set_channel = at86rf23x_set_channel,
.get_desense_steps = at86rf23x_get_desens_steps
.set_txpower = at86rf23x_set_txpower,
};
static struct at86rf2xx_chip_data at86rf231_data = {
@@ -1378,7 +1258,7 @@ static struct at86rf2xx_chip_data at86rf231_data = {
.t_p_ack = 545,
.rssi_base_val = -91,
.set_channel = at86rf23x_set_channel,
.get_desense_steps = at86rf23x_get_desens_steps
.set_txpower = at86rf23x_set_txpower,
};
static struct at86rf2xx_chip_data at86rf212_data = {
@@ -1391,7 +1271,7 @@ static struct at86rf2xx_chip_data at86rf212_data = {
.t_p_ack = 545,
.rssi_base_val = -100,
.set_channel = at86rf212_set_channel,
.get_desense_steps = at86rf212_get_desens_steps
.set_txpower = at86rf212_set_txpower,
};
static int at86rf230_hw_init(struct at86rf230_local *lp, u8 xtal_trim)
@@ -1564,8 +1444,21 @@ at86rf230_detect_device(struct at86rf230_local *lp)
}
lp->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AACK |
IEEE802154_HW_TXPOWER | IEEE802154_HW_ARET |
IEEE802154_HW_AFILT | IEEE802154_HW_PROMISCUOUS;
IEEE802154_HW_CSMA_PARAMS |
IEEE802154_HW_FRAME_RETRIES | IEEE802154_HW_AFILT |
IEEE802154_HW_PROMISCUOUS;
lp->hw->phy->flags = WPAN_PHY_FLAG_TXPOWER |
WPAN_PHY_FLAG_CCA_ED_LEVEL |
WPAN_PHY_FLAG_CCA_MODE;
lp->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) |
BIT(NL802154_CCA_CARRIER) | BIT(NL802154_CCA_ENERGY_CARRIER);
lp->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) |
BIT(NL802154_CCA_OPT_ENERGY_CARRIER_OR);
lp->hw->phy->supported.cca_ed_levels = at86rf23x_ed_levels;
lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf23x_ed_levels);
lp->hw->phy->cca.mode = NL802154_CCA_ENERGY;
@@ -1573,36 +1466,49 @@ at86rf230_detect_device(struct at86rf230_local *lp)
case 2:
chip = "at86rf230";
rc = -ENOTSUPP;
break;
goto not_supp;
case 3:
chip = "at86rf231";
lp->data = &at86rf231_data;
lp->hw->phy->channels_supported[0] = 0x7FFF800;
lp->hw->phy->supported.channels[0] = 0x7FFF800;
lp->hw->phy->current_channel = 11;
lp->hw->phy->symbol_duration = 16;
lp->hw->phy->supported.tx_powers = at86rf231_powers;
lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf231_powers);
break;
case 7:
chip = "at86rf212";
lp->data = &at86rf212_data;
lp->hw->flags |= IEEE802154_HW_LBT;
lp->hw->phy->channels_supported[0] = 0x00007FF;
lp->hw->phy->channels_supported[2] = 0x00007FF;
lp->hw->phy->supported.channels[0] = 0x00007FF;
lp->hw->phy->supported.channels[2] = 0x00007FF;
lp->hw->phy->current_channel = 5;
lp->hw->phy->symbol_duration = 25;
lp->hw->phy->supported.lbt = NL802154_SUPPORTED_BOOL_BOTH;
lp->hw->phy->supported.tx_powers = at86rf212_powers;
lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf212_powers);
lp->hw->phy->supported.cca_ed_levels = at86rf212_ed_levels_100;
lp->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(at86rf212_ed_levels_100);
break;
case 11:
chip = "at86rf233";
lp->data = &at86rf233_data;
lp->hw->phy->channels_supported[0] = 0x7FFF800;
lp->hw->phy->supported.channels[0] = 0x7FFF800;
lp->hw->phy->current_channel = 13;
lp->hw->phy->symbol_duration = 16;
lp->hw->phy->supported.tx_powers = at86rf233_powers;
lp->hw->phy->supported.tx_powers_size = ARRAY_SIZE(at86rf233_powers);
break;
default:
chip = "unknown";
rc = -ENOTSUPP;
break;
goto not_supp;
}
lp->hw->phy->cca_ed_level = lp->hw->phy->supported.cca_ed_levels[7];
lp->hw->phy->transmit_power = lp->hw->phy->supported.tx_powers[0];
not_supp:
dev_info(&lp->spi->dev, "Detected %s chip version %d\n", chip, version);
return rc;
+220
View File
@@ -0,0 +1,220 @@
/*
* AT86RF230/RF231 driver
*
* Copyright (C) 2009-2012 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Written by:
* Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
* Alexander Smirnov <alex.bluesman.smirnov@gmail.com>
*/
#ifndef _AT86RF230_H
#define _AT86RF230_H
#define RG_TRX_STATUS (0x01)
#define SR_TRX_STATUS 0x01, 0x1f, 0
#define SR_RESERVED_01_3 0x01, 0x20, 5
#define SR_CCA_STATUS 0x01, 0x40, 6
#define SR_CCA_DONE 0x01, 0x80, 7
#define RG_TRX_STATE (0x02)
#define SR_TRX_CMD 0x02, 0x1f, 0
#define SR_TRAC_STATUS 0x02, 0xe0, 5
#define RG_TRX_CTRL_0 (0x03)
#define SR_CLKM_CTRL 0x03, 0x07, 0
#define SR_CLKM_SHA_SEL 0x03, 0x08, 3
#define SR_PAD_IO_CLKM 0x03, 0x30, 4
#define SR_PAD_IO 0x03, 0xc0, 6
#define RG_TRX_CTRL_1 (0x04)
#define SR_IRQ_POLARITY 0x04, 0x01, 0
#define SR_IRQ_MASK_MODE 0x04, 0x02, 1
#define SR_SPI_CMD_MODE 0x04, 0x0c, 2
#define SR_RX_BL_CTRL 0x04, 0x10, 4
#define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5
#define SR_IRQ_2_EXT_EN 0x04, 0x40, 6
#define SR_PA_EXT_EN 0x04, 0x80, 7
#define RG_PHY_TX_PWR (0x05)
#define SR_TX_PWR_23X 0x05, 0x0f, 0
#define SR_PA_LT_230 0x05, 0x30, 4
#define SR_PA_BUF_LT_230 0x05, 0xc0, 6
#define SR_TX_PWR_212 0x05, 0x1f, 0
#define SR_GC_PA_212 0x05, 0x60, 5
#define SR_PA_BOOST_LT_212 0x05, 0x80, 7
#define RG_PHY_RSSI (0x06)
#define SR_RSSI 0x06, 0x1f, 0
#define SR_RND_VALUE 0x06, 0x60, 5
#define SR_RX_CRC_VALID 0x06, 0x80, 7
#define RG_PHY_ED_LEVEL (0x07)
#define SR_ED_LEVEL 0x07, 0xff, 0
#define RG_PHY_CC_CCA (0x08)
#define SR_CHANNEL 0x08, 0x1f, 0
#define SR_CCA_MODE 0x08, 0x60, 5
#define SR_CCA_REQUEST 0x08, 0x80, 7
#define RG_CCA_THRES (0x09)
#define SR_CCA_ED_THRES 0x09, 0x0f, 0
#define SR_RESERVED_09_1 0x09, 0xf0, 4
#define RG_RX_CTRL (0x0a)
#define SR_PDT_THRES 0x0a, 0x0f, 0
#define SR_RESERVED_0a_1 0x0a, 0xf0, 4
#define RG_SFD_VALUE (0x0b)
#define SR_SFD_VALUE 0x0b, 0xff, 0
#define RG_TRX_CTRL_2 (0x0c)
#define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0
#define SR_SUB_MODE 0x0c, 0x04, 2
#define SR_BPSK_QPSK 0x0c, 0x08, 3
#define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4
#define SR_RESERVED_0c_5 0x0c, 0x60, 5
#define SR_RX_SAFE_MODE 0x0c, 0x80, 7
#define RG_ANT_DIV (0x0d)
#define SR_ANT_CTRL 0x0d, 0x03, 0
#define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2
#define SR_ANT_DIV_EN 0x0d, 0x08, 3
#define SR_RESERVED_0d_2 0x0d, 0x70, 4
#define SR_ANT_SEL 0x0d, 0x80, 7
#define RG_IRQ_MASK (0x0e)
#define SR_IRQ_MASK 0x0e, 0xff, 0
#define RG_IRQ_STATUS (0x0f)
#define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0
#define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1
#define SR_IRQ_2_RX_START 0x0f, 0x04, 2
#define SR_IRQ_3_TRX_END 0x0f, 0x08, 3
#define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4
#define SR_IRQ_5_AMI 0x0f, 0x20, 5
#define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6
#define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7
#define RG_VREG_CTRL (0x10)
#define SR_RESERVED_10_6 0x10, 0x03, 0
#define SR_DVDD_OK 0x10, 0x04, 2
#define SR_DVREG_EXT 0x10, 0x08, 3
#define SR_RESERVED_10_3 0x10, 0x30, 4
#define SR_AVDD_OK 0x10, 0x40, 6
#define SR_AVREG_EXT 0x10, 0x80, 7
#define RG_BATMON (0x11)
#define SR_BATMON_VTH 0x11, 0x0f, 0
#define SR_BATMON_HR 0x11, 0x10, 4
#define SR_BATMON_OK 0x11, 0x20, 5
#define SR_RESERVED_11_1 0x11, 0xc0, 6
#define RG_XOSC_CTRL (0x12)
#define SR_XTAL_TRIM 0x12, 0x0f, 0
#define SR_XTAL_MODE 0x12, 0xf0, 4
#define RG_RX_SYN (0x15)
#define SR_RX_PDT_LEVEL 0x15, 0x0f, 0
#define SR_RESERVED_15_2 0x15, 0x70, 4
#define SR_RX_PDT_DIS 0x15, 0x80, 7
#define RG_XAH_CTRL_1 (0x17)
#define SR_RESERVED_17_8 0x17, 0x01, 0
#define SR_AACK_PROM_MODE 0x17, 0x02, 1
#define SR_AACK_ACK_TIME 0x17, 0x04, 2
#define SR_RESERVED_17_5 0x17, 0x08, 3
#define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4
#define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5
#define SR_CSMA_LBT_MODE 0x17, 0x40, 6
#define SR_RESERVED_17_1 0x17, 0x80, 7
#define RG_FTN_CTRL (0x18)
#define SR_RESERVED_18_2 0x18, 0x7f, 0
#define SR_FTN_START 0x18, 0x80, 7
#define RG_PLL_CF (0x1a)
#define SR_RESERVED_1a_2 0x1a, 0x7f, 0
#define SR_PLL_CF_START 0x1a, 0x80, 7
#define RG_PLL_DCU (0x1b)
#define SR_RESERVED_1b_3 0x1b, 0x3f, 0
#define SR_RESERVED_1b_2 0x1b, 0x40, 6
#define SR_PLL_DCU_START 0x1b, 0x80, 7
#define RG_PART_NUM (0x1c)
#define SR_PART_NUM 0x1c, 0xff, 0
#define RG_VERSION_NUM (0x1d)
#define SR_VERSION_NUM 0x1d, 0xff, 0
#define RG_MAN_ID_0 (0x1e)
#define SR_MAN_ID_0 0x1e, 0xff, 0
#define RG_MAN_ID_1 (0x1f)
#define SR_MAN_ID_1 0x1f, 0xff, 0
#define RG_SHORT_ADDR_0 (0x20)
#define SR_SHORT_ADDR_0 0x20, 0xff, 0
#define RG_SHORT_ADDR_1 (0x21)
#define SR_SHORT_ADDR_1 0x21, 0xff, 0
#define RG_PAN_ID_0 (0x22)
#define SR_PAN_ID_0 0x22, 0xff, 0
#define RG_PAN_ID_1 (0x23)
#define SR_PAN_ID_1 0x23, 0xff, 0
#define RG_IEEE_ADDR_0 (0x24)
#define SR_IEEE_ADDR_0 0x24, 0xff, 0
#define RG_IEEE_ADDR_1 (0x25)
#define SR_IEEE_ADDR_1 0x25, 0xff, 0
#define RG_IEEE_ADDR_2 (0x26)
#define SR_IEEE_ADDR_2 0x26, 0xff, 0
#define RG_IEEE_ADDR_3 (0x27)
#define SR_IEEE_ADDR_3 0x27, 0xff, 0
#define RG_IEEE_ADDR_4 (0x28)
#define SR_IEEE_ADDR_4 0x28, 0xff, 0
#define RG_IEEE_ADDR_5 (0x29)
#define SR_IEEE_ADDR_5 0x29, 0xff, 0
#define RG_IEEE_ADDR_6 (0x2a)
#define SR_IEEE_ADDR_6 0x2a, 0xff, 0
#define RG_IEEE_ADDR_7 (0x2b)
#define SR_IEEE_ADDR_7 0x2b, 0xff, 0
#define RG_XAH_CTRL_0 (0x2c)
#define SR_SLOTTED_OPERATION 0x2c, 0x01, 0
#define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1
#define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4
#define RG_CSMA_SEED_0 (0x2d)
#define SR_CSMA_SEED_0 0x2d, 0xff, 0
#define RG_CSMA_SEED_1 (0x2e)
#define SR_CSMA_SEED_1 0x2e, 0x07, 0
#define SR_AACK_I_AM_COORD 0x2e, 0x08, 3
#define SR_AACK_DIS_ACK 0x2e, 0x10, 4
#define SR_AACK_SET_PD 0x2e, 0x20, 5
#define SR_AACK_FVN_MODE 0x2e, 0xc0, 6
#define RG_CSMA_BE (0x2f)
#define SR_MIN_BE 0x2f, 0x0f, 0
#define SR_MAX_BE 0x2f, 0xf0, 4
#define CMD_REG 0x80
#define CMD_REG_MASK 0x3f
#define CMD_WRITE 0x40
#define CMD_FB 0x20
#define IRQ_BAT_LOW BIT(7)
#define IRQ_TRX_UR BIT(6)
#define IRQ_AMI BIT(5)
#define IRQ_CCA_ED BIT(4)
#define IRQ_TRX_END BIT(3)
#define IRQ_RX_START BIT(2)
#define IRQ_PLL_UNL BIT(1)
#define IRQ_PLL_LOCK BIT(0)
#define IRQ_ACTIVE_HIGH 0
#define IRQ_ACTIVE_LOW 1
#define STATE_P_ON 0x00 /* BUSY */
#define STATE_BUSY_RX 0x01
#define STATE_BUSY_TX 0x02
#define STATE_FORCE_TRX_OFF 0x03
#define STATE_FORCE_TX_ON 0x04 /* IDLE */
/* 0x05 */ /* INVALID_PARAMETER */
#define STATE_RX_ON 0x06
/* 0x07 */ /* SUCCESS */
#define STATE_TRX_OFF 0x08
#define STATE_TX_ON 0x09
/* 0x0a - 0x0e */ /* 0x0a - UNSUPPORTED_ATTRIBUTE */
#define STATE_SLEEP 0x0F
#define STATE_PREP_DEEP_SLEEP 0x10
#define STATE_BUSY_RX_AACK 0x11
#define STATE_BUSY_TX_ARET 0x12
#define STATE_RX_AACK_ON 0x16
#define STATE_TX_ARET_ON 0x19
#define STATE_RX_ON_NOCLK 0x1C
#define STATE_RX_AACK_ON_NOCLK 0x1D
#define STATE_BUSY_RX_AACK_NOCLK 0x1E
#define STATE_TRANSITION_IN_PROGRESS 0x1F
#define TRX_STATE_MASK (0x1F)
#endif /* !_AT86RF230_H */
File diff suppressed because it is too large. Load diff
+84
View File
@@ -0,0 +1,84 @@
/*
* atusb.h - Definitions shared between kernel and ATUSB firmware
*
* Written 2013 by Werner Almesberger <werner@almesberger.net>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation, version 2, or
* (at your option) any later version.
*
* This file should be identical for kernel and firmware.
* Kernel: drivers/net/ieee802154/atusb.h
* Firmware: ben-wpan/atusb/fw/include/atusb/atusb.h
*/
#ifndef _ATUSB_H
#define _ATUSB_H
#define ATUSB_VENDOR_ID 0x20b7 /* Qi Hardware*/
#define ATUSB_PRODUCT_ID 0x1540 /* 802.15.4, device 0 */
/* -- - - */
#define ATUSB_BUILD_SIZE 256 /* maximum build version/date message length */
/* Commands to our device. Make sure this is synced with the firmware */
enum atusb_requests {
ATUSB_ID = 0x00, /* system status/control grp */
ATUSB_BUILD,
ATUSB_RESET,
ATUSB_RF_RESET = 0x10, /* debug/test group */
ATUSB_POLL_INT,
ATUSB_TEST, /* atusb-sil only */
ATUSB_TIMER,
ATUSB_GPIO,
ATUSB_SLP_TR,
ATUSB_GPIO_CLEANUP,
ATUSB_REG_WRITE = 0x20, /* transceiver group */
ATUSB_REG_READ,
ATUSB_BUF_WRITE,
ATUSB_BUF_READ,
ATUSB_SRAM_WRITE,
ATUSB_SRAM_READ,
ATUSB_SPI_WRITE = 0x30, /* SPI group */
ATUSB_SPI_READ1,
ATUSB_SPI_READ2,
ATUSB_SPI_WRITE2_SYNC,
ATUSB_RX_MODE = 0x40, /* HardMAC group */
ATUSB_TX,
};
/* Direction bRequest wValue wIndex wLength
*
* ->host ATUSB_ID - - 3
* ->host ATUSB_BUILD - - #bytes
* host-> ATUSB_RESET - - 0
*
* host-> ATUSB_RF_RESET - - 0
* ->host ATUSB_POLL_INT - - 1
* host-> ATUSB_TEST - - 0
* ->host ATUSB_TIMER - - #bytes (6)
* ->host ATUSB_GPIO dir+data mask+p# 3
* host-> ATUSB_SLP_TR - - 0
* host-> ATUSB_GPIO_CLEANUP - - 0
*
* host-> ATUSB_REG_WRITE value addr 0
* ->host ATUSB_REG_READ - addr 1
* host-> ATUSB_BUF_WRITE - - #bytes
* ->host ATUSB_BUF_READ - - #bytes
* host-> ATUSB_SRAM_WRITE - addr #bytes
* ->host ATUSB_SRAM_READ - addr #bytes
*
* host-> ATUSB_SPI_WRITE byte0 byte1 #bytes
* ->host ATUSB_SPI_READ1 byte0 - #bytes
* ->host ATUSB_SPI_READ2 byte0 byte1 #bytes
* ->host ATUSB_SPI_WRITE2_SYNC byte0 byte1 0/1
*
* host-> ATUSB_RX_MODE on - 0
* host-> ATUSB_TX flags ack_seq #bytes
*/
#define ATUSB_REQ_FROM_DEV (USB_TYPE_VENDOR | USB_DIR_IN)
#define ATUSB_REQ_TO_DEV (USB_TYPE_VENDOR | USB_DIR_OUT)
#endif /* !_ATUSB_H */
+1 -1
View File
@@ -653,7 +653,7 @@ static int cc2520_register(struct cc2520_private *priv)
ieee802154_random_extended_addr(&priv->hw->phy->perm_extended_addr);
/* We do support only 2.4 Ghz */
priv->hw->phy->channels_supported[0] = 0x7FFF800;
priv->hw->phy->supported.channels[0] = 0x7FFF800;
priv->hw->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK |
IEEE802154_HW_AFILT;
+95 -122
View File
@@ -27,25 +27,25 @@
#include <net/mac802154.h>
#include <net/cfg802154.h>
static int numlbs = 1;
static int numlbs = 2;
struct fakelb_dev_priv {
static LIST_HEAD(fakelb_phys);
static DEFINE_SPINLOCK(fakelb_phys_lock);
static LIST_HEAD(fakelb_ifup_phys);
static DEFINE_RWLOCK(fakelb_ifup_phys_lock);
struct fakelb_phy {
struct ieee802154_hw *hw;
struct list_head list;
struct fakelb_priv *fake;
u8 page;
u8 channel;
spinlock_t lock;
bool working;
struct list_head list;
struct list_head list_ifup;
};
struct fakelb_priv {
struct list_head list;
rwlock_t lock;
};
static int
fakelb_hw_ed(struct ieee802154_hw *hw, u8 *level)
static int fakelb_hw_ed(struct ieee802154_hw *hw, u8 *level)
{
BUG_ON(!level);
*level = 0xbe;
@@ -53,78 +53,63 @@ fakelb_hw_ed(struct ieee802154_hw *hw, u8 *level)
return 0;
}
static int
fakelb_hw_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
static int fakelb_hw_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
{
pr_debug("set channel to %d\n", channel);
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
phy->page = page;
phy->channel = channel;
write_unlock_bh(&fakelb_ifup_phys_lock);
return 0;
}
static void
fakelb_hw_deliver(struct fakelb_dev_priv *priv, struct sk_buff *skb)
static int fakelb_hw_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
{
struct sk_buff *newskb;
struct fakelb_phy *current_phy = hw->priv, *phy;
spin_lock(&priv->lock);
if (priv->working) {
newskb = pskb_copy(skb, GFP_ATOMIC);
ieee802154_rx_irqsafe(priv->hw, newskb, 0xcc);
}
spin_unlock(&priv->lock);
}
read_lock_bh(&fakelb_ifup_phys_lock);
list_for_each_entry(phy, &fakelb_ifup_phys, list_ifup) {
if (current_phy == phy)
continue;
static int
fakelb_hw_xmit(struct ieee802154_hw *hw, struct sk_buff *skb)
{
struct fakelb_dev_priv *priv = hw->priv;
struct fakelb_priv *fake = priv->fake;
if (current_phy->page == phy->page &&
current_phy->channel == phy->channel) {
struct sk_buff *newskb = pskb_copy(skb, GFP_ATOMIC);
read_lock_bh(&fake->lock);
if (priv->list.next == priv->list.prev) {
/* we are the only one device */
fakelb_hw_deliver(priv, skb);
} else {
struct fakelb_dev_priv *dp;
list_for_each_entry(dp, &priv->fake->list, list) {
if (dp != priv &&
(dp->hw->phy->current_channel ==
priv->hw->phy->current_channel))
fakelb_hw_deliver(dp, skb);
if (newskb)
ieee802154_rx_irqsafe(phy->hw, newskb, 0xcc);
}
}
read_unlock_bh(&fake->lock);
read_unlock_bh(&fakelb_ifup_phys_lock);
ieee802154_xmit_complete(hw, skb, false);
return 0;
}
static int fakelb_hw_start(struct ieee802154_hw *hw)
{
struct fakelb_phy *phy = hw->priv;
write_lock_bh(&fakelb_ifup_phys_lock);
list_add(&phy->list_ifup, &fakelb_ifup_phys);
write_unlock_bh(&fakelb_ifup_phys_lock);
return 0;
}
static int
fakelb_hw_start(struct ieee802154_hw *hw) {
struct fakelb_dev_priv *priv = hw->priv;
int ret = 0;
static void fakelb_hw_stop(struct ieee802154_hw *hw)
{
struct fakelb_phy *phy = hw->priv;
spin_lock(&priv->lock);
if (priv->working)
ret = -EBUSY;
else
priv->working = 1;
spin_unlock(&priv->lock);
return ret;
}
static void
fakelb_hw_stop(struct ieee802154_hw *hw) {
struct fakelb_dev_priv *priv = hw->priv;
spin_lock(&priv->lock);
priv->working = 0;
spin_unlock(&priv->lock);
write_lock_bh(&fakelb_ifup_phys_lock);
list_del(&phy->list_ifup);
write_unlock_bh(&fakelb_ifup_phys_lock);
}
static const struct ieee802154_ops fakelb_ops = {
.owner = THIS_MODULE,
.xmit_sync = fakelb_hw_xmit,
.xmit_async = fakelb_hw_xmit,
.ed = fakelb_hw_ed,
.set_channel = fakelb_hw_channel,
.start = fakelb_hw_start,
@@ -135,54 +120,54 @@ static const struct ieee802154_ops fakelb_ops = {
module_param(numlbs, int, 0);
MODULE_PARM_DESC(numlbs, " number of pseudo devices");
static int fakelb_add_one(struct device *dev, struct fakelb_priv *fake)
static int fakelb_add_one(struct device *dev)
{
struct fakelb_dev_priv *priv;
int err;
struct ieee802154_hw *hw;
struct fakelb_phy *phy;
int err;
hw = ieee802154_alloc_hw(sizeof(*priv), &fakelb_ops);
hw = ieee802154_alloc_hw(sizeof(*phy), &fakelb_ops);
if (!hw)
return -ENOMEM;
priv = hw->priv;
priv->hw = hw;
phy = hw->priv;
phy->hw = hw;
/* 868 MHz BPSK 802.15.4-2003 */
hw->phy->channels_supported[0] |= 1;
hw->phy->supported.channels[0] |= 1;
/* 915 MHz BPSK 802.15.4-2003 */
hw->phy->channels_supported[0] |= 0x7fe;
hw->phy->supported.channels[0] |= 0x7fe;
/* 2.4 GHz O-QPSK 802.15.4-2003 */
hw->phy->channels_supported[0] |= 0x7FFF800;
hw->phy->supported.channels[0] |= 0x7FFF800;
/* 868 MHz ASK 802.15.4-2006 */
hw->phy->channels_supported[1] |= 1;
hw->phy->supported.channels[1] |= 1;
/* 915 MHz ASK 802.15.4-2006 */
hw->phy->channels_supported[1] |= 0x7fe;
hw->phy->supported.channels[1] |= 0x7fe;
/* 868 MHz O-QPSK 802.15.4-2006 */
hw->phy->channels_supported[2] |= 1;
hw->phy->supported.channels[2] |= 1;
/* 915 MHz O-QPSK 802.15.4-2006 */
hw->phy->channels_supported[2] |= 0x7fe;
hw->phy->supported.channels[2] |= 0x7fe;
/* 2.4 GHz CSS 802.15.4a-2007 */
hw->phy->channels_supported[3] |= 0x3fff;
hw->phy->supported.channels[3] |= 0x3fff;
/* UWB Sub-gigahertz 802.15.4a-2007 */
hw->phy->channels_supported[4] |= 1;
hw->phy->supported.channels[4] |= 1;
/* UWB Low band 802.15.4a-2007 */
hw->phy->channels_supported[4] |= 0x1e;
hw->phy->supported.channels[4] |= 0x1e;
/* UWB High band 802.15.4a-2007 */
hw->phy->channels_supported[4] |= 0xffe0;
hw->phy->supported.channels[4] |= 0xffe0;
/* 750 MHz O-QPSK 802.15.4c-2009 */
hw->phy->channels_supported[5] |= 0xf;
hw->phy->supported.channels[5] |= 0xf;
/* 750 MHz MPSK 802.15.4c-2009 */
hw->phy->channels_supported[5] |= 0xf0;
hw->phy->supported.channels[5] |= 0xf0;
/* 950 MHz BPSK 802.15.4d-2009 */
hw->phy->channels_supported[6] |= 0x3ff;
hw->phy->supported.channels[6] |= 0x3ff;
/* 950 MHz GFSK 802.15.4d-2009 */
hw->phy->channels_supported[6] |= 0x3ffc00;
hw->phy->supported.channels[6] |= 0x3ffc00;
INIT_LIST_HEAD(&priv->list);
priv->fake = fake;
spin_lock_init(&priv->lock);
ieee802154_random_extended_addr(&hw->phy->perm_extended_addr);
/* fake phy channel 13 as default */
hw->phy->current_channel = 13;
phy->channel = hw->phy->current_channel;
hw->parent = dev;
@@ -190,67 +175,55 @@ static int fakelb_add_one(struct device *dev, struct fakelb_priv *fake)
if (err)
goto err_reg;
write_lock_bh(&fake->lock);
list_add_tail(&priv->list, &fake->list);
write_unlock_bh(&fake->lock);
spin_lock(&fakelb_phys_lock);
list_add_tail(&phy->list, &fakelb_phys);
spin_unlock(&fakelb_phys_lock);
return 0;
err_reg:
ieee802154_free_hw(priv->hw);
ieee802154_free_hw(phy->hw);
return err;
}
static void fakelb_del(struct fakelb_dev_priv *priv)
static void fakelb_del(struct fakelb_phy *phy)
{
write_lock_bh(&priv->fake->lock);
list_del(&priv->list);
write_unlock_bh(&priv->fake->lock);
list_del(&phy->list);
ieee802154_unregister_hw(priv->hw);
ieee802154_free_hw(priv->hw);
ieee802154_unregister_hw(phy->hw);
ieee802154_free_hw(phy->hw);
}
static int fakelb_probe(struct platform_device *pdev)
{
struct fakelb_priv *priv;
struct fakelb_dev_priv *dp;
int err = -ENOMEM;
int i;
priv = devm_kzalloc(&pdev->dev, sizeof(struct fakelb_priv),
GFP_KERNEL);
if (!priv)
goto err_alloc;
INIT_LIST_HEAD(&priv->list);
rwlock_init(&priv->lock);
struct fakelb_phy *phy, *tmp;
int err, i;
for (i = 0; i < numlbs; i++) {
err = fakelb_add_one(&pdev->dev, priv);
err = fakelb_add_one(&pdev->dev);
if (err < 0)
goto err_slave;
}
platform_set_drvdata(pdev, priv);
dev_info(&pdev->dev, "added ieee802154 hardware\n");
return 0;
err_slave:
list_for_each_entry(dp, &priv->list, list)
fakelb_del(dp);
err_alloc:
spin_lock(&fakelb_phys_lock);
list_for_each_entry_safe(phy, tmp, &fakelb_phys, list)
fakelb_del(phy);
spin_unlock(&fakelb_phys_lock);
return err;
}
static int fakelb_remove(struct platform_device *pdev)
{
struct fakelb_priv *priv = platform_get_drvdata(pdev);
struct fakelb_dev_priv *dp, *temp;
list_for_each_entry_safe(dp, temp, &priv->list, list)
fakelb_del(dp);
struct fakelb_phy *phy, *tmp;
spin_lock(&fakelb_phys_lock);
list_for_each_entry_safe(phy, tmp, &fakelb_phys, list)
fakelb_del(phy);
spin_unlock(&fakelb_phys_lock);
return 0;
}
+1 -1
View File
@@ -750,7 +750,7 @@ static int mrf24j40_probe(struct spi_device *spi)
devrec->hw->priv = devrec;
devrec->hw->parent = &devrec->spi->dev;
devrec->hw->phy->channels_supported[0] = CHANNEL_MASK;
devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
devrec->hw->flags = IEEE802154_HW_OMIT_CKSUM | IEEE802154_HW_AACK |
IEEE802154_HW_AFILT;
Loaded 20 of 46 files, more files were not shown because too many files have changed in this diff. Show more