mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"Core:
- Add suuport for "rx-polarity" and "tx-polarity" device tree
properties and phy common properties to manage this
New Support:
- Qualcomm Glymur PCIe Gen4 2-lanes PCIe phy, DP and edp phy, USB UNI
PHY and SMB2370 eUSB2 repeater. SC8280xp QMP UFS PHY, Kaanapali
PCIe phy and QMP PHY, QCS615 QMP USB3+DP PHY and driver support for
that.
- SpacemiT PCIe/combo PHY and K1 USB2 PHY driver.
- HDMI 2.1 FRL configuration support and driver enabling for rockchip
samsung-hdptx driver
- TI TCAN1046 phy
- Renesas RZ/V2H(P) and RZ/V2N usb3
- Mediatek MT8188 hdmi-phy
- Google Tensor SoC USB PHY driver
- Apple Type-C PHY
Updates:
- Subsystem conversion for clock round_rate() to determine_rate()
- TI USB3 DT schema conversion
- Samsung ExynosAutov920 usb3, combo hsphy and ssphy support"
* tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (143 commits)
phy: ti: phy-j721e-wiz: convert from divider_round_rate() to divider_determine_rate()
dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
dt-bindings: phy: ti,phy-usb3: convert to DT schema
phy: tegra: xusb: Remove unused powered_on variable
phy: renesas: rcar-gen3-usb2: add regulator dependency
phy: GOOGLE_USB: add TYPEC dependency
phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY
phy: renesas: rcar-gen3-usb2: Use mux-state for phyrst management
phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control
phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable()
phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic
dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC
dt-bindings: phy: renesas,usb2-phy: Document mux-states property
dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator
phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support
phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper
phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config
phy: rockchip: samsung-hdptx: Drop hw_rate driver data
phy: rockchip: samsung-hdptx: Compute clk rate from PLL config
phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,222 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/apple,atcphy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple Type-C PHY (ATCPHY)
|
||||
|
||||
maintainers:
|
||||
- Sven Peter <sven@kernel.org>
|
||||
|
||||
description: >
|
||||
The Apple Type-C PHY (ATCPHY) is a combined PHY for USB 2.0, USB 3.x,
|
||||
USB4/Thunderbolt, and DisplayPort connectivity via Type-C ports found in
|
||||
Apple Silicon SoCs.
|
||||
|
||||
The PHY handles muxing between these different protocols and also provides the
|
||||
reset controller for the attached DWC3 USB controller.
|
||||
|
||||
It is designed for USB4 operation and does not handle individual differential
|
||||
pairs as distinct DisplayPort lanes. Any reference to lane in this binding
|
||||
hence refers to two differential pairs (RX and TX) as used in USB terminology.
|
||||
|
||||
In order to correctly setup these lanes for the various modes calibration
|
||||
values copied from Apple's firmware and converted to the format described
|
||||
below by our bootloader m1n1 are required. Without these only USB2 operation
|
||||
is possible.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/usb/usb-switch.yaml#
|
||||
|
||||
$defs:
|
||||
apple,tunable:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description: Register offset
|
||||
- description: Mask to be applied to the register value
|
||||
- description: Bits to be set after applying the mask
|
||||
description: >
|
||||
List of (register offset, mask, value) tuples copied from Apple's Device
|
||||
Tree by our bootloader m1n1 and used to configure the PHY. These values
|
||||
even vary for a single product/device and likely contain calibration
|
||||
values determined by Apple at manufacturing time.
|
||||
Unless otherwise noted these tunables are always applied to the core
|
||||
register region.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- apple,t6000-atcphy
|
||||
- apple,t6020-atcphy
|
||||
- apple,t8112-atcphy
|
||||
- const: apple,t8103-atcphy
|
||||
- const: apple,t8103-atcphy
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Common controls for all PHYs (USB2/3/4, DisplayPort, TBT)
|
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- description: DisplayPort Alternate Mode PHY specific controls
|
||||
- description: Type-C PHY AXI to Apple Fabric interconnect controls
|
||||
- description: USB2 PHY specific controls
|
||||
- description: USB3 PIPE interface controls
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: lpdptx
|
||||
- const: axi2af
|
||||
- const: usb2phy
|
||||
- const: pipehandler
|
||||
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 0
|
||||
|
||||
mode-switch: true
|
||||
orientation-switch: true
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
ports:
|
||||
$ref: /schemas/graph.yaml#/properties/ports
|
||||
properties:
|
||||
port@0:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Outgoing connection to the SS port of the Type-C connector.
|
||||
|
||||
port@1:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Incoming endpoint from the USB3 controller.
|
||||
|
||||
port@2:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Incoming endpoint from the DisplayPort controller.
|
||||
|
||||
port@3:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Incoming endpoint from the USB4/Thunderbolt controller.
|
||||
|
||||
apple,tunable-common-a:
|
||||
$ref: "#/$defs/apple,tunable"
|
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description: >
|
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Common tunables required for all modes, applied before tunable-axi2af.
|
||||
|
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apple,tunable-axi2af:
|
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$ref: "#/$defs/apple,tunable"
|
||||
description: >
|
||||
AXI to Apple Fabric tunables, required for all modes. Unlike all other
|
||||
tunables these are applied to the axi2af region.
|
||||
|
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apple,tunable-common-b:
|
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$ref: "#/$defs/apple,tunable"
|
||||
description: >
|
||||
Common tunables required for all modes, applied after tunable-axi2af.
|
||||
|
||||
apple,tunable-lane0-usb:
|
||||
$ref: "#/$defs/apple,tunable"
|
||||
description: USB3 tunables for lane 0.
|
||||
|
||||
apple,tunable-lane1-usb:
|
||||
$ref: "#/$defs/apple,tunable"
|
||||
description: USB3 tunables for lane 1.
|
||||
|
||||
apple,tunable-lane0-cio:
|
||||
$ref: "#/$defs/apple,tunable"
|
||||
description: USB4/Thunderbolt ("Converged IO") tunables for lane 0.
|
||||
|
||||
apple,tunable-lane1-cio:
|
||||
$ref: "#/$defs/apple,tunable"
|
||||
description: USB4/Thunderbolt ("Converged IO") tunables for lane 1.
|
||||
|
||||
apple,tunable-lane0-dp:
|
||||
$ref: "#/$defs/apple,tunable"
|
||||
description: >
|
||||
DisplayPort tunables for lane 0.
|
||||
|
||||
Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
|
||||
and not to an individual DisplayPort differential lane.
|
||||
|
||||
apple,tunable-lane1-dp:
|
||||
$ref: "#/$defs/apple,tunable"
|
||||
description: >
|
||||
DisplayPort tunables for lane 1.
|
||||
|
||||
Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
|
||||
and not to an individual DisplayPort differential lane.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#phy-cells"
|
||||
- "#reset-cells"
|
||||
- orientation-switch
|
||||
- mode-switch
|
||||
- power-domains
|
||||
- ports
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@83000000 {
|
||||
compatible = "apple,t8103-atcphy";
|
||||
reg = <0x83000000 0x4c000>,
|
||||
<0x83050000 0x8000>,
|
||||
<0x80000000 0x4000>,
|
||||
<0x82a90000 0x4000>,
|
||||
<0x82a84000 0x4000>;
|
||||
reg-names = "core", "lpdptx", "axi2af", "usb2phy",
|
||||
"pipehandler";
|
||||
|
||||
#phy-cells = <1>;
|
||||
#reset-cells = <0>;
|
||||
|
||||
orientation-switch;
|
||||
mode-switch;
|
||||
power-domains = <&ps_atc0_usb>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&typec_connector_ss>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&dwc3_ss_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&dcp_dp_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
|
||||
endpoint {
|
||||
remote-endpoint = <&acio_tbt_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -20,6 +20,32 @@ properties:
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
patternProperties:
|
||||
"^phy@[0-7]$":
|
||||
type: object
|
||||
description: SerDes lane (single RX/TX differential pair)
|
||||
|
||||
properties:
|
||||
reg:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
description: Lane index as seen in register map
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -32,9 +58,52 @@ examples:
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
serdes_1: phy@1ea0000 {
|
||||
|
||||
serdes@1ea0000 {
|
||||
compatible = "fsl,lynx-28g";
|
||||
reg = <0x0 0x1ea0000 0x0 0x1e30>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
phy@0 {
|
||||
reg = <0>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
phy@1 {
|
||||
reg = <1>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
phy@2 {
|
||||
reg = <2>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
phy@3 {
|
||||
reg = <3>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
phy@4 {
|
||||
reg = <4>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
phy@5 {
|
||||
reg = <5>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
phy@6 {
|
||||
reg = <6>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
phy@7 {
|
||||
reg = <7>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,133 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2025, Google LLC
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/google,lga-usb-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Google Tensor Series G5 (Laguna) USB PHY
|
||||
|
||||
maintainers:
|
||||
- Roy Luo <royluo@google.com>
|
||||
|
||||
description:
|
||||
Describes the USB PHY interfaces integrated with the DWC3 USB controller on
|
||||
Google Tensor SoCs, starting with the G5 generation (laguna).
|
||||
Two specific PHY IPs from Synopsys are integrated, including eUSB 2.0 PHY IP
|
||||
and USB3.2/DisplayPort combo PHY IP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,lga-usb-phy
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: USB3.2/DisplayPort combo PHY core registers.
|
||||
- description: USB3.2/DisplayPort combo PHY Type-C Assist registers.
|
||||
- description: eUSB 2.0 PHY core registers.
|
||||
- description: Top-level wrapper registers for the integrated PHYs.
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: usb3_core
|
||||
- const: usb3_tca
|
||||
- const: usb2_core
|
||||
- const: usbdp_top
|
||||
|
||||
"#phy-cells":
|
||||
description: |
|
||||
The phandle's argument in the PHY specifier selects one of the three
|
||||
following PHY interfaces.
|
||||
- 0 for USB high-speed.
|
||||
- 1 for USB super-speed.
|
||||
- 2 for DisplayPort.
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: USB2 PHY clock.
|
||||
- description: USB2 PHY APB clock.
|
||||
- description: USB3.2/DisplayPort combo PHY clock.
|
||||
- description: USB3.2/DisplayPort combo PHY firmware clock.
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: usb2
|
||||
- const: usb2_apb
|
||||
- const: usb3
|
||||
- const: usb3_fw
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: USB2 PHY reset.
|
||||
- description: USB2 PHY APB reset.
|
||||
- description: USB3.2/DisplayPort combo PHY reset.
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: usb2
|
||||
- const: usb2_apb
|
||||
- const: usb3
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
orientation-switch:
|
||||
type: boolean
|
||||
description:
|
||||
Indicates the PHY as a handler of USB Type-C orientation changes
|
||||
|
||||
google,usb-cfg-csr:
|
||||
description:
|
||||
A phandle to a syscon node used to access the USB configuration
|
||||
registers. These registers are the top-level wrapper of the USB
|
||||
subsystem and provide control and status for the integrated USB
|
||||
controller and USB PHY.
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to the syscon node.
|
||||
- description: USB2 PHY configuration register offset.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- "#phy-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- orientation-switch
|
||||
- google,usb-cfg-csr
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
usb-phy@c410000 {
|
||||
compatible = "google,lga-usb-phy";
|
||||
reg = <0 0x0c410000 0 0x20000>,
|
||||
<0 0x0c430000 0 0x1000>,
|
||||
<0 0x0c440000 0 0x10000>,
|
||||
<0 0x0c637000 0 0xa0>;
|
||||
reg-names = "usb3_core", "usb3_tca", "usb2_core", "usbdp_top";
|
||||
#phy-cells = <1>;
|
||||
clocks = <&hsion_usb2_phy_clk>, <&hsion_u2phy_apb_clk>,
|
||||
<&hsion_usb3_phy_clk>, <&hsion_usb3_phy_fw_clk>;
|
||||
clock-names = "usb2", "usb2_apb", "usb3", "usb3_fw";
|
||||
resets = <&hsion_resets_usb2_phy>,
|
||||
<&hsion_resets_u2phy_apb>,
|
||||
<&hsion_resets_usb3_phy>;
|
||||
reset-names = "usb2", "usb2_apb", "usb3";
|
||||
power-domains = <&hsio_n_usb_pd>;
|
||||
orientation-switch;
|
||||
google,usb-cfg-csr = <&usb_cfg_csr 0x14>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@@ -18,6 +18,7 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,glymur-dp-phy
|
||||
- qcom,sa8775p-edp-phy
|
||||
- qcom,sc7280-edp-phy
|
||||
- qcom,sc8180x-edp-phy
|
||||
@@ -37,12 +38,15 @@ properties:
|
||||
- description: PLL register block
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: aux
|
||||
- const: cfg_ahb
|
||||
- const: ref
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
@@ -64,6 +68,30 @@ required:
|
||||
- "#clock-cells"
|
||||
- "#phy-cells"
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-dp-phy
|
||||
- qcom,x1e80100-dp-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
clock-names:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -15,9 +15,13 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,sm8750-m31-eusb2-phy
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,glymur-m31-eusb2-phy
|
||||
- qcom,kaanapali-m31-eusb2-phy
|
||||
- const: qcom,sm8750-m31-eusb2-phy
|
||||
- const: qcom,sm8750-m31-eusb2-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615)
|
||||
|
||||
maintainers:
|
||||
- Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
|
||||
|
||||
description:
|
||||
The QMP PHY controller supports physical layer functionality for both USB3
|
||||
and DisplayPort over USB-C. While it enables mode switching between USB3 and
|
||||
DisplayPort, but does not support combo mode.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs615-qmp-usb3-dp-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: aux
|
||||
- const: ref
|
||||
- const: cfg_ahb
|
||||
- const: pipe
|
||||
|
||||
resets:
|
||||
maxItems: 2
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: phy_phy
|
||||
- const: dp_phy
|
||||
|
||||
vdda-phy-supply: true
|
||||
|
||||
vdda-pll-supply: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description:
|
||||
See include/dt-bindings/phy/phy-qcom-qmp.h
|
||||
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
description:
|
||||
See include/dt-bindings/phy/phy-qcom-qmp.h
|
||||
|
||||
qcom,tcsr-reg:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle to TCSR hardware block
|
||||
- description: offset of the VLS CLAMP register
|
||||
- description: offset of the PHY mode register
|
||||
description: Clamp and PHY mode register present in the TCSR
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- vdda-phy-supply
|
||||
- vdda-pll-supply
|
||||
- "#clock-cells"
|
||||
- "#phy-cells"
|
||||
- qcom,tcsr-reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
phy@88e8000 {
|
||||
compatible = "qcom,qcs615-qmp-usb3-dp-phy";
|
||||
reg = <0x88e8000 0x2000>;
|
||||
|
||||
clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||||
<&gcc GCC_AHB2PHY_WEST_CLK>,
|
||||
<&gcc GCC_USB2_SEC_PHY_PIPE_CLK>;
|
||||
clock-names = "aux",
|
||||
"ref",
|
||||
"cfg_ahb",
|
||||
"pipe";
|
||||
|
||||
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
|
||||
<&gcc GCC_USB3_DP_PHY_SEC_BCR>;
|
||||
reset-names = "phy_phy",
|
||||
"dp_phy";
|
||||
|
||||
vdda-phy-supply = <&vreg_l5a>;
|
||||
vdda-pll-supply = <&vreg_l12a>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
#phy-cells = <1>;
|
||||
|
||||
qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>;
|
||||
};
|
||||
@@ -16,7 +16,9 @@ description:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-qmp-gen4x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen5x4-pcie-phy
|
||||
- qcom,kaanapali-qmp-gen3x2-pcie-phy
|
||||
- qcom,qcs615-qmp-gen3x1-pcie-phy
|
||||
- qcom,qcs8300-qmp-gen4x2-pcie-phy
|
||||
- qcom,sa8775p-qmp-gen4x2-pcie-phy
|
||||
@@ -146,6 +148,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,kaanapali-qmp-gen3x2-pcie-phy
|
||||
- qcom,qcs615-qmp-gen3x1-pcie-phy
|
||||
- qcom,sar2130p-qmp-gen3x2-pcie-phy
|
||||
- qcom,sc8180x-qmp-pcie-phy
|
||||
@@ -178,6 +181,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-qmp-gen4x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen5x4-pcie-phy
|
||||
- qcom,qcs8300-qmp-gen4x2-pcie-phy
|
||||
- qcom,sa8775p-qmp-gen4x2-pcie-phy
|
||||
@@ -202,7 +206,9 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-qmp-gen4x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen5x4-pcie-phy
|
||||
- qcom,kaanapali-qmp-gen3x2-pcie-phy
|
||||
- qcom,sm8550-qmp-gen4x2-pcie-phy
|
||||
- qcom,sm8650-qmp-gen4x2-pcie-phy
|
||||
- qcom,x1e80100-qmp-gen3x2-pcie-phy
|
||||
|
||||
@@ -20,6 +20,10 @@ properties:
|
||||
- enum:
|
||||
- qcom,qcs615-qmp-ufs-phy
|
||||
- const: qcom,sm6115-qmp-ufs-phy
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,x1e80100-qmp-ufs-phy
|
||||
- const: qcom,sm8550-qmp-ufs-phy
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,qcs8300-qmp-ufs-phy
|
||||
@@ -29,6 +33,7 @@ properties:
|
||||
- qcom,kaanapali-qmp-ufs-phy
|
||||
- const: qcom,sm8750-qmp-ufs-phy
|
||||
- enum:
|
||||
- qcom,milos-qmp-ufs-phy
|
||||
- qcom,msm8996-qmp-ufs-phy
|
||||
- qcom,msm8998-qmp-ufs-phy
|
||||
- qcom,sa8775p-qmp-ufs-phy
|
||||
@@ -98,6 +103,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,milos-qmp-ufs-phy
|
||||
- qcom,msm8998-qmp-ufs-phy
|
||||
- qcom,sa8775p-qmp-ufs-phy
|
||||
- qcom,sc7180-qmp-ufs-phy
|
||||
|
||||
@@ -16,6 +16,7 @@ description:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-qmp-usb3-uni-phy
|
||||
- qcom,ipq5424-qmp-usb3-phy
|
||||
- qcom,ipq6018-qmp-usb3-phy
|
||||
- qcom,ipq8074-qmp-usb3-phy
|
||||
@@ -61,6 +62,8 @@ properties:
|
||||
|
||||
vdda-pll-supply: true
|
||||
|
||||
refgen-supply: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
@@ -113,6 +116,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-qmp-usb3-uni-phy
|
||||
- qcom,qcs8300-qmp-usb3-uni-phy
|
||||
- qcom,qdu1000-qmp-usb3-uni-phy
|
||||
- qcom,sa8775p-qmp-usb3-uni-phy
|
||||
@@ -156,6 +160,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-qmp-usb3-uni-phy
|
||||
- qcom,sa8775p-qmp-usb3-uni-phy
|
||||
- qcom,sc8180x-qmp-usb3-uni-phy
|
||||
- qcom,sc8280xp-qmp-usb3-uni-phy
|
||||
@@ -164,6 +169,19 @@ allOf:
|
||||
required:
|
||||
- power-domains
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-qmp-usb3-uni-phy
|
||||
then:
|
||||
required:
|
||||
- refgen-supply
|
||||
else:
|
||||
properties:
|
||||
refgen-supply: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -15,22 +15,28 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sar2130p-qmp-usb3-dp-phy
|
||||
- qcom,sc7180-qmp-usb3-dp-phy
|
||||
- qcom,sc7280-qmp-usb3-dp-phy
|
||||
- qcom,sc8180x-qmp-usb3-dp-phy
|
||||
- qcom,sc8280xp-qmp-usb43dp-phy
|
||||
- qcom,sdm845-qmp-usb3-dp-phy
|
||||
- qcom,sm6350-qmp-usb3-dp-phy
|
||||
- qcom,sm8150-qmp-usb3-dp-phy
|
||||
- qcom,sm8250-qmp-usb3-dp-phy
|
||||
- qcom,sm8350-qmp-usb3-dp-phy
|
||||
- qcom,sm8450-qmp-usb3-dp-phy
|
||||
- qcom,sm8550-qmp-usb3-dp-phy
|
||||
- qcom,sm8650-qmp-usb3-dp-phy
|
||||
- qcom,sm8750-qmp-usb3-dp-phy
|
||||
- qcom,x1e80100-qmp-usb3-dp-phy
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,kaanapali-qmp-usb3-dp-phy
|
||||
- const: qcom,sm8750-qmp-usb3-dp-phy
|
||||
- enum:
|
||||
- qcom,glymur-qmp-usb3-dp-phy
|
||||
- qcom,sar2130p-qmp-usb3-dp-phy
|
||||
- qcom,sc7180-qmp-usb3-dp-phy
|
||||
- qcom,sc7280-qmp-usb3-dp-phy
|
||||
- qcom,sc8180x-qmp-usb3-dp-phy
|
||||
- qcom,sc8280xp-qmp-usb43dp-phy
|
||||
- qcom,sdm845-qmp-usb3-dp-phy
|
||||
- qcom,sm6350-qmp-usb3-dp-phy
|
||||
- qcom,sm8150-qmp-usb3-dp-phy
|
||||
- qcom,sm8250-qmp-usb3-dp-phy
|
||||
- qcom,sm8350-qmp-usb3-dp-phy
|
||||
- qcom,sm8450-qmp-usb3-dp-phy
|
||||
- qcom,sm8550-qmp-usb3-dp-phy
|
||||
- qcom,sm8650-qmp-usb3-dp-phy
|
||||
- qcom,sm8750-qmp-usb3-dp-phy
|
||||
- qcom,x1e80100-qmp-usb3-dp-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -63,6 +69,8 @@ properties:
|
||||
|
||||
vdda-pll-supply: true
|
||||
|
||||
refgen-supply: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
description:
|
||||
@@ -194,14 +202,16 @@ allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sar2130p-qmp-usb3-dp-phy
|
||||
- qcom,sc8280xp-qmp-usb43dp-phy
|
||||
- qcom,sm6350-qmp-usb3-dp-phy
|
||||
- qcom,sm8550-qmp-usb3-dp-phy
|
||||
- qcom,sm8650-qmp-usb3-dp-phy
|
||||
- qcom,sm8750-qmp-usb3-dp-phy
|
||||
- qcom,x1e80100-qmp-usb3-dp-phy
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-qmp-usb3-dp-phy
|
||||
- qcom,sar2130p-qmp-usb3-dp-phy
|
||||
- qcom,sc8280xp-qmp-usb43dp-phy
|
||||
- qcom,sm6350-qmp-usb3-dp-phy
|
||||
- qcom,sm8550-qmp-usb3-dp-phy
|
||||
- qcom,sm8650-qmp-usb3-dp-phy
|
||||
- qcom,sm8750-qmp-usb3-dp-phy
|
||||
- qcom,x1e80100-qmp-usb3-dp-phy
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
@@ -209,6 +219,18 @@ allOf:
|
||||
properties:
|
||||
power-domains: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-qmp-usb3-dp-phy
|
||||
then:
|
||||
required:
|
||||
- refgen-supply
|
||||
else:
|
||||
properties:
|
||||
refgen-supply: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -24,6 +24,7 @@ properties:
|
||||
- qcom,pm8550b-eusb2-repeater
|
||||
- qcom,pmiv0104-eusb2-repeater
|
||||
- qcom,smb2360-eusb2-repeater
|
||||
- qcom,smb2370-eusb2-repeater
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -59,6 +60,14 @@ properties:
|
||||
minimum: 0
|
||||
maximum: 7
|
||||
|
||||
qcom,squelch-detector-bp:
|
||||
description:
|
||||
This adjusts the voltage level for the threshold used to detect valid
|
||||
high-speed data.
|
||||
minimum: -6000
|
||||
maximum: 1000
|
||||
multipleOf: 1000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
@@ -11,7 +11,14 @@ maintainers:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a09g047-usb3-phy
|
||||
oneOf:
|
||||
- const: renesas,r9a09g047-usb3-phy # RZ/G3E
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,r9a09g056-usb3-phy # RZ/V2N
|
||||
- renesas,r9a09g057-usb3-phy # RZ/V2H(P)
|
||||
- const: renesas,r9a09g047-usb3-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -41,7 +41,9 @@ properties:
|
||||
- const: renesas,rzg2l-usb2-phy
|
||||
|
||||
- items:
|
||||
- const: renesas,usb2-phy-r9a09g056 # RZ/V2N
|
||||
- enum:
|
||||
- renesas,usb2-phy-r9a09g047 # RZ/G3E
|
||||
- renesas,usb2-phy-r9a09g056 # RZ/V2N
|
||||
- const: renesas,usb2-phy-r9a09g057
|
||||
|
||||
- const: renesas,usb2-phy-r9a09g077 # RZ/T2H
|
||||
@@ -89,6 +91,12 @@ properties:
|
||||
Phandle to a regulator that provides power to the VBUS. This regulator
|
||||
will be managed during the PHY power on/off sequence.
|
||||
|
||||
vbus-regulator:
|
||||
$ref: /schemas/regulator/regulator.yaml#
|
||||
description: USB VBUS internal regulator
|
||||
type: object
|
||||
unevaluatedProperties: false
|
||||
|
||||
renesas,no-otg-pins:
|
||||
$ref: /schemas/types.yaml#/definitions/flag
|
||||
description: |
|
||||
@@ -96,6 +104,11 @@ properties:
|
||||
|
||||
dr_mode: true
|
||||
|
||||
mux-states:
|
||||
description:
|
||||
phandle to a mux controller node that select the source for USB VBUS.
|
||||
maxItems: 1
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -36,6 +36,9 @@ properties:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
samsung,pmu-syscon:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
|
||||
@@ -34,6 +34,9 @@ properties:
|
||||
- samsung,exynos7870-usbdrd-phy
|
||||
- samsung,exynos850-usbdrd-phy
|
||||
- samsung,exynos990-usbdrd-phy
|
||||
- samsung,exynosautov920-usb31drd-combo-ssphy
|
||||
- samsung,exynosautov920-usbdrd-combo-hsphy
|
||||
- samsung,exynosautov920-usbdrd-phy
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
@@ -51,6 +54,9 @@ properties:
|
||||
settings register. For Exynos5420 this is given as 'sclk_usbphy30'
|
||||
in the CMU. It's not needed for Exynos2200.
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
|
||||
@@ -110,6 +116,15 @@ properties:
|
||||
vddh-usbdp-supply:
|
||||
description: VDDh power supply for the USB DP phy.
|
||||
|
||||
dvdd-supply:
|
||||
description: 0.75V power supply for the USB phy.
|
||||
|
||||
vdd18-supply:
|
||||
description: 1.8V power supply for the USB phy.
|
||||
|
||||
vdd33-supply:
|
||||
description: 3.3V power supply for the USB phy.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
@@ -221,6 +236,9 @@ allOf:
|
||||
- samsung,exynos7870-usbdrd-phy
|
||||
- samsung,exynos850-usbdrd-phy
|
||||
- samsung,exynos990-usbdrd-phy
|
||||
- samsung,exynosautov920-usb31drd-combo-ssphy
|
||||
- samsung,exynosautov920-usbdrd-combo-hsphy
|
||||
- samsung,exynosautov920-usbdrd-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
@@ -238,6 +256,39 @@ allOf:
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-usb31drd-combo-ssphy
|
||||
- samsung,exynosautov920-usbdrd-combo-hsphy
|
||||
- samsung,exynosautov920-usbdrd-phy
|
||||
then:
|
||||
required:
|
||||
- dvdd-supply
|
||||
- vdd18-supply
|
||||
|
||||
else:
|
||||
properties:
|
||||
dvdd-supply: false
|
||||
vdd18-supply: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynosautov920-usbdrd-combo-hsphy
|
||||
- samsung,exynosautov920-usbdrd-phy
|
||||
then:
|
||||
required:
|
||||
- vdd33-supply
|
||||
|
||||
else:
|
||||
properties:
|
||||
vdd33-supply: false
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -0,0 +1,114 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/spacemit,k1-combo-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SpacemiT K1 PCIe/USB3 Combo PHY
|
||||
|
||||
maintainers:
|
||||
- Alex Elder <elder@riscstar.com>
|
||||
|
||||
description: >
|
||||
Of the three PHYs on the SpacemiT K1 SoC capable of being used for
|
||||
PCIe, one is a combo PHY that can also be configured for use by a
|
||||
USB 3 controller. Using PCIe or USB 3 is a board design decision.
|
||||
|
||||
The combo PHY is also the only PCIe PHY that is able to determine
|
||||
PCIe calibration values to use, and this must be determined before
|
||||
the other two PCIe PHYs can be used. This calibration must be
|
||||
performed with the combo PHY in PCIe mode, and is this is done
|
||||
when the combo PHY is probed.
|
||||
|
||||
The combo PHY uses an external oscillator as a reference clock.
|
||||
During normal operation, the PCIe or USB port driver is responsible
|
||||
for ensuring all other clocks needed by a PHY are enabled, and all
|
||||
resets affecting the PHY are deasserted. However, for the combo
|
||||
PHY to perform calibration independent of whether it's later used
|
||||
for PCIe or USB, all PCIe mode clocks and resets must be defined.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spacemit,k1-combo-phy
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: PHY control registers
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: External oscillator used by the PHY PLL
|
||||
- description: DWC PCIe Data Bus Interface (DBI) clock
|
||||
- description: DWC PCIe application AXI-bus Master interface clock
|
||||
- description: DWC PCIe application AXI-bus slave interface clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: refclk
|
||||
- const: dbi
|
||||
- const: mstr
|
||||
- const: slv
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: PHY reset; remains deasserted after initialization
|
||||
- description: DWC PCIe Data Bus Interface (DBI) reset
|
||||
- description: DWC PCIe application AXI-bus Master interface reset
|
||||
- description: DWC PCIe application AXI-bus slave interface reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: phy
|
||||
- const: dbi
|
||||
- const: mstr
|
||||
- const: slv
|
||||
|
||||
spacemit,apmu:
|
||||
description:
|
||||
A phandle that refers to the APMU system controller, whose
|
||||
regmap is used in setting the mode
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
description:
|
||||
The argument value (PHY_TYPE_PCIE or PHY_TYPE_USB3) determines
|
||||
whether the PHY operates in PCIe or USB3 mode.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- spacemit,apmu
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/spacemit,k1-syscon.h>
|
||||
phy@c0b10000 {
|
||||
compatible = "spacemit,k1-combo-phy";
|
||||
reg = <0xc0b10000 0x1000>;
|
||||
clocks = <&vctcxo_24m>,
|
||||
<&syscon_apmu CLK_PCIE0_DBI>,
|
||||
<&syscon_apmu CLK_PCIE0_MASTER>,
|
||||
<&syscon_apmu CLK_PCIE0_SLAVE>;
|
||||
clock-names = "refclk",
|
||||
"dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
|
||||
<&syscon_apmu RESET_PCIE0_DBI>,
|
||||
<&syscon_apmu RESET_PCIE0_MASTER>,
|
||||
<&syscon_apmu RESET_PCIE0_SLAVE>;
|
||||
reset-names = "phy",
|
||||
"dbi",
|
||||
"mstr",
|
||||
"slv";
|
||||
spacemit,apmu = <&syscon_apmu>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,71 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SpacemiT K1 PCIe PHY
|
||||
|
||||
maintainers:
|
||||
- Alex Elder <elder@riscstar.com>
|
||||
|
||||
description: >
|
||||
Two PHYs on the SpacemiT K1 SoC used for only for PCIe. These
|
||||
PHYs must be configured using calibration values that are
|
||||
determined by a third "combo PHY". The combo PHY determines
|
||||
these calibration values during probe so they can be used for
|
||||
the two PCIe-only PHYs.
|
||||
|
||||
The PHY uses an external oscillator as a reference clock. During
|
||||
normal operation, the PCIe host driver is responsible for ensuring
|
||||
all other clocks needed by a PHY are enabled, and all resets
|
||||
affecting the PHY are deasserted.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spacemit,k1-pcie-phy
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: PHY control registers
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: External oscillator used by the PHY PLL
|
||||
|
||||
clock-names:
|
||||
const: refclk
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: PHY reset; remains deasserted after initialization
|
||||
|
||||
reset-names:
|
||||
const: phy
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/spacemit,k1-syscon.h>
|
||||
phy@c0c10000 {
|
||||
compatible = "spacemit,k1-pcie-phy";
|
||||
reg = <0xc0c10000 0x1000>;
|
||||
clocks = <&vctcxo_24m>;
|
||||
clock-names = "refclk";
|
||||
resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
|
||||
reset-names = "phy";
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: SpacemiT K1 SoC USB 2.0 PHY
|
||||
|
||||
maintainers:
|
||||
- Ze Huang <huang.ze@linux.dev>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spacemit,k1-usb2-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#phy-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usb-phy@c09c0000 {
|
||||
compatible = "spacemit,k1-usb2-phy";
|
||||
reg = <0xc09c0000 0x200>;
|
||||
clocks = <&syscon_apmu 15>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
@@ -0,0 +1,99 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI OMAP Control PHY Module
|
||||
|
||||
maintainers:
|
||||
- Roger Quadros <rogerq@ti.com>
|
||||
|
||||
description:
|
||||
The TI OMAP Control PHY module is a hardware block within the system
|
||||
control module (SCM) of Texas Instruments OMAP SoCs. It provides
|
||||
centralized control over power, configuration, and auxiliary features
|
||||
for multiple on-chip PHYs. This module is essential for proper PHY
|
||||
operation in power-constrained embedded systems.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^phy@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- ti,control-phy-otghs
|
||||
- ti,control-phy-pcie
|
||||
- ti,control-phy-pipe3
|
||||
- ti,control-phy-usb2
|
||||
- ti,control-phy-usb2-am437
|
||||
- ti,control-phy-usb2-dra7
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
items:
|
||||
enum: [otghs_control, power, pcie_pcs, control_sma]
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ti,control-phy-otghs
|
||||
then:
|
||||
properties:
|
||||
reg-names:
|
||||
const: otghs_control
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ti,control-phy-pcie
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 3
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: power
|
||||
- const: pcie_pcs
|
||||
- const: control_sma
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- ti,control-phy-usb2
|
||||
- ti,control-phy-usb2-dra7
|
||||
- ti,control-phy-usb2-am437
|
||||
- ti,control-phy-pipe3
|
||||
then:
|
||||
properties:
|
||||
reg-names:
|
||||
const: power
|
||||
|
||||
required:
|
||||
- reg
|
||||
- compatible
|
||||
- reg-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@4a00233c {
|
||||
compatible = "ti,control-phy-otghs";
|
||||
reg = <0x4a00233c 0x4>;
|
||||
reg-names = "otghs_control";
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,138 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI PIPE3 PHY Module
|
||||
|
||||
maintainers:
|
||||
- Roger Quadros <rogerq@ti.com>
|
||||
|
||||
description:
|
||||
The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
|
||||
transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
|
||||
It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
|
||||
interface standard, which defines a common physical layer for
|
||||
high-speed serial interfaces.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- ti,omap-usb3
|
||||
- ti,phy-pipe3-pcie
|
||||
- ti,phy-pipe3-sata
|
||||
- ti,phy-usb3
|
||||
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: phy_rx
|
||||
- const: phy_tx
|
||||
- const: pll_ctrl
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 7
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 7
|
||||
items:
|
||||
enum: [wkupclk, sysclk, refclk, dpll_ref,
|
||||
dpll_ref_m2, phy-div, div-clk]
|
||||
|
||||
syscon-phy-power:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
items:
|
||||
items:
|
||||
- description: Phandle to the system control module
|
||||
- description: Register offset controlling PHY power
|
||||
|
||||
syscon-pllreset:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
items:
|
||||
items:
|
||||
- description: Phandle to the system control module
|
||||
- description: Register offset of CTRL_CORE_SMA_SW_0
|
||||
|
||||
syscon-pcs:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
maxItems: 1
|
||||
items:
|
||||
items:
|
||||
- description: Phandle to the system control module
|
||||
- description: Register offset for PCS delay programming
|
||||
|
||||
ctrl-module:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle of control module for PHY power on.
|
||||
deprecated: true
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,phy-pipe3-sata
|
||||
then:
|
||||
properties:
|
||||
syscon-pllreset: true
|
||||
else:
|
||||
properties:
|
||||
syscon-pllreset: false
|
||||
|
||||
required:
|
||||
- reg
|
||||
- compatible
|
||||
- reg-names
|
||||
- "#phy-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/* TI PIPE3 USB3 PHY */
|
||||
usb3-phy@4a084400 {
|
||||
compatible = "ti,phy-usb3";
|
||||
reg = <0x4a084400 0x80>,
|
||||
<0x4a084800 0x64>,
|
||||
<0x4a084c00 0x40>;
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
#phy-cells = <0>;
|
||||
clocks = <&usb_phy_cm_clk32k>,
|
||||
<&sys_clkin>,
|
||||
<&usb_otg_ss_refclk960m>;
|
||||
clock-names = "wkupclk", "sysclk", "refclk";
|
||||
ctrl-module = <&omap_control_usb>;
|
||||
};
|
||||
|
||||
- |
|
||||
/* TI PIPE3 SATA PHY */
|
||||
phy@4a096000 {
|
||||
compatible = "ti,phy-pipe3-sata";
|
||||
reg = <0x4a096000 0x80>, /* phy_rx */
|
||||
<0x4a096400 0x64>, /* phy_tx */
|
||||
<0x4a096800 0x40>; /* pll_ctrl */
|
||||
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
||||
clocks = <&sys_clkin1>, <&sata_ref_clk>;
|
||||
clock-names = "sysclk", "refclk";
|
||||
syscon-pllreset = <&scm_conf 0x3fc>;
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
...
|
||||
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Reference in New Issue
Block a user