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https://github.com/linux-msm/laptops-kernel.git
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Merge tag 'char-misc-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char / misc driver updates from Greg KH: "Here is the "large" pull request for char and misc and other assorted smaller driver subsystems for 5.3-rc1. It seems that this tree is becoming the funnel point of lots of smaller driver subsystems, which is fine for me, but that's why it is getting larger over time and does not just contain stuff under drivers/char/ and drivers/misc. Lots of small updates all over the place here from different driver subsystems: - habana driver updates - coresight driver updates - documentation file movements and updates - Android binder fixes and updates - extcon driver updates - google firmware driver updates - fsi driver updates - smaller misc and char driver updates - soundwire driver updates - nvmem driver updates - w1 driver fixes All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-5.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (188 commits) coresight: Do not default to CPU0 for missing CPU phandle dt-bindings: coresight: Change CPU phandle to required property ocxl: Allow contexts to be attached with a NULL mm fsi: sbefifo: Don't fail operations when in SBE IPL state coresight: tmc: Smatch: Fix potential NULL pointer dereference coresight: etm3x: Smatch: Fix potential NULL pointer dereference coresight: Potential uninitialized variable in probe() coresight: etb10: Do not call smp_processor_id from preemptible coresight: tmc-etf: Do not call smp_processor_id from preemptible coresight: tmc-etr: alloc_perf_buf: Do not call smp_processor_id from preemptible coresight: tmc-etr: Do not call smp_processor_id() from preemptible docs: misc-devices: convert files without extension to ReST fpga: dfl: fme: align PR buffer size per PR datawidth fpga: dfl: fme: remove copy_to_user() in ioctl for PR fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address. intel_th: msu: Start read iterator from a non-empty window intel_th: msu: Split sgt array and pointer in multiwindow mode intel_th: msu: Support multipage blocks intel_th: pci: Add Ice Lake NNPI support intel_th: msu: Fix single mode with disabled IOMMU ...
This commit is contained in:
Linus Torvalds
@@ -3,7 +3,10 @@ Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Sets the device address to be used for read or write through
|
||||
PCI bar. The acceptable value is a string that starts with "0x"
|
||||
PCI bar, or the device VA of a host mapped memory to be read or
|
||||
written directly from the host. The latter option is allowed
|
||||
only when the IOMMU is disabled.
|
||||
The acceptable value is a string that starts with "0x"
|
||||
|
||||
What: /sys/kernel/debug/habanalabs/hl<n>/command_buffers
|
||||
Date: Jan 2019
|
||||
@@ -33,10 +36,12 @@ Contact: oded.gabbay@gmail.com
|
||||
Description: Allows the root user to read or write directly through the
|
||||
device's PCI bar. Writing to this file generates a write
|
||||
transaction while reading from the file generates a read
|
||||
transcation. This custom interface is needed (instead of using
|
||||
transaction. This custom interface is needed (instead of using
|
||||
the generic Linux user-space PCI mapping) because the DDR bar
|
||||
is very small compared to the DDR memory and only the driver can
|
||||
move the bar before and after the transaction
|
||||
move the bar before and after the transaction.
|
||||
If the IOMMU is disabled, it also allows the root user to read
|
||||
or write from the host a device VA of a host mapped memory
|
||||
|
||||
What: /sys/kernel/debug/habanalabs/hl<n>/device
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||||
Date: Jan 2019
|
||||
@@ -46,6 +51,13 @@ Description: Enables the root user to set the device to specific state.
|
||||
Valid values are "disable", "enable", "suspend", "resume".
|
||||
User can read this property to see the valid values
|
||||
|
||||
What: /sys/kernel/debug/habanalabs/hl<n>/engines
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||||
Date: Jul 2019
|
||||
KernelVersion: 5.3
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Displays the status registers values of the device engines and
|
||||
their derived idle status
|
||||
|
||||
What: /sys/kernel/debug/habanalabs/hl<n>/i2c_addr
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||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
|
||||
@@ -62,18 +62,20 @@ What: /sys/class/habanalabs/hl<n>/ic_clk
|
||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Allows the user to set the maximum clock frequency of the
|
||||
Interconnect fabric. Writes to this parameter affect the device
|
||||
only when the power management profile is set to "manual" mode.
|
||||
The device IC clock might be set to lower value then the
|
||||
Description: Allows the user to set the maximum clock frequency, in Hz, of
|
||||
the Interconnect fabric. Writes to this parameter affect the
|
||||
device only when the power management profile is set to "manual"
|
||||
mode. The device IC clock might be set to lower value than the
|
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maximum. The user should read the ic_clk_curr to see the actual
|
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frequency value of the IC
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frequency value of the IC. This property is valid only for the
|
||||
Goya ASIC family
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||||
|
||||
What: /sys/class/habanalabs/hl<n>/ic_clk_curr
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||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Displays the current clock frequency of the Interconnect fabric
|
||||
Description: Displays the current clock frequency, in Hz, of the Interconnect
|
||||
fabric. This property is valid only for the Goya ASIC family
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/infineon_ver
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Date: Jan 2019
|
||||
@@ -92,18 +94,20 @@ What: /sys/class/habanalabs/hl<n>/mme_clk
|
||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Allows the user to set the maximum clock frequency of the
|
||||
MME compute engine. Writes to this parameter affect the device
|
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only when the power management profile is set to "manual" mode.
|
||||
The device MME clock might be set to lower value then the
|
||||
Description: Allows the user to set the maximum clock frequency, in Hz, of
|
||||
the MME compute engine. Writes to this parameter affect the
|
||||
device only when the power management profile is set to "manual"
|
||||
mode. The device MME clock might be set to lower value than the
|
||||
maximum. The user should read the mme_clk_curr to see the actual
|
||||
frequency value of the MME
|
||||
frequency value of the MME. This property is valid only for the
|
||||
Goya ASIC family
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/mme_clk_curr
|
||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Displays the current clock frequency of the MME compute engine
|
||||
Description: Displays the current clock frequency, in Hz, of the MME compute
|
||||
engine. This property is valid only for the Goya ASIC family
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/pci_addr
|
||||
Date: Jan 2019
|
||||
@@ -163,18 +167,20 @@ What: /sys/class/habanalabs/hl<n>/tpc_clk
|
||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Allows the user to set the maximum clock frequency of the
|
||||
TPC compute engines. Writes to this parameter affect the device
|
||||
only when the power management profile is set to "manual" mode.
|
||||
The device TPC clock might be set to lower value then the
|
||||
Description: Allows the user to set the maximum clock frequency, in Hz, of
|
||||
the TPC compute engines. Writes to this parameter affect the
|
||||
device only when the power management profile is set to "manual"
|
||||
mode. The device TPC clock might be set to lower value than the
|
||||
maximum. The user should read the tpc_clk_curr to see the actual
|
||||
frequency value of the TPC
|
||||
frequency value of the TPC. This property is valid only for
|
||||
Goya ASIC family
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/tpc_clk_curr
|
||||
Date: Jan 2019
|
||||
KernelVersion: 5.1
|
||||
Contact: oded.gabbay@gmail.com
|
||||
Description: Displays the current clock frequency of the TPC compute engines
|
||||
Description: Displays the current clock frequency, in Hz, of the TPC compute
|
||||
engines. This property is valid only for the Goya ASIC family
|
||||
|
||||
What: /sys/class/habanalabs/hl<n>/uboot_ver
|
||||
Date: Jan 2019
|
||||
|
||||
@@ -26,8 +26,8 @@ Required properties:
|
||||
processor core is clocked by the internal CPU clock, so it
|
||||
is enabled with CPU clock by default.
|
||||
|
||||
- cpu : the CPU phandle the debug module is affined to. When omitted
|
||||
the module is considered to belong to CPU0.
|
||||
- cpu : the CPU phandle the debug module is affined to. Do not assume it
|
||||
to default to CPU0 if omitted.
|
||||
|
||||
Optional properties:
|
||||
|
||||
|
||||
@@ -59,6 +59,11 @@ its hardware characteristcs.
|
||||
|
||||
* port or ports: see "Graph bindings for Coresight" below.
|
||||
|
||||
* Additional required property for Embedded Trace Macrocell (version 3.x and
|
||||
version 4.x):
|
||||
* cpu: the cpu phandle this ETM/PTM is affined to. Do not
|
||||
assume it to default to CPU0 if omitted.
|
||||
|
||||
* Additional required properties for System Trace Macrocells (STM):
|
||||
* reg: along with the physical base address and length of the register
|
||||
set as described above, another entry is required to describe the
|
||||
@@ -87,9 +92,6 @@ its hardware characteristcs.
|
||||
* arm,cp14: must be present if the system accesses ETM/PTM management
|
||||
registers via co-processor 14.
|
||||
|
||||
* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
|
||||
source is considered to belong to CPU0.
|
||||
|
||||
* Optional property for TMC:
|
||||
|
||||
* arm,buffer-size: size of contiguous buffer space for TMC ETR
|
||||
|
||||
@@ -133,6 +133,18 @@ RTC bindings based on SCU Message Protocol
|
||||
Required properties:
|
||||
- compatible: should be "fsl,imx8qxp-sc-rtc";
|
||||
|
||||
OCOTP bindings based on SCU Message Protocol
|
||||
------------------------------------------------------------
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx8qxp-scu-ocotp"
|
||||
- #address-cells: Must be 1. Contains byte index
|
||||
- #size-cells: Must be 1. Contains byte length
|
||||
|
||||
Optional Child nodes:
|
||||
|
||||
- Data cells of ocotp:
|
||||
Detailed bindings are described in bindings/nvmem/nvmem.txt
|
||||
|
||||
Example (imx8qxp):
|
||||
-------------
|
||||
aliases {
|
||||
@@ -177,6 +189,16 @@ firmware {
|
||||
...
|
||||
};
|
||||
|
||||
ocotp: imx8qx-ocotp {
|
||||
compatible = "fsl,imx8qxp-scu-ocotp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
fec_mac0: mac@2c4 {
|
||||
reg = <0x2c4 8>;
|
||||
};
|
||||
};
|
||||
|
||||
pd: imx8qx-pd {
|
||||
compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
FAIRCHILD SEMICONDUCTOR FSA9480 MICROUSB SWITCH
|
||||
|
||||
The FSA9480 is a USB port accessory detector and switch. The FSA9480 is fully
|
||||
controlled using I2C and enables USB data, stereo and mono audio, video,
|
||||
microphone, and UART data to use a common connector port.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "fcs,fsa9480"
|
||||
- reg : Specifies i2c slave address. Must be 0x25.
|
||||
- interrupts : Should contain one entry specifying interrupt signal of
|
||||
interrupt parent to which interrupt pin of the chip is connected.
|
||||
|
||||
Example:
|
||||
musb@25 {
|
||||
compatible = "fcs,fsa9480";
|
||||
reg = <0x25>;
|
||||
interrupt-parent = <&gph2>;
|
||||
interrupts = <7 0>;
|
||||
};
|
||||
@@ -5,6 +5,7 @@ controller in Ingenic JZ4780
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be set to one of:
|
||||
"ingenic,jz4740-nemc" (JZ4740)
|
||||
"ingenic,jz4780-nemc" (JZ4780)
|
||||
- reg: Should specify the NEMC controller registers location and length.
|
||||
- clocks: Clock for the NEMC controller.
|
||||
|
||||
@@ -0,0 +1,58 @@
|
||||
* Xilinx SDFEC(16nm) IP *
|
||||
|
||||
The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
|
||||
which provides high-throughput LDPC and Turbo Code implementations.
|
||||
The LDPC decode & encode functionality is capable of covering a range of
|
||||
customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
|
||||
principally covers codes used by LTE. The FEC Engine offers significant
|
||||
power and area savings versus implementations done in the FPGA fabric.
|
||||
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "xlnx,sd-fec-1.1"
|
||||
- clock-names : List of input clock names from the following:
|
||||
- "core_clk", Main processing clock for processing core (required)
|
||||
- "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
|
||||
- "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
|
||||
- "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
|
||||
- "s_axis_ctrl_aclk", Control input AXI4-Stream Slave interface clock (optional)
|
||||
- "m_axis_dout_aclk", DOUT AXI4-Stream Master interface clock (optional)
|
||||
- "m_axis_dout_words_aclk", DOUT_WORDS AXI4-Stream Master interface clock (optional)
|
||||
- "m_axis_status_aclk", Status output AXI4-Stream Master interface clock (optional)
|
||||
- clocks : Clock phandles (see clock_bindings.txt for details).
|
||||
- reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
|
||||
location and length.
|
||||
- xlnx,sdfec-code : Should contain "ldpc" or "turbo" to describe the codes
|
||||
being used.
|
||||
- xlnx,sdfec-din-words : A value 0 indicates that the DIN_WORDS interface is
|
||||
driven with a fixed value and is not present on the device, a value of 1
|
||||
configures the DIN_WORDS to be block based, while a value of 2 configures the
|
||||
DIN_WORDS input to be supplied for each AXI transaction.
|
||||
- xlnx,sdfec-din-width : Configures the DIN AXI stream where a value of 1
|
||||
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
|
||||
of "4x128b".
|
||||
- xlnx,sdfec-dout-words : A value 0 indicates that the DOUT_WORDS interface is
|
||||
driven with a fixed value and is not present on the device, a value of 1
|
||||
configures the DOUT_WORDS to be block based, while a value of 2 configures the
|
||||
DOUT_WORDS input to be supplied for each AXI transaction.
|
||||
- xlnx,sdfec-dout-width : Configures the DOUT AXI stream where a value of 1
|
||||
configures a width of "1x128b", 2 a width of "2x128b" and 4 configures a width
|
||||
of "4x128b".
|
||||
Optional properties:
|
||||
- interrupts: should contain SDFEC interrupt number
|
||||
|
||||
Example
|
||||
---------------------------------------
|
||||
sd_fec_0: sd-fec@a0040000 {
|
||||
compatible = "xlnx,sd-fec-1.1";
|
||||
clock-names = "core_clk","s_axi_aclk","s_axis_ctrl_aclk","s_axis_din_aclk","m_axis_status_aclk","m_axis_dout_aclk";
|
||||
clocks = <&misc_clk_2>,<&misc_clk_0>,<&misc_clk_1>,<&misc_clk_1>,<&misc_clk_1>, <&misc_clk_1>;
|
||||
reg = <0x0 0xa0040000 0x0 0x40000>;
|
||||
interrupt-parent = <&axi_intc>;
|
||||
interrupts = <1 0>;
|
||||
xlnx,sdfec-code = "ldpc";
|
||||
xlnx,sdfec-din-words = <0>;
|
||||
xlnx,sdfec-din-width = <2>;
|
||||
xlnx,sdfec-dout-words = <0>;
|
||||
xlnx,sdfec-dout-width = <1>;
|
||||
};
|
||||
@@ -1,60 +0,0 @@
|
||||
MMIO register bitfield-based multiplexer controller bindings
|
||||
|
||||
Define register bitfields to be used to control multiplexers. The parent
|
||||
device tree node must be a syscon node to provide register access.
|
||||
|
||||
Required properties:
|
||||
- compatible : "mmio-mux"
|
||||
- #mux-control-cells : <1>
|
||||
- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
|
||||
pairs, each describing a single mux control.
|
||||
* Standard mux-controller bindings as decribed in mux-controller.txt
|
||||
|
||||
Optional properties:
|
||||
- idle-states : if present, the state the muxes will have when idle. The
|
||||
special state MUX_IDLE_AS_IS is the default.
|
||||
|
||||
The multiplexer state of each multiplexer is defined as the value of the
|
||||
bitfield described by the corresponding register offset and bitfield mask pair
|
||||
in the mux-reg-masks array, accessed through the parent syscon.
|
||||
|
||||
Example:
|
||||
|
||||
syscon {
|
||||
compatible = "syscon";
|
||||
|
||||
mux: mux-controller {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
|
||||
mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
|
||||
<0x3 0x40>, /* 1: reg 0x3, bit 6 */
|
||||
idle-states = <MUX_IDLE_AS_IS>, <0>;
|
||||
};
|
||||
};
|
||||
|
||||
video-mux {
|
||||
compatible = "video-mux";
|
||||
mux-controls = <&mux 0>;
|
||||
|
||||
ports {
|
||||
/* inputs 0..3 */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
/* output */
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,129 @@
|
||||
Generic register bitfield-based multiplexer controller bindings
|
||||
|
||||
Define register bitfields to be used to control multiplexers. The parent
|
||||
device tree node must be a device node to provide register r/w access.
|
||||
|
||||
Required properties:
|
||||
- compatible : should be one of
|
||||
"reg-mux" : if parent device of mux controller is not syscon device
|
||||
"mmio-mux" : if parent device of mux controller is syscon device
|
||||
- #mux-control-cells : <1>
|
||||
- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
|
||||
pairs, each describing a single mux control.
|
||||
* Standard mux-controller bindings as decribed in mux-controller.txt
|
||||
|
||||
Optional properties:
|
||||
- idle-states : if present, the state the muxes will have when idle. The
|
||||
special state MUX_IDLE_AS_IS is the default.
|
||||
|
||||
The multiplexer state of each multiplexer is defined as the value of the
|
||||
bitfield described by the corresponding register offset and bitfield mask
|
||||
pair in the mux-reg-masks array.
|
||||
|
||||
Example 1:
|
||||
The parent device of mux controller is not a syscon device.
|
||||
|
||||
&i2c0 {
|
||||
fpga@66 { // fpga connected to i2c
|
||||
compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
|
||||
"simple-mfd";
|
||||
reg = <0x66>;
|
||||
|
||||
mux: mux-controller {
|
||||
compatible = "reg-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
|
||||
<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio-mux-1 {
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mux 0>;
|
||||
mdio-parent-bus = <&emdio1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mdio@8 {
|
||||
reg = <0x8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
..
|
||||
..
|
||||
};
|
||||
|
||||
mdio-mux-2 {
|
||||
compatible = "mdio-mux-multiplexer";
|
||||
mux-controls = <&mux 1>;
|
||||
mdio-parent-bus = <&emdio2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
mdio@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
..
|
||||
..
|
||||
};
|
||||
|
||||
Example 2:
|
||||
The parent device of mux controller is syscon device.
|
||||
|
||||
syscon {
|
||||
compatible = "syscon";
|
||||
|
||||
mux: mux-controller {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
|
||||
mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
|
||||
<0x3 0x40>, /* 1: reg 0x3, bit 6 */
|
||||
idle-states = <MUX_IDLE_AS_IS>, <0>;
|
||||
};
|
||||
};
|
||||
|
||||
video-mux {
|
||||
compatible = "video-mux";
|
||||
mux-controls = <&mux 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ports {
|
||||
/* inputs 0..3 */
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
|
||||
/* output */
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/nvmem/allwinner,sun4i-a10-sid.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Allwinner A10 Security ID Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Chen-Yu Tsai <wens@csie.org>
|
||||
- Maxime Ripard <maxime.ripard@bootlin.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "nvmem.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- allwinner,sun4i-a10-sid
|
||||
- allwinner,sun7i-a20-sid
|
||||
- allwinner,sun8i-a83t-sid
|
||||
- allwinner,sun8i-h3-sid
|
||||
- allwinner,sun50i-a64-sid
|
||||
- allwinner,sun50i-h5-sid
|
||||
- allwinner,sun50i-h6-sid
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
# FIXME: We should set it, but it would report all the generic
|
||||
# properties as additional properties.
|
||||
# additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sid@1c23800 {
|
||||
compatible = "allwinner,sun4i-a10-sid";
|
||||
reg = <0x01c23800 0x10>;
|
||||
};
|
||||
|
||||
- |
|
||||
sid@1c23800 {
|
||||
compatible = "allwinner,sun7i-a20-sid";
|
||||
reg = <0x01c23800 0x200>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -1,29 +0,0 @@
|
||||
Allwinner sunxi-sid
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of the following:
|
||||
"allwinner,sun4i-a10-sid"
|
||||
"allwinner,sun7i-a20-sid"
|
||||
"allwinner,sun8i-a83t-sid"
|
||||
"allwinner,sun8i-h3-sid"
|
||||
"allwinner,sun50i-a64-sid"
|
||||
"allwinner,sun50i-h5-sid"
|
||||
"allwinner,sun50i-h6-sid"
|
||||
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
= Data cells =
|
||||
Are child nodes of sunxi-sid, bindings of which as described in
|
||||
bindings/nvmem/nvmem.txt
|
||||
|
||||
Example for sun4i:
|
||||
sid@1c23800 {
|
||||
compatible = "allwinner,sun4i-a10-sid";
|
||||
reg = <0x01c23800 0x10>
|
||||
};
|
||||
|
||||
Example for sun7i:
|
||||
sid@1c23800 {
|
||||
compatible = "allwinner,sun7i-a20-sid";
|
||||
reg = <0x01c23800 0x200>
|
||||
};
|
||||
@@ -15,6 +15,7 @@ Required properties:
|
||||
"fsl,imx6sll-ocotp" (i.MX6SLL),
|
||||
"fsl,imx7ulp-ocotp" (i.MX7ULP),
|
||||
"fsl,imx8mq-ocotp" (i.MX8MQ),
|
||||
"fsl,imx8mm-ocotp" (i.MX8MM),
|
||||
followed by "syscon".
|
||||
- #address-cells : Should be 1
|
||||
- #size-cells : Should be 1
|
||||
|
||||
@@ -42,6 +42,7 @@ available subsections can be seen below.
|
||||
target
|
||||
mtdnand
|
||||
miscellaneous
|
||||
mei/index
|
||||
w1
|
||||
rapidio
|
||||
s390-drivers
|
||||
|
||||
@@ -0,0 +1,32 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
HDCP:
|
||||
=====
|
||||
|
||||
ME FW as a security engine provides the capability for setting up
|
||||
HDCP2.2 protocol negotiation between the Intel graphics device and
|
||||
an HDC2.2 sink.
|
||||
|
||||
ME FW prepares HDCP2.2 negotiation parameters, signs and encrypts them
|
||||
according the HDCP 2.2 spec. The Intel graphics sends the created blob
|
||||
to the HDCP2.2 sink.
|
||||
|
||||
Similarly, the HDCP2.2 sink's response is transferred to ME FW
|
||||
for decryption and verification.
|
||||
|
||||
Once all the steps of HDCP2.2 negotiation are completed,
|
||||
upon request ME FW will configure the port as authenticated and supply
|
||||
the HDCP encryption keys to Intel graphics hardware.
|
||||
|
||||
|
||||
mei_hdcp driver
|
||||
---------------
|
||||
.. kernel-doc:: drivers/misc/mei/hdcp/mei_hdcp.c
|
||||
:doc: MEI_HDCP Client Driver
|
||||
|
||||
mei_hdcp api
|
||||
------------
|
||||
|
||||
.. kernel-doc:: drivers/misc/mei/hdcp/mei_hdcp.c
|
||||
:functions:
|
||||
|
||||
@@ -0,0 +1,101 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
Intel(R) Active Management Technology (Intel AMT)
|
||||
=================================================
|
||||
|
||||
Prominent usage of the Intel ME Interface is to communicate with Intel(R)
|
||||
Active Management Technology (Intel AMT) implemented in firmware running on
|
||||
the Intel ME.
|
||||
|
||||
Intel AMT provides the ability to manage a host remotely out-of-band (OOB)
|
||||
even when the operating system running on the host processor has crashed or
|
||||
is in a sleep state.
|
||||
|
||||
Some examples of Intel AMT usage are:
|
||||
- Monitoring hardware state and platform components
|
||||
- Remote power off/on (useful for green computing or overnight IT
|
||||
maintenance)
|
||||
- OS updates
|
||||
- Storage of useful platform information such as software assets
|
||||
- Built-in hardware KVM
|
||||
- Selective network isolation of Ethernet and IP protocol flows based
|
||||
on policies set by a remote management console
|
||||
- IDE device redirection from remote management console
|
||||
|
||||
Intel AMT (OOB) communication is based on SOAP (deprecated
|
||||
starting with Release 6.0) over HTTP/S or WS-Management protocol over
|
||||
HTTP/S that are received from a remote management console application.
|
||||
|
||||
For more information about Intel AMT:
|
||||
https://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/default.htm
|
||||
|
||||
|
||||
Intel AMT Applications
|
||||
----------------------
|
||||
|
||||
1) Intel Local Management Service (Intel LMS)
|
||||
|
||||
Applications running locally on the platform communicate with Intel AMT Release
|
||||
2.0 and later releases in the same way that network applications do via SOAP
|
||||
over HTTP (deprecated starting with Release 6.0) or with WS-Management over
|
||||
SOAP over HTTP. This means that some Intel AMT features can be accessed from a
|
||||
local application using the same network interface as a remote application
|
||||
communicating with Intel AMT over the network.
|
||||
|
||||
When a local application sends a message addressed to the local Intel AMT host
|
||||
name, the Intel LMS, which listens for traffic directed to the host name,
|
||||
intercepts the message and routes it to the Intel MEI.
|
||||
For more information:
|
||||
https://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/default.htm
|
||||
Under "About Intel AMT" => "Local Access"
|
||||
|
||||
For downloading Intel LMS:
|
||||
https://github.com/intel/lms
|
||||
|
||||
The Intel LMS opens a connection using the Intel MEI driver to the Intel LMS
|
||||
firmware feature using a defined GUID and then communicates with the feature
|
||||
using a protocol called Intel AMT Port Forwarding Protocol (Intel APF protocol).
|
||||
The protocol is used to maintain multiple sessions with Intel AMT from a
|
||||
single application.
|
||||
|
||||
See the protocol specification in the Intel AMT Software Development Kit (SDK)
|
||||
https://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/default.htm
|
||||
Under "SDK Resources" => "Intel(R) vPro(TM) Gateway (MPS)"
|
||||
=> "Information for Intel(R) vPro(TM) Gateway Developers"
|
||||
=> "Description of the Intel AMT Port Forwarding (APF) Protocol"
|
||||
|
||||
2) Intel AMT Remote configuration using a Local Agent
|
||||
|
||||
A Local Agent enables IT personnel to configure Intel AMT out-of-the-box
|
||||
without requiring installing additional data to enable setup. The remote
|
||||
configuration process may involve an ISV-developed remote configuration
|
||||
agent that runs on the host.
|
||||
For more information:
|
||||
https://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/default.htm
|
||||
Under "Setup and Configuration of Intel AMT" =>
|
||||
"SDK Tools Supporting Setup and Configuration" =>
|
||||
"Using the Local Agent Sample"
|
||||
|
||||
Intel AMT OS Health Watchdog
|
||||
----------------------------
|
||||
|
||||
The Intel AMT Watchdog is an OS Health (Hang/Crash) watchdog.
|
||||
Whenever the OS hangs or crashes, Intel AMT will send an event
|
||||
to any subscriber to this event. This mechanism means that
|
||||
IT knows when a platform crashes even when there is a hard failure on the host.
|
||||
|
||||
The Intel AMT Watchdog is composed of two parts:
|
||||
1) Firmware feature - receives the heartbeats
|
||||
and sends an event when the heartbeats stop.
|
||||
2) Intel MEI iAMT watchdog driver - connects to the watchdog feature,
|
||||
configures the watchdog and sends the heartbeats.
|
||||
|
||||
The Intel iAMT watchdog MEI driver uses the kernel watchdog API to configure
|
||||
the Intel AMT Watchdog and to send heartbeats to it. The default timeout of the
|
||||
watchdog is 120 seconds.
|
||||
|
||||
If the Intel AMT is not enabled in the firmware then the watchdog client won't enumerate
|
||||
on the me client bus and watchdog devices won't be exposed.
|
||||
|
||||
---
|
||||
linux-mei@linux.intel.com
|
||||
@@ -0,0 +1,23 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
.. include:: <isonum.txt>
|
||||
|
||||
===================================================
|
||||
Intel(R) Management Engine Interface (Intel(R) MEI)
|
||||
===================================================
|
||||
|
||||
**Copyright** |copy| 2019 Intel Corporation
|
||||
|
||||
|
||||
.. only:: html
|
||||
|
||||
.. class:: toc-title
|
||||
|
||||
Table of Contents
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 3
|
||||
|
||||
mei
|
||||
mei-client-bus
|
||||
iamt
|
||||
@@ -0,0 +1,168 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
==============================================
|
||||
Intel(R) Management Engine (ME) Client bus API
|
||||
==============================================
|
||||
|
||||
|
||||
Rationale
|
||||
=========
|
||||
|
||||
The MEI character device is useful for dedicated applications to send and receive
|
||||
data to the many FW appliance found in Intel's ME from the user space.
|
||||
However, for some of the ME functionalities it makes sense to leverage existing software
|
||||
stack and expose them through existing kernel subsystems.
|
||||
|
||||
In order to plug seamlessly into the kernel device driver model we add kernel virtual
|
||||
bus abstraction on top of the MEI driver. This allows implementing Linux kernel drivers
|
||||
for the various MEI features as a stand alone entities found in their respective subsystem.
|
||||
Existing device drivers can even potentially be re-used by adding an MEI CL bus layer to
|
||||
the existing code.
|
||||
|
||||
|
||||
MEI CL bus API
|
||||
==============
|
||||
|
||||
A driver implementation for an MEI Client is very similar to any other existing bus
|
||||
based device drivers. The driver registers itself as an MEI CL bus driver through
|
||||
the ``struct mei_cl_driver`` structure defined in :file:`include/linux/mei_cl_bus.c`
|
||||
|
||||
.. code-block:: C
|
||||
|
||||
struct mei_cl_driver {
|
||||
struct device_driver driver;
|
||||
const char *name;
|
||||
|
||||
const struct mei_cl_device_id *id_table;
|
||||
|
||||
int (*probe)(struct mei_cl_device *dev, const struct mei_cl_id *id);
|
||||
int (*remove)(struct mei_cl_device *dev);
|
||||
};
|
||||
|
||||
|
||||
|
||||
The mei_cl_device_id structure defined in :file:`include/linux/mod_devicetable.h` allows a
|
||||
driver to bind itself against a device name.
|
||||
|
||||
.. code-block:: C
|
||||
|
||||
struct mei_cl_device_id {
|
||||
char name[MEI_CL_NAME_SIZE];
|
||||
uuid_le uuid;
|
||||
__u8 version;
|
||||
kernel_ulong_t driver_info;
|
||||
};
|
||||
|
||||
To actually register a driver on the ME Client bus one must call the :c:func:`mei_cl_add_driver`
|
||||
API. This is typically called at module initialization time.
|
||||
|
||||
Once the driver is registered and bound to the device, a driver will typically
|
||||
try to do some I/O on this bus and this should be done through the :c:func:`mei_cl_send`
|
||||
and :c:func:`mei_cl_recv` functions. More detailed information is in :ref:`api` section.
|
||||
|
||||
In order for a driver to be notified about pending traffic or event, the driver
|
||||
should register a callback via :c:func:`mei_cl_devev_register_rx_cb` and
|
||||
:c:func:`mei_cldev_register_notify_cb` function respectively.
|
||||
|
||||
.. _api:
|
||||
|
||||
API:
|
||||
----
|
||||
.. kernel-doc:: drivers/misc/mei/bus.c
|
||||
:export: drivers/misc/mei/bus.c
|
||||
|
||||
|
||||
|
||||
Example
|
||||
=======
|
||||
|
||||
As a theoretical example let's pretend the ME comes with a "contact" NFC IP.
|
||||
The driver init and exit routines for this device would look like:
|
||||
|
||||
.. code-block:: C
|
||||
|
||||
#define CONTACT_DRIVER_NAME "contact"
|
||||
|
||||
static struct mei_cl_device_id contact_mei_cl_tbl[] = {
|
||||
{ CONTACT_DRIVER_NAME, },
|
||||
|
||||
/* required last entry */
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(mei_cl, contact_mei_cl_tbl);
|
||||
|
||||
static struct mei_cl_driver contact_driver = {
|
||||
.id_table = contact_mei_tbl,
|
||||
.name = CONTACT_DRIVER_NAME,
|
||||
|
||||
.probe = contact_probe,
|
||||
.remove = contact_remove,
|
||||
};
|
||||
|
||||
static int contact_init(void)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = mei_cl_driver_register(&contact_driver);
|
||||
if (r) {
|
||||
pr_err(CONTACT_DRIVER_NAME ": driver registration failed\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit contact_exit(void)
|
||||
{
|
||||
mei_cl_driver_unregister(&contact_driver);
|
||||
}
|
||||
|
||||
module_init(contact_init);
|
||||
module_exit(contact_exit);
|
||||
|
||||
And the driver's simplified probe routine would look like that:
|
||||
|
||||
.. code-block:: C
|
||||
|
||||
int contact_probe(struct mei_cl_device *dev, struct mei_cl_device_id *id)
|
||||
{
|
||||
[...]
|
||||
mei_cldev_enable(dev);
|
||||
|
||||
mei_cldev_register_rx_cb(dev, contact_rx_cb);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
In the probe routine the driver first enable the MEI device and then registers
|
||||
an rx handler which is as close as it can get to registering a threaded IRQ handler.
|
||||
The handler implementation will typically call :c:func:`mei_cldev_recv` and then
|
||||
process received data.
|
||||
|
||||
.. code-block:: C
|
||||
|
||||
#define MAX_PAYLOAD 128
|
||||
#define HDR_SIZE 4
|
||||
static void conntact_rx_cb(struct mei_cl_device *cldev)
|
||||
{
|
||||
struct contact *c = mei_cldev_get_drvdata(cldev);
|
||||
unsigned char payload[MAX_PAYLOAD];
|
||||
ssize_t payload_sz;
|
||||
|
||||
payload_sz = mei_cldev_recv(cldev, payload, MAX_PAYLOAD)
|
||||
if (reply_size < HDR_SIZE) {
|
||||
return;
|
||||
}
|
||||
|
||||
c->process_rx(payload);
|
||||
|
||||
}
|
||||
|
||||
MEI Client Bus Drivers
|
||||
======================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
hdcp
|
||||
nfc
|
||||
@@ -0,0 +1,176 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
Introduction
|
||||
============
|
||||
|
||||
The Intel Management Engine (Intel ME) is an isolated and protected computing
|
||||
resource (Co-processor) residing inside certain Intel chipsets. The Intel ME
|
||||
provides support for computer/IT management and security features.
|
||||
The actual feature set depends on the Intel chipset SKU.
|
||||
|
||||
The Intel Management Engine Interface (Intel MEI, previously known as HECI)
|
||||
is the interface between the Host and Intel ME. This interface is exposed
|
||||
to the host as a PCI device, actually multiple PCI devices might be exposed.
|
||||
The Intel MEI Driver is in charge of the communication channel between
|
||||
a host application and the Intel ME features.
|
||||
|
||||
Each Intel ME feature, or Intel ME Client is addressed by a unique GUID and
|
||||
each client has its own protocol. The protocol is message-based with a
|
||||
header and payload up to maximal number of bytes advertised by the client,
|
||||
upon connection.
|
||||
|
||||
Intel MEI Driver
|
||||
================
|
||||
|
||||
The driver exposes a character device with device nodes /dev/meiX.
|
||||
|
||||
An application maintains communication with an Intel ME feature while
|
||||
/dev/meiX is open. The binding to a specific feature is performed by calling
|
||||
:c:macro:`MEI_CONNECT_CLIENT_IOCTL`, which passes the desired GUID.
|
||||
The number of instances of an Intel ME feature that can be opened
|
||||
at the same time depends on the Intel ME feature, but most of the
|
||||
features allow only a single instance.
|
||||
|
||||
The driver is transparent to data that are passed between firmware feature
|
||||
and host application.
|
||||
|
||||
Because some of the Intel ME features can change the system
|
||||
configuration, the driver by default allows only a privileged
|
||||
user to access it.
|
||||
|
||||
The session is terminated calling :c:func:`close(int fd)`.
|
||||
|
||||
A code snippet for an application communicating with Intel AMTHI client:
|
||||
|
||||
.. code-block:: C
|
||||
|
||||
struct mei_connect_client_data data;
|
||||
fd = open(MEI_DEVICE);
|
||||
|
||||
data.d.in_client_uuid = AMTHI_GUID;
|
||||
|
||||
ioctl(fd, IOCTL_MEI_CONNECT_CLIENT, &data);
|
||||
|
||||
printf("Ver=%d, MaxLen=%ld\n",
|
||||
data.d.in_client_uuid.protocol_version,
|
||||
data.d.in_client_uuid.max_msg_length);
|
||||
|
||||
[...]
|
||||
|
||||
write(fd, amthi_req_data, amthi_req_data_len);
|
||||
|
||||
[...]
|
||||
|
||||
read(fd, &amthi_res_data, amthi_res_data_len);
|
||||
|
||||
[...]
|
||||
close(fd);
|
||||
|
||||
|
||||
User space API
|
||||
|
||||
IOCTLs:
|
||||
=======
|
||||
|
||||
The Intel MEI Driver supports the following IOCTL commands:
|
||||
|
||||
IOCTL_MEI_CONNECT_CLIENT
|
||||
-------------------------
|
||||
Connect to firmware Feature/Client.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
Usage:
|
||||
|
||||
struct mei_connect_client_data client_data;
|
||||
|
||||
ioctl(fd, IOCTL_MEI_CONNECT_CLIENT, &client_data);
|
||||
|
||||
Inputs:
|
||||
|
||||
struct mei_connect_client_data - contain the following
|
||||
Input field:
|
||||
|
||||
in_client_uuid - GUID of the FW Feature that needs
|
||||
to connect to.
|
||||
Outputs:
|
||||
out_client_properties - Client Properties: MTU and Protocol Version.
|
||||
|
||||
Error returns:
|
||||
|
||||
ENOTTY No such client (i.e. wrong GUID) or connection is not allowed.
|
||||
EINVAL Wrong IOCTL Number
|
||||
ENODEV Device or Connection is not initialized or ready.
|
||||
ENOMEM Unable to allocate memory to client internal data.
|
||||
EFAULT Fatal Error (e.g. Unable to access user input data)
|
||||
EBUSY Connection Already Open
|
||||
|
||||
:Note:
|
||||
max_msg_length (MTU) in client properties describes the maximum
|
||||
data that can be sent or received. (e.g. if MTU=2K, can send
|
||||
requests up to bytes 2k and received responses up to 2k bytes).
|
||||
|
||||
|
||||
IOCTL_MEI_NOTIFY_SET
|
||||
---------------------
|
||||
Enable or disable event notifications.
|
||||
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
Usage:
|
||||
|
||||
uint32_t enable;
|
||||
|
||||
ioctl(fd, IOCTL_MEI_NOTIFY_SET, &enable);
|
||||
|
||||
|
||||
uint32_t enable = 1;
|
||||
or
|
||||
uint32_t enable[disable] = 0;
|
||||
|
||||
Error returns:
|
||||
|
||||
|
||||
EINVAL Wrong IOCTL Number
|
||||
ENODEV Device is not initialized or the client not connected
|
||||
ENOMEM Unable to allocate memory to client internal data.
|
||||
EFAULT Fatal Error (e.g. Unable to access user input data)
|
||||
EOPNOTSUPP if the device doesn't support the feature
|
||||
|
||||
:Note:
|
||||
The client must be connected in order to enable notification events
|
||||
|
||||
|
||||
IOCTL_MEI_NOTIFY_GET
|
||||
--------------------
|
||||
Retrieve event
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
Usage:
|
||||
uint32_t event;
|
||||
ioctl(fd, IOCTL_MEI_NOTIFY_GET, &event);
|
||||
|
||||
Outputs:
|
||||
1 - if an event is pending
|
||||
0 - if there is no even pending
|
||||
|
||||
Error returns:
|
||||
EINVAL Wrong IOCTL Number
|
||||
ENODEV Device is not initialized or the client not connected
|
||||
ENOMEM Unable to allocate memory to client internal data.
|
||||
EFAULT Fatal Error (e.g. Unable to access user input data)
|
||||
EOPNOTSUPP if the device doesn't support the feature
|
||||
|
||||
:Note:
|
||||
The client must be connected and event notification has to be enabled
|
||||
in order to receive an event
|
||||
|
||||
|
||||
|
||||
Supported Chipsets
|
||||
==================
|
||||
82X38/X48 Express and newer
|
||||
|
||||
linux-mei@linux.intel.com
|
||||
@@ -0,0 +1,28 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
MEI NFC
|
||||
-------
|
||||
|
||||
Some Intel 8 and 9 Serieses chipsets supports NFC devices connected behind
|
||||
the Intel Management Engine controller.
|
||||
MEI client bus exposes the NFC chips as NFC phy devices and enables
|
||||
binding with Microread and NXP PN544 NFC device driver from the Linux NFC
|
||||
subsystem.
|
||||
|
||||
.. kernel-render:: DOT
|
||||
:alt: MEI NFC digraph
|
||||
:caption: **MEI NFC** Stack
|
||||
|
||||
digraph NFC {
|
||||
cl_nfc -> me_cl_nfc;
|
||||
"drivers/nfc/mei_phy" -> cl_nfc [lhead=bus];
|
||||
"drivers/nfc/microread/mei" -> cl_nfc;
|
||||
"drivers/nfc/microread/mei" -> "drivers/nfc/mei_phy";
|
||||
"drivers/nfc/pn544/mei" -> cl_nfc;
|
||||
"drivers/nfc/pn544/mei" -> "drivers/nfc/mei_phy";
|
||||
"net/nfc" -> "drivers/nfc/microread/mei";
|
||||
"net/nfc" -> "drivers/nfc/pn544/mei";
|
||||
"neard" -> "net/nfc";
|
||||
cl_nfc [label="mei/bus(nfc)"];
|
||||
me_cl_nfc [label="me fw (nfc)"];
|
||||
}
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user