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PCI: Fix typos and whitespace errors
Fix various typos and whitespace errors: s/Synopsis/Synopsys/ s/Designware/DesignWare/ s/Keystine/Keystone/ s/gpio/GPIO/ s/pcie/PCIe/ s/phy/PHY/ s/confgiruation/configuration/ No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Bjorn Helgaas
@@ -2090,7 +2090,7 @@ S: Kuala Lumpur, Malaysia
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N: Mohit Kumar
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D: ST Microelectronics SPEAr13xx PCI host bridge driver
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D: Synopsys Designware PCI host bridge driver
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D: Synopsys DesignWare PCI host bridge driver
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N: Gabor Kuti
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E: seasons@falcon.sch.bme.hu
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@@ -1,11 +1,11 @@
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* Freescale 83xx and 512x PCI bridges
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Freescale 83xx and 512x SOCs include the same pci bridge core.
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Freescale 83xx and 512x SOCs include the same PCI bridge core.
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83xx/512x specific notes:
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- reg: should contain two address length tuples
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The first is for the internal pci bridge registers
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The second is for the pci config space access registers
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The first is for the internal PCI bridge registers
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The second is for the PCI config space access registers
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Example (MPC8313ERDB)
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pci0: pci@e0008500 {
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@@ -7,21 +7,21 @@ Required properties:
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"Txs": TX slave port region
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"Cra": Control register access region
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- interrupt-parent: interrupt source phandle.
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- interrupts: specifies the interrupt source of the parent interrupt controller.
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The format of the interrupt specifier depends on the parent interrupt
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controller.
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends
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on the parent interrupt controller.
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- device_type: must be "pci"
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- #size-cells: set to <2>
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- #interrupt-cells: set to <1>
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- ranges: describes the translation of addresses for root ports and standard
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PCI regions.
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- ranges: describes the translation of addresses for root ports and
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standard PCI regions.
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- interrupt-map-mask and interrupt-map: standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers.
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Optional properties:
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- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
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controller.
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- msi-parent: Link to the hardware entity that serves as the MSI controller
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for this PCIe controller.
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- bus-range: PCI bus numbers covered
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Example
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@@ -45,5 +45,5 @@ Example
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<0 0 0 3 &pcie_0 3>,
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<0 0 0 4 &pcie_0 4>;
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ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
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};
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@@ -6,7 +6,7 @@ and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
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- reg: base addresses and lengths of the PCIe controller (DBI),
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the phy controller, and configuration address space.
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the PHY controller, and configuration address space.
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- reg-names: Must include the following entries:
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- "dbi"
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- "phy"
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@@ -1,4 +1,4 @@
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* Synopsys Designware PCIe interface
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* Synopsys DesignWare PCIe interface
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Required properties:
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- compatible: should contain "snps,dw-pcie" to identify the core.
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@@ -17,29 +17,27 @@ RC mode:
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properties to define the mapping of the PCIe interface to interrupt
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numbers.
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EP mode:
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- num-ib-windows: number of inbound address translation
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windows
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- num-ob-windows: number of outbound address translation
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windows
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- num-ib-windows: number of inbound address translation windows
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- num-ob-windows: number of outbound address translation windows
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Optional properties:
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- num-lanes: number of lanes to use (this property should be specified unless
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the link is brought already up in BIOS)
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- reset-gpio: gpio pin number of power good signal
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- reset-gpio: GPIO pin number of power good signal
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- "pcie"
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- "pcie_bus"
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RC mode:
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- num-viewport: number of view ports configured in
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hardware. If a platform does not specify it, the driver assumes 2.
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- bus-range: PCI bus numbers covered (it is recommended
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for new devicetrees to specify this property, to keep backwards
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compatibility a range of 0x00-0xff is assumed if not present)
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- num-viewport: number of view ports configured in hardware. If a platform
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does not specify it, the driver assumes 2.
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- bus-range: PCI bus numbers covered (it is recommended for new devicetrees
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to specify this property, to keep backwards compatibility a range of
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0x00-0xff is assumed if not present)
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EP mode:
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- max-functions: maximum number of functions that can be
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configured
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- max-functions: maximum number of functions that can be configured
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Example configuration:
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@@ -1,6 +1,6 @@
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* Freescale i.MX6 PCIe interface
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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@@ -1,7 +1,7 @@
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HiSilicon Hip05 and Hip06 PCIe host bridge DT description
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HiSilicon PCIe host controller is based on Designware PCI core.
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It shares common functions with PCIe Designware core driver and inherits
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HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pci.txt.
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@@ -1,8 +1,8 @@
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HiSilicon Kirin SoCs PCIe host DT description
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Kirin PCIe host controller is based on Designware PCI core.
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It shares common functions with PCIe Designware core driver
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and inherits common properties defined in
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Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/designware-pci.txt.
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Additional properties are described here:
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@@ -16,7 +16,7 @@ Required properties
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"apb": apb Ctrl register defined by Kirin;
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"phy": apb PHY register defined by Kirin;
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"config": PCIe configuration space registers.
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- reset-gpios: The gpio to generate PCIe perst assert and deassert signal.
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- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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Optional properties:
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@@ -16,7 +16,7 @@ Required properties:
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"fsl,ls1021a-pcie", "snps,dw-pcie"
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"fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
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"fsl,ls1046a-pcie"
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- reg: base addresses and lengths of the PCIe controller
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- reg: base addresses and lengths of the PCIe controller register blocks.
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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@@ -77,7 +77,7 @@ and the following optional properties:
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- marvell,pcie-lane: the physical PCIe lane number, for ports having
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multiple lanes. If this property is not found, we assume that the
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value is 0.
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- reset-gpios: optional gpio to PERST#
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- reset-gpios: optional GPIO to PERST#
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- reset-delay-us: delay in us to wait after reset de-assertion, if not
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specified will default to 100ms, as required by the PCIe specification.
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@@ -1,6 +1,6 @@
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* Marvell Armada 7K/8K PCIe interface
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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@@ -1,12 +1,12 @@
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TI Keystone PCIe interface
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Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
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It shares common functions with PCIe Designware core driver and inherit
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common properties defined in
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Keystone PCI host Controller is based on the Synopsys DesignWare PCI
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hardware version 3.65. It shares common functions with the PCIe DesignWare
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core driver and inherits common properties defined in
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Documentation/devicetree/bindings/pci/designware-pci.txt
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Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
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for the details of Designware DT bindings. Additional properties are
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for the details of DesignWare DT bindings. Additional properties are
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described here as well as properties that are not applicable.
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Required Properties:-
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@@ -52,13 +52,12 @@ pcie_intc: Interrupt controller device node for Legacy IRQ chip
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};
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Optional properties:-
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phys: phandle to Generic Keystone SerDes phy for PCI
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phy-names: name of the Generic Keystine SerDes phy for PCI
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phys: phandle to generic Keystone SerDes PHY for PCI
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phy-names: name of the generic Keystone SerDes PHY for PCI
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- If boot loader already does PCI link establishment, then phys and
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phy-names shouldn't be present.
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interrupts: platform interrupt for error interrupts.
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Designware DT Properties not applicable for Keystone PCI
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DesignWare DT Properties not applicable for Keystone PCI
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1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
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@@ -20,7 +20,7 @@
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Value type: <stringlist>
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Definition: Must include the following entries
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- "parf" Qualcomm specific registers
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- "dbi" Designware PCIe registers
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- "dbi" DesignWare PCIe registers
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- "elbi" External local bus interface registers
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- "config" PCIe configuration space
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@@ -180,7 +180,7 @@
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- <name>-gpios:
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Usage: optional
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Value type: <prop-encoded-array>
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Definition: List of phandle and gpio specifier pairs. Should contain
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Definition: List of phandle and GPIO specifier pairs. Should contain
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- "perst-gpios" PCIe endpoint reset signal line
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- "wake-gpios" PCIe endpoint wake signal line
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@@ -71,7 +71,7 @@
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- interrupt-map: standard PCI properties to define the mapping of the
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PCI interface to interrupt numbers.
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The PCI host bridge node migh have additional sub-nodes representing
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The PCI host bridge node might have additional sub-nodes representing
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the onboard PCI devices/PCI slots. Each such sub-node must have the
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following mandatory properties:
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@@ -14,7 +14,7 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: base address and length of the pcie controller registers.
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- reg: base address and length of the PCIe controller registers.
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- bus-range: PCI bus numbers covered
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@@ -25,15 +25,14 @@ compatible: "renesas,pcie-r8a7779" for the R8A7779 SoC;
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source for hardware related interrupts (e.g. link speed change).
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map: standard PCI properties
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to define the mapping of the PCIe interface to interrupt
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numbers.
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to define the mapping of the PCIe interface to interrupt numbers.
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- clocks: from common clock binding: clock specifiers for the PCIe controller
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and PCIe bus clocks.
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- clock-names: from common clock binding: should be "pcie" and "pcie_bus".
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Example:
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SoC specific DT Entry:
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SoC-specific DT Entry:
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pcie: pcie@fe000000 {
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compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
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@@ -45,7 +45,7 @@ Required properties:
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Optional Property:
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- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
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using 24MHz OSC for RC's PHY.
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- ep-gpios: contain the entry for pre-reset gpio
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- ep-gpios: contain the entry for pre-reset GPIO
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- num-lanes: number of lanes to use
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- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
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- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
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@@ -1,29 +1,29 @@
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* Samsung Exynos 5440 PCIe interface
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This PCIe host controller is based on the Synopsis Designware PCIe IP
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible: "samsung,exynos5440-pcie"
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- reg: base addresses and lengths of the pcie controller,
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the phy controller, additional register for the phy controller.
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(Registers for the phy controller are DEPRECATED.
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- reg: base addresses and lengths of the PCIe controller,
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the PHY controller, additional register for the PHY controller.
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(Registers for the PHY controller are DEPRECATED.
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Use the PHY framework.)
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- reg-names : First name should be set to "elbi".
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And use the "config" instead of getting the confgiruation address space
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And use the "config" instead of getting the configuration address space
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from "ranges".
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NOTE: When use the "config" property, reg-names must be set.
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NOTE: When using the "config" property, reg-names must be set.
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- interrupts: A list of interrupt outputs for level interrupt,
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pulse interrupt, special interrupt.
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- phys: From PHY binding. Phandle for the Generic PHY.
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- phys: From PHY binding. Phandle for the generic PHY.
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Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
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Other common properties refer to
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Documentation/devicetree/binding/pci/designware-pcie.txt
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For other common properties, refer to
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Documentation/devicetree/bindings/pci/designware-pcie.txt
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Example:
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SoC specific DT Entry:
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SoC-specific DT Entry:
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pcie@290000 {
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compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
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@@ -83,7 +83,7 @@ With using PHY framework:
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...
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};
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Board specific DT Entry:
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Board-specific DT Entry:
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pcie@290000 {
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reset-gpio = <&pin_ctrl 5 0>;
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@@ -1,12 +1,12 @@
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SPEAr13XX PCIe DT detail:
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================================
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SPEAr13XX uses synopsis designware PCIe controller and ST MiPHY as phy
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SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
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controller.
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Required properties:
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- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
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- phys : phandle to phy node associated with pcie controller
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- compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
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- phys : phandle to PHY node associated with PCIe controller
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- phy-names : must be "pcie-phy"
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- All other definitions as per generic PCI bindings
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@@ -1,6 +1,6 @@
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TI PCI Controllers
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PCIe Designware Controller
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PCIe DesignWare Controller
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- compatible: Should be "ti,dra7-pcie" for RC
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Should be "ti,dra7-pcie-ep" for EP
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- phys : list of PHY specifiers (used by generic PHY framework)
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@@ -13,7 +13,7 @@ PCIe Designware Controller
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HOST MODE
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=========
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- reg : Two register ranges as listed in the reg-names property
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- reg-names : The first entry must be "ti-conf" for the TI specific registers
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- reg-names : The first entry must be "ti-conf" for the TI-specific registers
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The second entry must be "rc-dbics" for the DesignWare PCIe
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registers
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The third entry must be "config" for the PCIe configuration space
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@@ -30,7 +30,7 @@ HOST MODE
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DEVICE MODE
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===========
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- reg : Four register ranges as listed in the reg-names property
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- reg-names : "ti-conf" for the TI specific registers
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- reg-names : "ti-conf" for the TI-specific registers
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"ep_dbics" for the standard configuration registers as
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they are locally accessed within the DIF CS space
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"ep_dbics2" for the standard configuration registers as
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@@ -46,7 +46,7 @@ DEVICE MODE
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access.
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Optional Property:
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- gpios : Should be added if a gpio line is required to drive PERST# line
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- gpios : Should be added if a GPIO line is required to drive PERST# line
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NOTE: Two DT nodes may be added for each PCI controller; one for host
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mode and another for device mode. So in order for PCI to
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@@ -5,7 +5,7 @@ PCI host controller found on the ARM Versatile PB board's FPGA.
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Required properties:
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- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI
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controller.
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- reg: base addresses and lengths of the pci controller. There must be 3
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- reg: base addresses and lengths of the PCI controller. There must be 3
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entries:
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- Versatile-specific registers
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- Self Config space
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