mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branches 'audit', 'delay', 'fixes', 'misc' and 'sta2x11' into for-linus
This commit is contained in:
Russell King
@@ -45,6 +45,9 @@ config ARM
|
||||
select GENERIC_SMP_IDLE_THREAD
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||||
select KTIME_SCALAR
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||||
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
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||||
select GENERIC_STRNCPY_FROM_USER
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||||
select GENERIC_STRNLEN_USER
|
||||
select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
|
||||
help
|
||||
The ARM series is a line of low-power-consumption RISC chip designs
|
||||
licensed by ARM Ltd and targeted at embedded applications and
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||||
@@ -1961,6 +1964,25 @@ config ARM_ATAG_DTB_COMPAT
|
||||
bootloaders, this option allows zImage to extract the information
|
||||
from the ATAG list and store it at run time into the appended DTB.
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||||
|
||||
choice
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||||
prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
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||||
default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
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||||
|
||||
config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
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||||
bool "Use bootloader kernel arguments if available"
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||||
help
|
||||
Uses the command-line options passed by the boot loader instead of
|
||||
the device tree bootargs property. If the boot loader doesn't provide
|
||||
any, the device tree bootargs property will be used.
|
||||
|
||||
config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
|
||||
bool "Extend with bootloader kernel arguments"
|
||||
help
|
||||
The command-line arguments provided by the boot loader will be
|
||||
appended to the the device tree bootargs property.
|
||||
|
||||
endchoice
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||||
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||||
config CMDLINE
|
||||
string "Default kernel command string"
|
||||
default ""
|
||||
|
||||
@@ -369,4 +369,13 @@ config ARM_KPROBES_TEST
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||||
help
|
||||
Perform tests of kprobes API and instruction set simulation.
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||||
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||||
config PID_IN_CONTEXTIDR
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||||
bool "Write the current PID to the CONTEXTIDR register"
|
||||
depends on CPU_COPY_V6
|
||||
help
|
||||
Enabling this option causes the kernel to write the current PID to
|
||||
the PROCID field of the CONTEXTIDR register, at the expense of some
|
||||
additional instructions during context switch. Say Y here only if you
|
||||
are planning to use hardware trace tools with this kernel.
|
||||
|
||||
endmenu
|
||||
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||||
@@ -10,6 +10,9 @@
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||||
#
|
||||
# Copyright (C) 1995-2001 by Russell King
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||||
|
||||
# Ensure linker flags are correct
|
||||
LDFLAGS :=
|
||||
|
||||
LDFLAGS_vmlinux :=-p --no-undefined -X
|
||||
ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
|
||||
LDFLAGS_vmlinux += --be8
|
||||
|
||||
@@ -1,6 +1,12 @@
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||||
#include <asm/setup.h>
|
||||
#include <libfdt.h>
|
||||
|
||||
#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
|
||||
#define do_extend_cmdline 1
|
||||
#else
|
||||
#define do_extend_cmdline 0
|
||||
#endif
|
||||
|
||||
static int node_offset(void *fdt, const char *node_path)
|
||||
{
|
||||
int offset = fdt_path_offset(fdt, node_path);
|
||||
@@ -36,6 +42,48 @@ static int setprop_cell(void *fdt, const char *node_path,
|
||||
return fdt_setprop_cell(fdt, offset, property, val);
|
||||
}
|
||||
|
||||
static const void *getprop(const void *fdt, const char *node_path,
|
||||
const char *property, int *len)
|
||||
{
|
||||
int offset = fdt_path_offset(fdt, node_path);
|
||||
|
||||
if (offset == -FDT_ERR_NOTFOUND)
|
||||
return NULL;
|
||||
|
||||
return fdt_getprop(fdt, offset, property, len);
|
||||
}
|
||||
|
||||
static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
|
||||
{
|
||||
char cmdline[COMMAND_LINE_SIZE];
|
||||
const char *fdt_bootargs;
|
||||
char *ptr = cmdline;
|
||||
int len = 0;
|
||||
|
||||
/* copy the fdt command line into the buffer */
|
||||
fdt_bootargs = getprop(fdt, "/chosen", "bootargs", &len);
|
||||
if (fdt_bootargs)
|
||||
if (len < COMMAND_LINE_SIZE) {
|
||||
memcpy(ptr, fdt_bootargs, len);
|
||||
/* len is the length of the string
|
||||
* including the NULL terminator */
|
||||
ptr += len - 1;
|
||||
}
|
||||
|
||||
/* and append the ATAG_CMDLINE */
|
||||
if (fdt_cmdline) {
|
||||
len = strlen(fdt_cmdline);
|
||||
if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
|
||||
*ptr++ = ' ';
|
||||
memcpy(ptr, fdt_cmdline, len);
|
||||
ptr += len;
|
||||
}
|
||||
}
|
||||
*ptr = '\0';
|
||||
|
||||
setprop_string(fdt, "/chosen", "bootargs", cmdline);
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert and fold provided ATAGs into the provided FDT.
|
||||
*
|
||||
@@ -72,8 +120,18 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
|
||||
|
||||
for_each_tag(atag, atag_list) {
|
||||
if (atag->hdr.tag == ATAG_CMDLINE) {
|
||||
setprop_string(fdt, "/chosen", "bootargs",
|
||||
atag->u.cmdline.cmdline);
|
||||
/* Append the ATAGS command line to the device tree
|
||||
* command line.
|
||||
* NB: This means that if the same parameter is set in
|
||||
* the device tree and in the tags, the one from the
|
||||
* tags will be chosen.
|
||||
*/
|
||||
if (do_extend_cmdline)
|
||||
merge_fdt_bootargs(fdt,
|
||||
atag->u.cmdline.cmdline);
|
||||
else
|
||||
setprop_string(fdt, "/chosen", "bootargs",
|
||||
atag->u.cmdline.cmdline);
|
||||
} else if (atag->hdr.tag == ATAG_MEM) {
|
||||
if (memcount >= sizeof(mem_reg_property)/4)
|
||||
continue;
|
||||
|
||||
@@ -1,7 +1,10 @@
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||||
#ifndef __ASMARM_ARCH_TIMER_H
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||||
#define __ASMARM_ARCH_TIMER_H
|
||||
|
||||
#include <asm/errno.h>
|
||||
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER
|
||||
#define ARCH_HAS_READ_CURRENT_TIMER
|
||||
int arch_timer_of_register(void);
|
||||
int arch_timer_sched_clock_init(void);
|
||||
#else
|
||||
|
||||
@@ -6,9 +6,22 @@
|
||||
#ifndef __ASM_ARM_DELAY_H
|
||||
#define __ASM_ARM_DELAY_H
|
||||
|
||||
#include <asm/memory.h>
|
||||
#include <asm/param.h> /* HZ */
|
||||
|
||||
extern void __delay(int loops);
|
||||
#define MAX_UDELAY_MS 2
|
||||
#define UDELAY_MULT ((UL(2199023) * HZ) >> 11)
|
||||
#define UDELAY_SHIFT 30
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
extern struct arm_delay_ops {
|
||||
void (*delay)(unsigned long);
|
||||
void (*const_udelay)(unsigned long);
|
||||
void (*udelay)(unsigned long);
|
||||
} arm_delay_ops;
|
||||
|
||||
#define __delay(n) arm_delay_ops.delay(n)
|
||||
|
||||
/*
|
||||
* This function intentionally does not exist; if you see references to
|
||||
@@ -23,22 +36,27 @@ extern void __bad_udelay(void);
|
||||
* division by multiplication: you don't have to worry about
|
||||
* loss of precision.
|
||||
*
|
||||
* Use only for very small delays ( < 1 msec). Should probably use a
|
||||
* Use only for very small delays ( < 2 msec). Should probably use a
|
||||
* lookup table, really, as the multiplications take much too long with
|
||||
* short delays. This is a "reasonable" implementation, though (and the
|
||||
* first constant multiplications gets optimized away if the delay is
|
||||
* a constant)
|
||||
*/
|
||||
extern void __udelay(unsigned long usecs);
|
||||
extern void __const_udelay(unsigned long);
|
||||
|
||||
#define MAX_UDELAY_MS 2
|
||||
#define __udelay(n) arm_delay_ops.udelay(n)
|
||||
#define __const_udelay(n) arm_delay_ops.const_udelay(n)
|
||||
|
||||
#define udelay(n) \
|
||||
(__builtin_constant_p(n) ? \
|
||||
((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \
|
||||
__const_udelay((n) * ((2199023U*HZ)>>11))) : \
|
||||
__const_udelay((n) * UDELAY_MULT)) : \
|
||||
__udelay(n))
|
||||
|
||||
/* Loop-based definitions for assembly code. */
|
||||
extern void __loop_delay(unsigned long loops);
|
||||
extern void __loop_udelay(unsigned long usecs);
|
||||
extern void __loop_const_udelay(unsigned long);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* defined(_ARM_DELAY_H) */
|
||||
|
||||
|
||||
@@ -1,274 +0,0 @@
|
||||
/*
|
||||
* arch/arm/include/asm/locks.h
|
||||
*
|
||||
* Copyright (C) 2000 Russell King
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Interrupt safe locking assembler.
|
||||
*/
|
||||
#ifndef __ASM_PROC_LOCKS_H
|
||||
#define __ASM_PROC_LOCKS_H
|
||||
|
||||
#if __LINUX_ARM_ARCH__ >= 6
|
||||
|
||||
#define __down_op(ptr,fail) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"@ down_op\n" \
|
||||
"1: ldrex lr, [%0]\n" \
|
||||
" sub lr, lr, %1\n" \
|
||||
" strex ip, lr, [%0]\n" \
|
||||
" teq ip, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" teq lr, #0\n" \
|
||||
" movmi ip, %0\n" \
|
||||
" blmi " #fail \
|
||||
: \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
smp_mb(); \
|
||||
})
|
||||
|
||||
#define __down_op_ret(ptr,fail) \
|
||||
({ \
|
||||
unsigned int ret; \
|
||||
__asm__ __volatile__( \
|
||||
"@ down_op_ret\n" \
|
||||
"1: ldrex lr, [%1]\n" \
|
||||
" sub lr, lr, %2\n" \
|
||||
" strex ip, lr, [%1]\n" \
|
||||
" teq ip, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" teq lr, #0\n" \
|
||||
" movmi ip, %1\n" \
|
||||
" movpl ip, #0\n" \
|
||||
" blmi " #fail "\n" \
|
||||
" mov %0, ip" \
|
||||
: "=&r" (ret) \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
smp_mb(); \
|
||||
ret; \
|
||||
})
|
||||
|
||||
#define __up_op(ptr,wake) \
|
||||
({ \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"@ up_op\n" \
|
||||
"1: ldrex lr, [%0]\n" \
|
||||
" add lr, lr, %1\n" \
|
||||
" strex ip, lr, [%0]\n" \
|
||||
" teq ip, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" cmp lr, #0\n" \
|
||||
" movle ip, %0\n" \
|
||||
" blle " #wake \
|
||||
: \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* The value 0x01000000 supports up to 128 processors and
|
||||
* lots of processes. BIAS must be chosen such that sub'ing
|
||||
* BIAS once per CPU will result in the long remaining
|
||||
* negative.
|
||||
*/
|
||||
#define RW_LOCK_BIAS 0x01000000
|
||||
#define RW_LOCK_BIAS_STR "0x01000000"
|
||||
|
||||
#define __down_op_write(ptr,fail) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"@ down_op_write\n" \
|
||||
"1: ldrex lr, [%0]\n" \
|
||||
" sub lr, lr, %1\n" \
|
||||
" strex ip, lr, [%0]\n" \
|
||||
" teq ip, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" teq lr, #0\n" \
|
||||
" movne ip, %0\n" \
|
||||
" blne " #fail \
|
||||
: \
|
||||
: "r" (ptr), "I" (RW_LOCK_BIAS) \
|
||||
: "ip", "lr", "cc"); \
|
||||
smp_mb(); \
|
||||
})
|
||||
|
||||
#define __up_op_write(ptr,wake) \
|
||||
({ \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"@ up_op_write\n" \
|
||||
"1: ldrex lr, [%0]\n" \
|
||||
" adds lr, lr, %1\n" \
|
||||
" strex ip, lr, [%0]\n" \
|
||||
" teq ip, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" movcs ip, %0\n" \
|
||||
" blcs " #wake \
|
||||
: \
|
||||
: "r" (ptr), "I" (RW_LOCK_BIAS) \
|
||||
: "ip", "lr", "cc"); \
|
||||
})
|
||||
|
||||
#define __down_op_read(ptr,fail) \
|
||||
__down_op(ptr, fail)
|
||||
|
||||
#define __up_op_read(ptr,wake) \
|
||||
({ \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"@ up_op_read\n" \
|
||||
"1: ldrex lr, [%0]\n" \
|
||||
" add lr, lr, %1\n" \
|
||||
" strex ip, lr, [%0]\n" \
|
||||
" teq ip, #0\n" \
|
||||
" bne 1b\n" \
|
||||
" teq lr, #0\n" \
|
||||
" moveq ip, %0\n" \
|
||||
" bleq " #wake \
|
||||
: \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
})
|
||||
|
||||
#else
|
||||
|
||||
#define __down_op(ptr,fail) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"@ down_op\n" \
|
||||
" mrs ip, cpsr\n" \
|
||||
" orr lr, ip, #128\n" \
|
||||
" msr cpsr_c, lr\n" \
|
||||
" ldr lr, [%0]\n" \
|
||||
" subs lr, lr, %1\n" \
|
||||
" str lr, [%0]\n" \
|
||||
" msr cpsr_c, ip\n" \
|
||||
" movmi ip, %0\n" \
|
||||
" blmi " #fail \
|
||||
: \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
smp_mb(); \
|
||||
})
|
||||
|
||||
#define __down_op_ret(ptr,fail) \
|
||||
({ \
|
||||
unsigned int ret; \
|
||||
__asm__ __volatile__( \
|
||||
"@ down_op_ret\n" \
|
||||
" mrs ip, cpsr\n" \
|
||||
" orr lr, ip, #128\n" \
|
||||
" msr cpsr_c, lr\n" \
|
||||
" ldr lr, [%1]\n" \
|
||||
" subs lr, lr, %2\n" \
|
||||
" str lr, [%1]\n" \
|
||||
" msr cpsr_c, ip\n" \
|
||||
" movmi ip, %1\n" \
|
||||
" movpl ip, #0\n" \
|
||||
" blmi " #fail "\n" \
|
||||
" mov %0, ip" \
|
||||
: "=&r" (ret) \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
smp_mb(); \
|
||||
ret; \
|
||||
})
|
||||
|
||||
#define __up_op(ptr,wake) \
|
||||
({ \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"@ up_op\n" \
|
||||
" mrs ip, cpsr\n" \
|
||||
" orr lr, ip, #128\n" \
|
||||
" msr cpsr_c, lr\n" \
|
||||
" ldr lr, [%0]\n" \
|
||||
" adds lr, lr, %1\n" \
|
||||
" str lr, [%0]\n" \
|
||||
" msr cpsr_c, ip\n" \
|
||||
" movle ip, %0\n" \
|
||||
" blle " #wake \
|
||||
: \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* The value 0x01000000 supports up to 128 processors and
|
||||
* lots of processes. BIAS must be chosen such that sub'ing
|
||||
* BIAS once per CPU will result in the long remaining
|
||||
* negative.
|
||||
*/
|
||||
#define RW_LOCK_BIAS 0x01000000
|
||||
#define RW_LOCK_BIAS_STR "0x01000000"
|
||||
|
||||
#define __down_op_write(ptr,fail) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"@ down_op_write\n" \
|
||||
" mrs ip, cpsr\n" \
|
||||
" orr lr, ip, #128\n" \
|
||||
" msr cpsr_c, lr\n" \
|
||||
" ldr lr, [%0]\n" \
|
||||
" subs lr, lr, %1\n" \
|
||||
" str lr, [%0]\n" \
|
||||
" msr cpsr_c, ip\n" \
|
||||
" movne ip, %0\n" \
|
||||
" blne " #fail \
|
||||
: \
|
||||
: "r" (ptr), "I" (RW_LOCK_BIAS) \
|
||||
: "ip", "lr", "cc"); \
|
||||
smp_mb(); \
|
||||
})
|
||||
|
||||
#define __up_op_write(ptr,wake) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"@ up_op_write\n" \
|
||||
" mrs ip, cpsr\n" \
|
||||
" orr lr, ip, #128\n" \
|
||||
" msr cpsr_c, lr\n" \
|
||||
" ldr lr, [%0]\n" \
|
||||
" adds lr, lr, %1\n" \
|
||||
" str lr, [%0]\n" \
|
||||
" msr cpsr_c, ip\n" \
|
||||
" movcs ip, %0\n" \
|
||||
" blcs " #wake \
|
||||
: \
|
||||
: "r" (ptr), "I" (RW_LOCK_BIAS) \
|
||||
: "ip", "lr", "cc"); \
|
||||
smp_mb(); \
|
||||
})
|
||||
|
||||
#define __down_op_read(ptr,fail) \
|
||||
__down_op(ptr, fail)
|
||||
|
||||
#define __up_op_read(ptr,wake) \
|
||||
({ \
|
||||
smp_mb(); \
|
||||
__asm__ __volatile__( \
|
||||
"@ up_op_read\n" \
|
||||
" mrs ip, cpsr\n" \
|
||||
" orr lr, ip, #128\n" \
|
||||
" msr cpsr_c, lr\n" \
|
||||
" ldr lr, [%0]\n" \
|
||||
" adds lr, lr, %1\n" \
|
||||
" str lr, [%0]\n" \
|
||||
" msr cpsr_c, ip\n" \
|
||||
" moveq ip, %0\n" \
|
||||
" bleq " #wake \
|
||||
: \
|
||||
: "r" (ptr), "I" (1) \
|
||||
: "ip", "lr", "cc"); \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -16,7 +16,7 @@
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/const.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
#ifdef CONFIG_NEED_MACH_MEMORY_H
|
||||
#include <mach/memory.h>
|
||||
|
||||
@@ -12,21 +12,6 @@
|
||||
#ifndef __ARM_PERF_EVENT_H__
|
||||
#define __ARM_PERF_EVENT_H__
|
||||
|
||||
/* ARM perf PMU IDs for use by internal perf clients. */
|
||||
enum arm_perf_pmu_ids {
|
||||
ARM_PERF_PMU_ID_XSCALE1 = 0,
|
||||
ARM_PERF_PMU_ID_XSCALE2,
|
||||
ARM_PERF_PMU_ID_V6,
|
||||
ARM_PERF_PMU_ID_V6MP,
|
||||
ARM_PERF_PMU_ID_CA8,
|
||||
ARM_PERF_PMU_ID_CA9,
|
||||
ARM_PERF_PMU_ID_CA5,
|
||||
ARM_PERF_PMU_ID_CA15,
|
||||
ARM_PERF_PMU_ID_CA7,
|
||||
ARM_NUM_PMU_IDS,
|
||||
};
|
||||
|
||||
extern enum arm_perf_pmu_ids
|
||||
armpmu_get_pmu_id(void);
|
||||
/* Nothing to see here... */
|
||||
|
||||
#endif /* __ARM_PERF_EVENT_H__ */
|
||||
|
||||
@@ -103,10 +103,9 @@ struct pmu_hw_events {
|
||||
|
||||
struct arm_pmu {
|
||||
struct pmu pmu;
|
||||
enum arm_perf_pmu_ids id;
|
||||
enum arm_pmu_type type;
|
||||
cpumask_t active_irqs;
|
||||
const char *name;
|
||||
char *name;
|
||||
irqreturn_t (*handle_irq)(int irq_num, void *dev);
|
||||
void (*enable)(struct hw_perf_event *evt, int idx);
|
||||
void (*disable)(struct hw_perf_event *evt, int idx);
|
||||
|
||||
@@ -59,18 +59,13 @@ static inline void dsb_sev(void)
|
||||
}
|
||||
|
||||
/*
|
||||
* ARMv6 Spin-locking.
|
||||
* ARMv6 ticket-based spin-locking.
|
||||
*
|
||||
* We exclusively read the old value. If it is zero, we may have
|
||||
* won the lock, so we try exclusively storing it. A memory barrier
|
||||
* is required after we get a lock, and before we release it, because
|
||||
* V6 CPUs are assumed to have weakly ordered memory.
|
||||
*
|
||||
* Unlocked value: 0
|
||||
* Locked value: 1
|
||||
* A memory barrier is required after we get a lock, and before we
|
||||
* release it, because V6 CPUs are assumed to have weakly ordered
|
||||
* memory.
|
||||
*/
|
||||
|
||||
#define arch_spin_is_locked(x) ((x)->lock != 0)
|
||||
#define arch_spin_unlock_wait(lock) \
|
||||
do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
|
||||
|
||||
@@ -79,31 +74,39 @@ static inline void dsb_sev(void)
|
||||
static inline void arch_spin_lock(arch_spinlock_t *lock)
|
||||
{
|
||||
unsigned long tmp;
|
||||
u32 newval;
|
||||
arch_spinlock_t lockval;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldrex %0, [%1]\n"
|
||||
" teq %0, #0\n"
|
||||
WFE("ne")
|
||||
" strexeq %0, %2, [%1]\n"
|
||||
" teqeq %0, #0\n"
|
||||
"1: ldrex %0, [%3]\n"
|
||||
" add %1, %0, %4\n"
|
||||
" strex %2, %1, [%3]\n"
|
||||
" teq %2, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (tmp)
|
||||
: "r" (&lock->lock), "r" (1)
|
||||
: "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
|
||||
: "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
|
||||
: "cc");
|
||||
|
||||
while (lockval.tickets.next != lockval.tickets.owner) {
|
||||
wfe();
|
||||
lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
|
||||
}
|
||||
|
||||
smp_mb();
|
||||
}
|
||||
|
||||
static inline int arch_spin_trylock(arch_spinlock_t *lock)
|
||||
{
|
||||
unsigned long tmp;
|
||||
u32 slock;
|
||||
|
||||
__asm__ __volatile__(
|
||||
" ldrex %0, [%1]\n"
|
||||
" teq %0, #0\n"
|
||||
" strexeq %0, %2, [%1]"
|
||||
: "=&r" (tmp)
|
||||
: "r" (&lock->lock), "r" (1)
|
||||
" ldrex %0, [%2]\n"
|
||||
" subs %1, %0, %0, ror #16\n"
|
||||
" addeq %0, %0, %3\n"
|
||||
" strexeq %1, %0, [%2]"
|
||||
: "=&r" (slock), "=&r" (tmp)
|
||||
: "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
|
||||
: "cc");
|
||||
|
||||
if (tmp == 0) {
|
||||
@@ -116,17 +119,38 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
|
||||
|
||||
static inline void arch_spin_unlock(arch_spinlock_t *lock)
|
||||
{
|
||||
unsigned long tmp;
|
||||
u32 slock;
|
||||
|
||||
smp_mb();
|
||||
|
||||
__asm__ __volatile__(
|
||||
" str %1, [%0]\n"
|
||||
:
|
||||
: "r" (&lock->lock), "r" (0)
|
||||
" mov %1, #1\n"
|
||||
"1: ldrex %0, [%2]\n"
|
||||
" uadd16 %0, %0, %1\n"
|
||||
" strex %1, %0, [%2]\n"
|
||||
" teq %1, #0\n"
|
||||
" bne 1b"
|
||||
: "=&r" (slock), "=&r" (tmp)
|
||||
: "r" (&lock->slock)
|
||||
: "cc");
|
||||
|
||||
dsb_sev();
|
||||
}
|
||||
|
||||
static inline int arch_spin_is_locked(arch_spinlock_t *lock)
|
||||
{
|
||||
struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
|
||||
return tickets.owner != tickets.next;
|
||||
}
|
||||
|
||||
static inline int arch_spin_is_contended(arch_spinlock_t *lock)
|
||||
{
|
||||
struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
|
||||
return (tickets.next - tickets.owner) > 1;
|
||||
}
|
||||
#define arch_spin_is_contended arch_spin_is_contended
|
||||
|
||||
/*
|
||||
* RWLOCKS
|
||||
*
|
||||
@@ -158,7 +182,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
|
||||
unsigned long tmp;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldrex %0, [%1]\n"
|
||||
" ldrex %0, [%1]\n"
|
||||
" teq %0, #0\n"
|
||||
" strexeq %0, %2, [%1]"
|
||||
: "=&r" (tmp)
|
||||
@@ -244,7 +268,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
|
||||
unsigned long tmp, tmp2 = 1;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"1: ldrex %0, [%2]\n"
|
||||
" ldrex %0, [%2]\n"
|
||||
" adds %0, %0, #1\n"
|
||||
" strexpl %1, %0, [%2]\n"
|
||||
: "=&r" (tmp), "+r" (tmp2)
|
||||
|
||||
@@ -5,11 +5,24 @@
|
||||
# error "please don't include this file directly"
|
||||
#endif
|
||||
|
||||
#define TICKET_SHIFT 16
|
||||
|
||||
typedef struct {
|
||||
volatile unsigned int lock;
|
||||
union {
|
||||
u32 slock;
|
||||
struct __raw_tickets {
|
||||
#ifdef __ARMEB__
|
||||
u16 next;
|
||||
u16 owner;
|
||||
#else
|
||||
u16 owner;
|
||||
u16 next;
|
||||
#endif
|
||||
} tickets;
|
||||
};
|
||||
} arch_spinlock_t;
|
||||
|
||||
#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
|
||||
#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } }
|
||||
|
||||
typedef struct {
|
||||
volatile unsigned int lock;
|
||||
|
||||
@@ -12,13 +12,15 @@
|
||||
#ifndef _ASMARM_TIMEX_H
|
||||
#define _ASMARM_TIMEX_H
|
||||
|
||||
#include <asm/arch_timer.h>
|
||||
#include <mach/timex.h>
|
||||
|
||||
typedef unsigned long cycles_t;
|
||||
|
||||
static inline cycles_t get_cycles (void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#ifdef ARCH_HAS_READ_CURRENT_TIMER
|
||||
#define get_cycles() ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
|
||||
#else
|
||||
#define get_cycles() (0)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -189,6 +189,9 @@ static inline void set_fs(mm_segment_t fs)
|
||||
|
||||
#define access_ok(type,addr,size) (__range_ok(addr,size) == 0)
|
||||
|
||||
#define user_addr_max() \
|
||||
(segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL)
|
||||
|
||||
/*
|
||||
* The "__xxx" versions of the user access functions do not verify the
|
||||
* address space - it must have been done previously with a separate
|
||||
@@ -398,9 +401,6 @@ extern unsigned long __must_check __clear_user_std(void __user *addr, unsigned l
|
||||
#define __clear_user(addr,n) (memset((void __force *)addr, 0, n), 0)
|
||||
#endif
|
||||
|
||||
extern unsigned long __must_check __strncpy_from_user(char *to, const char __user *from, unsigned long count);
|
||||
extern unsigned long __must_check __strnlen_user(const char __user *s, long n);
|
||||
|
||||
static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
|
||||
{
|
||||
if (access_ok(VERIFY_READ, from, n))
|
||||
@@ -427,24 +427,9 @@ static inline unsigned long __must_check clear_user(void __user *to, unsigned lo
|
||||
return n;
|
||||
}
|
||||
|
||||
static inline long __must_check strncpy_from_user(char *dst, const char __user *src, long count)
|
||||
{
|
||||
long res = -EFAULT;
|
||||
if (access_ok(VERIFY_READ, src, 1))
|
||||
res = __strncpy_from_user(dst, src, count);
|
||||
return res;
|
||||
}
|
||||
extern long strncpy_from_user(char *dest, const char __user *src, long count);
|
||||
|
||||
#define strlen_user(s) strnlen_user(s, ~0UL >> 1)
|
||||
|
||||
static inline long __must_check strnlen_user(const char __user *s, long n)
|
||||
{
|
||||
unsigned long res = 0;
|
||||
|
||||
if (__addr_ok(s))
|
||||
res = __strnlen_user(s, n);
|
||||
|
||||
return res;
|
||||
}
|
||||
extern __must_check long strlen_user(const char __user *str);
|
||||
extern __must_check long strnlen_user(const char __user *str, long n);
|
||||
|
||||
#endif /* _ASMARM_UACCESS_H */
|
||||
|
||||
@@ -0,0 +1,96 @@
|
||||
#ifndef __ASM_ARM_WORD_AT_A_TIME_H
|
||||
#define __ASM_ARM_WORD_AT_A_TIME_H
|
||||
|
||||
#ifndef __ARMEB__
|
||||
|
||||
/*
|
||||
* Little-endian word-at-a-time zero byte handling.
|
||||
* Heavily based on the x86 algorithm.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
||||
struct word_at_a_time {
|
||||
const unsigned long one_bits, high_bits;
|
||||
};
|
||||
|
||||
#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) }
|
||||
|
||||
static inline unsigned long has_zero(unsigned long a, unsigned long *bits,
|
||||
const struct word_at_a_time *c)
|
||||
{
|
||||
unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits;
|
||||
*bits = mask;
|
||||
return mask;
|
||||
}
|
||||
|
||||
#define prep_zero_mask(a, bits, c) (bits)
|
||||
|
||||
static inline unsigned long create_zero_mask(unsigned long bits)
|
||||
{
|
||||
bits = (bits - 1) & ~bits;
|
||||
return bits >> 7;
|
||||
}
|
||||
|
||||
static inline unsigned long find_zero(unsigned long mask)
|
||||
{
|
||||
unsigned long ret;
|
||||
|
||||
#if __LINUX_ARM_ARCH__ >= 5
|
||||
/* We have clz available. */
|
||||
ret = fls(mask) >> 3;
|
||||
#else
|
||||
/* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */
|
||||
ret = (0x0ff0001 + mask) >> 23;
|
||||
/* Fix the 1 for 00 case */
|
||||
ret &= mask;
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DCACHE_WORD_ACCESS
|
||||
|
||||
#define zero_bytemask(mask) (mask)
|
||||
|
||||
/*
|
||||
* Load an unaligned word from kernel space.
|
||||
*
|
||||
* In the (very unlikely) case of the word being a page-crosser
|
||||
* and the next page not being mapped, take the exception and
|
||||
* return zeroes in the non-existing part.
|
||||
*/
|
||||
static inline unsigned long load_unaligned_zeropad(const void *addr)
|
||||
{
|
||||
unsigned long ret, offset;
|
||||
|
||||
/* Load word from unaligned pointer addr */
|
||||
asm(
|
||||
"1: ldr %0, [%2]\n"
|
||||
"2:\n"
|
||||
" .pushsection .fixup,\"ax\"\n"
|
||||
" .align 2\n"
|
||||
"3: and %1, %2, #0x3\n"
|
||||
" bic %2, %2, #0x3\n"
|
||||
" ldr %0, [%2]\n"
|
||||
" lsl %1, %1, #0x3\n"
|
||||
" lsr %0, %0, %1\n"
|
||||
" b 2b\n"
|
||||
" .popsection\n"
|
||||
" .pushsection __ex_table,\"a\"\n"
|
||||
" .align 3\n"
|
||||
" .long 1b, 3b\n"
|
||||
" .popsection"
|
||||
: "=&r" (ret), "=&r" (offset)
|
||||
: "r" (addr), "Qo" (*(unsigned long *)addr));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
#endif /* DCACHE_WORD_ACCESS */
|
||||
|
||||
#else /* __ARMEB__ */
|
||||
#include <asm-generic/word-at-a-time.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARM_WORD_AT_A_TIME_H */
|
||||
@@ -32,6 +32,8 @@ static int arch_timer_ppi2;
|
||||
|
||||
static struct clock_event_device __percpu **arch_timer_evt;
|
||||
|
||||
extern void init_current_timer_delay(unsigned long freq);
|
||||
|
||||
/*
|
||||
* Architected system timer support.
|
||||
*/
|
||||
@@ -137,7 +139,7 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
|
||||
/* Be safe... */
|
||||
arch_timer_disable();
|
||||
|
||||
clk->features = CLOCK_EVT_FEAT_ONESHOT;
|
||||
clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
|
||||
clk->name = "arch_sys_timer";
|
||||
clk->rating = 450;
|
||||
clk->set_mode = arch_timer_set_mode;
|
||||
@@ -223,6 +225,14 @@ static cycle_t arch_counter_read(struct clocksource *cs)
|
||||
return arch_counter_get_cntpct();
|
||||
}
|
||||
|
||||
int read_current_timer(unsigned long *timer_val)
|
||||
{
|
||||
if (!arch_timer_rate)
|
||||
return -ENXIO;
|
||||
*timer_val = arch_counter_get_cntpct();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_counter = {
|
||||
.name = "arch_sys_counter",
|
||||
.rating = 400,
|
||||
@@ -296,6 +306,7 @@ static int __init arch_timer_register(void)
|
||||
if (err)
|
||||
goto out_free_irq;
|
||||
|
||||
init_current_timer_delay(arch_timer_rate);
|
||||
return 0;
|
||||
|
||||
out_free_irq:
|
||||
|
||||
@@ -49,8 +49,7 @@ extern void __aeabi_ulcmp(void);
|
||||
extern void fpundefinstr(void);
|
||||
|
||||
/* platform dependent support */
|
||||
EXPORT_SYMBOL(__udelay);
|
||||
EXPORT_SYMBOL(__const_udelay);
|
||||
EXPORT_SYMBOL(arm_delay_ops);
|
||||
|
||||
/* networking */
|
||||
EXPORT_SYMBOL(csum_partial);
|
||||
@@ -87,10 +86,6 @@ EXPORT_SYMBOL(memmove);
|
||||
EXPORT_SYMBOL(memchr);
|
||||
EXPORT_SYMBOL(__memzero);
|
||||
|
||||
/* user mem (segment) */
|
||||
EXPORT_SYMBOL(__strnlen_user);
|
||||
EXPORT_SYMBOL(__strncpy_from_user);
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
EXPORT_SYMBOL(copy_page);
|
||||
|
||||
|
||||
@@ -95,13 +95,7 @@ ENDPROC(ret_to_user)
|
||||
ENTRY(ret_from_fork)
|
||||
bl schedule_tail
|
||||
get_thread_info tsk
|
||||
ldr r1, [tsk, #TI_FLAGS] @ check for syscall tracing
|
||||
mov why, #1
|
||||
tst r1, #_TIF_SYSCALL_WORK @ are we tracing syscalls?
|
||||
beq ret_slow_syscall
|
||||
mov r1, sp
|
||||
mov r0, #1 @ trace exit [IP = 1]
|
||||
bl syscall_trace
|
||||
b ret_slow_syscall
|
||||
ENDPROC(ret_from_fork)
|
||||
|
||||
@@ -448,10 +442,9 @@ ENDPROC(vector_swi)
|
||||
* context switches, and waiting for our parent to respond.
|
||||
*/
|
||||
__sys_trace:
|
||||
mov r2, scno
|
||||
add r1, sp, #S_OFF
|
||||
mov r0, #0 @ trace entry [IP = 0]
|
||||
bl syscall_trace
|
||||
mov r1, scno
|
||||
add r0, sp, #S_OFF
|
||||
bl syscall_trace_enter
|
||||
|
||||
adr lr, BSYM(__sys_trace_return) @ return address
|
||||
mov scno, r0 @ syscall number (possibly new)
|
||||
@@ -463,10 +456,9 @@ __sys_trace:
|
||||
|
||||
__sys_trace_return:
|
||||
str r0, [sp, #S_R0 + S_OFF]! @ save returned r0
|
||||
mov r2, scno
|
||||
mov r1, sp
|
||||
mov r0, #1 @ trace exit [IP = 1]
|
||||
bl syscall_trace
|
||||
mov r1, scno
|
||||
mov r0, sp
|
||||
bl syscall_trace_exit
|
||||
b ret_slow_syscall
|
||||
|
||||
.align 5
|
||||
|
||||
+24
-37
@@ -55,14 +55,6 @@
|
||||
add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
|
||||
.endm
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
#define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
|
||||
#define KERNEL_END _edata_loc
|
||||
#else
|
||||
#define KERNEL_START KERNEL_RAM_VADDR
|
||||
#define KERNEL_END _end
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Kernel startup entry point.
|
||||
* ---------------------------
|
||||
@@ -218,51 +210,46 @@ __create_page_tables:
|
||||
blo 1b
|
||||
|
||||
/*
|
||||
* Now setup the pagetables for our kernel direct
|
||||
* mapped region.
|
||||
* Map our RAM from the start to the end of the kernel .bss section.
|
||||
*/
|
||||
add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
|
||||
ldr r6, =(_end - 1)
|
||||
orr r3, r8, r7
|
||||
add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
|
||||
1: str r3, [r0], #1 << PMD_ORDER
|
||||
add r3, r3, #1 << SECTION_SHIFT
|
||||
cmp r0, r6
|
||||
bls 1b
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
/*
|
||||
* Map the kernel image separately as it is not located in RAM.
|
||||
*/
|
||||
#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
|
||||
mov r3, pc
|
||||
mov r3, r3, lsr #SECTION_SHIFT
|
||||
orr r3, r7, r3, lsl #SECTION_SHIFT
|
||||
add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
|
||||
str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
|
||||
ldr r6, =(KERNEL_END - 1)
|
||||
add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
|
||||
str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
|
||||
ldr r6, =(_edata_loc - 1)
|
||||
add r0, r0, #1 << PMD_ORDER
|
||||
add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
|
||||
1: cmp r0, r6
|
||||
add r3, r3, #1 << SECTION_SHIFT
|
||||
strls r3, [r0], #1 << PMD_ORDER
|
||||
bls 1b
|
||||
|
||||
#ifdef CONFIG_XIP_KERNEL
|
||||
/*
|
||||
* Map some ram to cover our .data and .bss areas.
|
||||
*/
|
||||
add r3, r8, #TEXT_OFFSET
|
||||
orr r3, r3, r7
|
||||
add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
|
||||
str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
|
||||
ldr r6, =(_end - 1)
|
||||
add r0, r0, #4
|
||||
add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
|
||||
1: cmp r0, r6
|
||||
add r3, r3, #1 << 20
|
||||
strls r3, [r0], #4
|
||||
bls 1b
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Then map boot params address in r2 or the first 1MB (2MB with LPAE)
|
||||
* of ram if boot params address is not specified.
|
||||
* Then map boot params address in r2 if specified.
|
||||
*/
|
||||
mov r0, r2, lsr #SECTION_SHIFT
|
||||
movs r0, r0, lsl #SECTION_SHIFT
|
||||
moveq r0, r8
|
||||
sub r3, r0, r8
|
||||
add r3, r3, #PAGE_OFFSET
|
||||
add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
|
||||
orr r6, r7, r0
|
||||
str r6, [r3]
|
||||
subne r3, r0, r8
|
||||
addne r3, r3, #PAGE_OFFSET
|
||||
addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
|
||||
orrne r6, r7, r0
|
||||
strne r6, [r3]
|
||||
|
||||
#ifdef CONFIG_DEBUG_LL
|
||||
#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
|
||||
|
||||
@@ -47,17 +47,14 @@ static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
|
||||
/* Set at runtime when we know what CPU type we are. */
|
||||
static struct arm_pmu *cpu_pmu;
|
||||
|
||||
enum arm_perf_pmu_ids
|
||||
armpmu_get_pmu_id(void)
|
||||
const char *perf_pmu_name(void)
|
||||
{
|
||||
int id = -ENODEV;
|
||||
if (!cpu_pmu)
|
||||
return NULL;
|
||||
|
||||
if (cpu_pmu != NULL)
|
||||
id = cpu_pmu->id;
|
||||
|
||||
return id;
|
||||
return cpu_pmu->pmu.name;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
|
||||
EXPORT_SYMBOL_GPL(perf_pmu_name);
|
||||
|
||||
int perf_num_counters(void)
|
||||
{
|
||||
@@ -760,7 +757,7 @@ init_hw_perf_events(void)
|
||||
cpu_pmu->name, cpu_pmu->num_events);
|
||||
cpu_pmu_init(cpu_pmu);
|
||||
register_cpu_notifier(&pmu_cpu_notifier);
|
||||
armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
|
||||
armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
|
||||
} else {
|
||||
pr_info("no hardware support available\n");
|
||||
}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user