mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
issei: add heci hardware module
Add support for the ISSEI (Intel Silicon Security Engine Interface) HECI PCI devices. Add the necessary PCI handling routines, hardware definitions, register mappings and hardware access routines. This enables the communication via HECI PCI device advertized by BIOS. Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com> Co-developed-by: Vitaly Lubart <lubvital@gmail.com> Signed-off-by: Vitaly Lubart <lubvital@gmail.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Link: https://patch.msgid.link/20260513-issei-for-upstream-v1-4-f590038678f9@intel.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexander Usyskin
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
7bd4b9991d
commit
8bf5e84998
@@ -11,3 +11,19 @@ config INTEL_SSEI
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If selected, the /dev/isseiX device will be created.
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If in doubt, select N.
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if INTEL_SSEI
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config INTEL_SSEI_HW_HECI
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tristate "Intel Silicon Security Engine Interface Hardware"
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depends on X86 && PCI
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help
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HECI interface of communication channel between
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the host and the Silicon Security Engine.
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Implementation of ISSEI communication channel over
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the HECI hardware PCI device.
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This device is available on Intel client CPUs released in 2024
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(Lunar Lake) or later.
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endif
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@@ -9,3 +9,7 @@ issei-objs += fw_client.o
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issei-objs += host_client.o
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issei-objs += ham.o
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issei-objs += main.o
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obj-$(CONFIG_INTEL_SSEI_HW_HECI) += issei-heci.o
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issei-heci-objs := pci_heci.o
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issei-heci-objs += hw_heci.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,47 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2023-2026 Intel Corporation */
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#ifndef _ISSEI_HW_HECI_H_
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#define _ISSEI_HW_HECI_H_
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#include <linux/irqreturn.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "issei_dev.h"
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/*
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* hw_heci_cfg - issei heci device configuration
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*
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* @dma_length: DMA area length
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*/
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struct hw_heci_cfg {
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const struct issei_dma_length dma_length;
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};
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/**
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* struct issei_heci_hw - issei heci hw specific data
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*
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* @cfg: per device generation config and ops
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* @mem_addr: io memory address
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* @irq: device irq number
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* @access_lock: spinlock to protect hw access
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* @hbuf_depth: depth of hardware host/write buffer in slots
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*/
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struct issei_heci_hw {
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const struct hw_heci_cfg *cfg;
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void __iomem *mem_addr;
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int irq;
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spinlock_t access_lock;
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u8 hbuf_depth;
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};
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#define to_heci_hw(dev) ((struct issei_heci_hw *)(dev)->hw)
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const struct hw_heci_cfg *issei_heci_get_cfg(kernel_ulong_t idx);
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const struct issei_hw_ops *issei_heci_get_ops(void);
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void issei_heci_dev_init(struct issei_device *idev,
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void __iomem *mem_addr, const struct hw_heci_cfg *cfg);
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irqreturn_t issei_heci_irq_quick_handler(int irq, void *dev_id);
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#endif /* _ISSEI_HW_HECI_H_ */
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@@ -0,0 +1,35 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2023-2026 Intel Corporation */
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#ifndef _ISSEI_HW_HECI_REGS_H_
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#define _ISSEI_HW_HECI_REGS_H_
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#include <linux/bits.h>
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/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
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#define H_CB_WW 0x0
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/* H_CSR - Host Control Status register */
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#define H_CSR 0x4
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#define H_CSR_CBD GENMASK(31, 24) /* Host Circular Buffer Depth */
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#define H_CSR_CBWP GENMASK(23, 16) /* Host Circular Buffer Write Pointer */
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#define H_CSR_CBRP GENMASK(15, 8) /* Host Circular Buffer Read Pointer */
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#define H_CSR_RST BIT(4) /* Host Reset */
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#define H_CSR_RDY BIT(3) /* Host Ready */
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#define H_CSR_IG BIT(2) /* Host Interrupt Generate */
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#define H_CSR_IS BIT(1) /* Host Interrupt Status */
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#define H_CSR_IE BIT(0) /* Host Interrupt Enable */
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/* FW_CB_RW - FW Circular Buffer Read Window register (read only) */
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#define FW_CB_RW 0x8
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/* FW_CSR_HA - FW Control Status Host Access register (read only) */
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#define FW_CSR_HA 0xC
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#define FW_CSR_CBD GENMASK(31, 24) /* FW CB (Circular Buffer) Depth */
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#define FW_CSR_CBWP GENMASK(23, 16) /* FW CB Write Pointer */
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#define FW_CSR_CBRP GENMASK(15, 8) /* FW CB Read Pointer */
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#define FW_CSR_RST BIT(4) /* FW Reset */
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#define FW_CSR_RDY BIT(3) /* FW Ready */
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#define FW_CSR_IG BIT(2) /* FW Interrupt Generate */
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#define FW_CSR_IS BIT(1) /* FW Interrupt Status */
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#define FW_CSR_IE BIT(0) /* FW Interrupt Enable */
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#define CB_SLOT_SIZE sizeof(u32) /* Circular Buffer windows size */
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#endif /* _ISSEI_HW_HECI_REGS_H_ */
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@@ -0,0 +1,151 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2023-2026 Intel Corporation */
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#include <linux/device.h>
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#include <linux/dev_printk.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pm.h>
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#include "cdev.h"
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#include "hw_heci.h"
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#include "hw_heci_regs.h"
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static int issei_heci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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struct device *dev = &pdev->dev;
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const struct hw_heci_cfg *cfg;
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struct issei_device *idev;
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struct issei_heci_hw *hw;
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char __iomem *registers;
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int err;
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cfg = issei_heci_get_cfg(ent->driver_data);
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if (!cfg)
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return dev_err_probe(dev, -ENODEV, "no usable configuration.\n");
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err = pcim_enable_device(pdev);
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if (err)
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return dev_err_probe(dev, err, "failed to enable pci device.\n");
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pci_set_master(pdev);
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registers = pcim_iomap_region(pdev, 0, KBUILD_MODNAME);
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if (IS_ERR(registers))
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return dev_err_probe(dev, PTR_ERR(registers), "failed to get pci region.\n");
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err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
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if (err)
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return dev_err_probe(dev, err, "no usable DMA configuration.\n");
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idev = issei_register(sizeof(*hw), dev, &cfg->dma_length, issei_heci_get_ops());
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if (IS_ERR(idev))
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return dev_err_probe(dev, PTR_ERR(idev), "register failure.\n");
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issei_heci_dev_init(idev, registers, cfg);
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pci_set_drvdata(pdev, idev);
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err = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
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if (err < 0) {
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dev_err_probe(dev, err, "pci_alloc_irq_vectors failure.\n");
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goto deregister;
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}
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hw = to_heci_hw(idev);
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hw->irq = pci_irq_vector(pdev, 0);
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err = request_threaded_irq(hw->irq,
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issei_heci_irq_quick_handler,
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NULL,
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IRQF_SHARED, KBUILD_MODNAME, idev);
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if (err)
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goto release_irq;
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err = issei_start(idev);
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if (err) {
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dev_err_probe(dev, err, "init hw failure.\n");
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goto free_irq;
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}
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return 0;
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free_irq:
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idev->ops->irq_disable(idev);
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free_irq(hw->irq, idev);
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release_irq:
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pci_free_irq_vectors(pdev);
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deregister:
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issei_deregister(idev);
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return err;
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}
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static void issei_heci_shutdown(struct pci_dev *pdev)
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{
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struct issei_device *idev = pci_get_drvdata(pdev);
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struct issei_heci_hw *hw = to_heci_hw(idev);
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issei_stop(idev);
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idev->ops->irq_disable(idev);
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free_irq(hw->irq, idev);
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pci_free_irq_vectors(pdev);
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}
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static void issei_heci_remove(struct pci_dev *pdev)
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{
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issei_heci_shutdown(pdev);
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issei_deregister(pci_get_drvdata(pdev));
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}
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static int issei_heci_pm_suspend(struct device *device)
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{
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struct issei_device *idev = dev_get_drvdata(device);
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issei_stop(idev);
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idev->ops->irq_disable(idev);
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return 0;
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}
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static int issei_heci_pm_resume(struct device *device)
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{
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struct issei_device *idev = dev_get_drvdata(device);
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return issei_start(idev);
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}
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static const struct dev_pm_ops issei_heci_pm_ops = {
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SYSTEM_SLEEP_PM_OPS(issei_heci_pm_suspend, issei_heci_pm_resume)
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};
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static const struct pci_device_id heci_pci_tbl[] = {
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{PCI_VDEVICE(INTEL, 0xA85D)}, /* Lunar Lake M */
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{PCI_VDEVICE(INTEL, 0xE35D)}, /* Panther Lake H */
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{PCI_VDEVICE(INTEL, 0xE45D)}, /* Panther Lake P */
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{PCI_VDEVICE(INTEL, 0xD470)}, /* Nova Lake S */
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{PCI_VDEVICE(INTEL, 0xD358)}, /* Nova Lake H */
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{PCI_VDEVICE(INTEL, 0x4D5D)}, /* Wildcat Lake */
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{}
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};
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MODULE_DEVICE_TABLE(pci, heci_pci_tbl);
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static struct pci_driver issei_heci_driver = {
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.name = KBUILD_MODNAME,
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.id_table = heci_pci_tbl,
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.probe = issei_heci_probe,
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.remove = issei_heci_remove,
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.shutdown = issei_heci_shutdown,
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.driver = {
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.pm = &issei_heci_pm_ops,
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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},
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};
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module_pci_driver(issei_heci_driver);
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MODULE_DESCRIPTION("Intel(R) Silicon Security Engine Interface - HECI");
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MODULE_LICENSE("GPL");
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MODULE_IMPORT_NS("INTEL_SSEI");
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