mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'tty-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
Pull tty / serial driver updates from Greg KH: "Here is the big set of TTY and Serial driver updates for 7.2-rc1. Overall we end up removing more code than added, due to an obsolete synclink_gt driver being removed from the tree, always a nice thing to see happen. Other than that driver removal, major things included in here are: - max310x serial driver updates and fixes - 8250 driver updates and rework in places to make it more "modern" - dts file updates - serial driver core tweaks and updates - vt code cleanups - vc_screen crash fixes - other minor driver updates and cleanups All of these have been in linux-next for well over a week with no reported issues" * tag 'tty-7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty: (49 commits) serial: 8250_pci: Don't specify conflicting values to pci_device_id members vc_screen: fix null-ptr-deref in vcs_notifier() during concurrent vcs_write serial: qcom_geni: Fix RX DMA stall when SE_DMA_RX_LEN_IN is zero vt: merge ucs_is_zero_width()/ucs_is_double_width() into ucs_get_width() serial: 8250: fix possible ISR soft lockup dt-bindings: serial: rs485: remove deprecated .txt binding stub serial: qcom-geni: trace: Add tracepoint support for Qualcomm GENI serial tty: serial: Use named initializers for arrays of i2c_device_data serial: 8250_dw: remove clock-notifier infrastructure serial: 8250_dw: unregister 8250 port if clk_notifier_register() fails amba/serial: amba-pl011: Bring back zx29 UART support serial: 8250: Add support for console flow control serial: 8250: Check LSR timeout on console flow control serial: 8250: Set cons_flow on port registration tty: serial: 8250: protect against NULL uart->port.dev in register arm64: dts: add support for A9 based Amlogic BY401 dt-bindings: arm: amlogic: add A311Y3 support serial: max310x: fix compile errors if CONFIG_SPI_MASTER is disabled serial: qcom-geni: Avoid probing debug console UART without console support serial: max310x: add comments for PLL limits ...
This commit is contained in:
Linus Torvalds
@@ -234,6 +234,12 @@ properties:
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- amlogic,av400
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- const: amlogic,a5
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- description: Boards with the Amlogic A9 A311Y3 SoC
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items:
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- enum:
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- amlogic,by401
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- const: amlogic,a9
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- description: Boards with the Amlogic C3 C302X/C308L SoC
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items:
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- enum:
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@@ -14,9 +14,16 @@ allOf:
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properties:
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compatible:
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enum:
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- qcom,sa8255p-geni-uart
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- qcom,sa8255p-geni-debug-uart
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oneOf:
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- enum:
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- qcom,sa8255p-geni-uart
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- qcom,sa8255p-geni-debug-uart
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- items:
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- const: qcom,sa8797p-geni-uart
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- const: qcom,sa8255p-geni-uart
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- items:
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- const: qcom,sa8797p-geni-debug-uart
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- const: qcom,sa8255p-geni-debug-uart
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reg:
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maxItems: 1
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@@ -1 +0,0 @@
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See rs485.yaml
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@@ -78,6 +78,7 @@ properties:
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- starfive,jh7100-hsuart
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- starfive,jh7100-uart
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- starfive,jh7110-uart
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- ultrarisc,dp1000-uart
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- const: snps,dw-apb-uart
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- const: snps,dw-apb-uart
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@@ -132,4 +132,4 @@ RS485 Serial Communications
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6. References
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=============
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.. [#DT-bindings] Documentation/devicetree/bindings/serial/rs485.txt
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.. [#DT-bindings] Documentation/devicetree/bindings/serial/rs485.yaml
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@@ -270,7 +270,6 @@ Code Seq# Include File Comments
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'm' 00-09 linux/mmtimer.h conflict!
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'm' all linux/mtio.h conflict!
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'm' all linux/soundcard.h conflict!
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'm' all linux/synclink.h conflict!
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'm' 00-19 drivers/message/fusion/mptctl.h conflict!
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'm' 00 drivers/scsi/megaraid/megaraid_ioctl.h conflict!
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'n' 00-7F linux/ncp_fs.h and fs/ncpfs/ioctl.c
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@@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MESON) += amlogic-a4-a113l2-ba400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-a5-a113x2-av400.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-a9-a311y3-by401.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c308l-aw419.dtb
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dtb-$(CONFIG_ARCH_MESON) += amlogic-s6-s905x5-bl209.dtb
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@@ -0,0 +1,40 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2026 Amlogic, Inc. All rights reserved.
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*/
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/dts-v1/;
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#include "amlogic-a9.dtsi"
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/ {
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model = "Amlogic A311DY3 BY401 Development Board";
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compatible = "amlogic,by401", "amlogic,a9";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart_b;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 35 MiB reserved for ARM Trusted Firmware */
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secmon_reserved: secmon@5000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x05000000 0x0 0x2300000>;
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no-map;
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};
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};
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};
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&uart_b {
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status = "okay";
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};
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@@ -0,0 +1,128 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2026 Amlogic, Inc. All rights reserved.
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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enable-method = "psci";
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};
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cpu4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x400>;
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enable-method = "psci";
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};
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cpu5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x500>;
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enable-method = "psci";
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};
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cpu6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0 0x600>;
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enable-method = "psci";
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};
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cpu7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a78";
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reg = <0x0 0x700>;
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enable-method = "psci";
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@ff800000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xff800000 0 0x10000>,
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<0x0 0xff840000 0 0x100000>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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aobus: bus@ffa00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffa00000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffa00000 0x0 0x100000>;
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uart_b: serial@1e000 {
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compatible = "amlogic,a9-uart",
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"amlogic,meson-s4-uart";
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reg = <0x0 0x1e000 0x0 0x18>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&xtal>, <&xtal>;
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clock-names = "xtal", "pclk", "baud";
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status = "disabled";
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};
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};
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};
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};
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@@ -548,7 +548,6 @@ CONFIG_GAMEPORT_EMU10K1=m
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CONFIG_GAMEPORT_FM801=m
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_NONSTANDARD=y
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CONFIG_SYNCLINK_GT=m
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CONFIG_NOZOMI=m
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CONFIG_N_HDLC=m
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CONFIG_SERIAL_8250=y
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@@ -197,8 +197,8 @@ config PPP_SYNC_TTY
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tristate "PPP support for sync tty ports"
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help
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Say Y (or M) here if you want to be able to use PPP over synchronous
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(HDLC) tty devices, such as the SyncLink adapter. These devices
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are often used for high-speed leased lines like T1/E1.
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(HDLC) tty devices. These devices are often used for high-speed leased
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lines like T1/E1.
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To compile this driver as a module, choose M here.
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+1
-10
@@ -231,21 +231,12 @@ config MOXA_SMARTIO
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This driver can also be built as a module. The module will be called
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mxser. If you want to do that, say M here.
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config SYNCLINK_GT
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tristate "SyncLink GT/AC support"
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depends on SERIAL_NONSTANDARD && PCI
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depends on BROKEN
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help
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Support for SyncLink GT and SyncLink AC families of
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synchronous and asynchronous serial adapters
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manufactured by Microgate Systems, Ltd. (www.microgate.com)
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config N_HDLC
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tristate "HDLC line discipline support"
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depends on SERIAL_NONSTANDARD
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help
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Allows synchronous HDLC communications with tty device drivers that
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support synchronous HDLC such as the Microgate SyncLink adapter.
|
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support synchronous HDLC.
|
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This driver can be built as a module ( = code which can be
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inserted in and removed from the running kernel whenever you want).
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@@ -21,7 +21,6 @@ obj-$(CONFIG_MOXA_INTELLIO) += moxa.o
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obj-$(CONFIG_MOXA_SMARTIO) += mxser.o
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obj-$(CONFIG_NOZOMI) += nozomi.o
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obj-$(CONFIG_NULL_TTY) += ttynull.o
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obj-$(CONFIG_SYNCLINK_GT) += synclink_gt.o
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obj-$(CONFIG_PPC_EPAPR_HV_BYTECHAN) += ehv_bytechan.o
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obj-$(CONFIG_GOLDFISH_TTY) += goldfish.o
|
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obj-$(CONFIG_MIPS_EJTAG_FDC_TTY) += mips_ejtag_fdc.o
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|
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@@ -4,8 +4,6 @@
|
||||
* Written by Paul Fulghum paulkf@microgate.com
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* for Microgate Corporation
|
||||
*
|
||||
* Microgate and SyncLink are registered trademarks of Microgate Corporation
|
||||
*
|
||||
* Adapted from ppp.c, written by Michael Callahan <callahan@maths.ox.ac.uk>,
|
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* Al Longyear <longyear@netcom.com>,
|
||||
* Paul Mackerras <Paul.Mackerras@cs.anu.edu.au>
|
||||
@@ -54,11 +52,6 @@
|
||||
* this line discipline (or another line discipline that is frame
|
||||
* oriented such as N_PPP).
|
||||
*
|
||||
* The SyncLink driver (synclink.c) implements both asynchronous
|
||||
* (using standard line discipline N_TTY) and synchronous HDLC
|
||||
* (using N_HDLC) communications, with the latter using the above
|
||||
* conventions.
|
||||
*
|
||||
* This implementation is very basic and does not maintain
|
||||
* any statistics. The main point is to enforce the raw data
|
||||
* and frame orientation of HDLC communications.
|
||||
|
||||
@@ -693,6 +693,7 @@ static void serial_8250_overrun_backoff_work(struct work_struct *work)
|
||||
int serial8250_register_8250_port(const struct uart_8250_port *up)
|
||||
{
|
||||
struct uart_8250_port *uart;
|
||||
bool cons_flow;
|
||||
int ret;
|
||||
|
||||
if (up->port.uartclk == 0)
|
||||
@@ -716,6 +717,9 @@ int serial8250_register_8250_port(const struct uart_8250_port *up)
|
||||
if (uart->port.type == PORT_8250_CIR)
|
||||
return -ENODEV;
|
||||
|
||||
/* Preserve specified console flow control. */
|
||||
cons_flow = uart_cons_flow_enabled(&uart->port);
|
||||
|
||||
if (uart->port.dev)
|
||||
uart_remove_one_port(&serial8250_reg, &uart->port);
|
||||
|
||||
@@ -746,6 +750,8 @@ int serial8250_register_8250_port(const struct uart_8250_port *up)
|
||||
uart->lsr_save_mask = up->lsr_save_mask;
|
||||
uart->dma = up->dma;
|
||||
|
||||
uart_set_cons_flow_enabled(&uart->port, uart_cons_flow_enabled(&up->port) | cons_flow);
|
||||
|
||||
/* Take tx_loadsz from fifosize if it wasn't set separately */
|
||||
if (uart->port.fifosize && !uart->tx_loadsz)
|
||||
uart->tx_loadsz = uart->port.fifosize;
|
||||
@@ -764,7 +770,7 @@ int serial8250_register_8250_port(const struct uart_8250_port *up)
|
||||
* Only call mctrl_gpio_init(), if the device has no ACPI
|
||||
* companion device
|
||||
*/
|
||||
if (!has_acpi_companion(uart->port.dev)) {
|
||||
if (uart->port.dev && !has_acpi_companion(uart->port.dev)) {
|
||||
struct mctrl_gpios *gpios = mctrl_gpio_init(&uart->port, 0);
|
||||
if (IS_ERR(gpios)) {
|
||||
ret = PTR_ERR(gpios);
|
||||
|
||||
@@ -19,13 +19,11 @@
|
||||
#include <linux/lockdep.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
#include <asm/byteorder.h>
|
||||
|
||||
@@ -34,22 +32,11 @@
|
||||
|
||||
#include "8250_dwlib.h"
|
||||
|
||||
/* Offsets for the DesignWare specific registers */
|
||||
#define DW_UART_USR 0x1f /* UART Status Register */
|
||||
#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
|
||||
|
||||
#define OCTEON_UART_USR 0x27 /* UART Status Register */
|
||||
|
||||
#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
|
||||
#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
|
||||
|
||||
/* DesignWare specific register fields */
|
||||
#define DW_UART_IIR_IID GENMASK(3, 0)
|
||||
|
||||
#define DW_UART_MCR_SIRE BIT(6)
|
||||
|
||||
#define DW_UART_USR_BUSY BIT(0)
|
||||
|
||||
/* Renesas specific register fields */
|
||||
#define RZN1_UART_xDMACR_DMA_EN BIT(0)
|
||||
#define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
|
||||
@@ -86,8 +73,6 @@ struct dw8250_data {
|
||||
u32 msr_mask_off;
|
||||
struct clk *clk;
|
||||
struct clk *pclk;
|
||||
struct notifier_block clk_notifier;
|
||||
struct work_struct clk_work;
|
||||
struct reset_control *rst;
|
||||
|
||||
unsigned int skip_autocfg:1;
|
||||
@@ -102,16 +87,6 @@ static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
|
||||
return container_of(data, struct dw8250_data, data);
|
||||
}
|
||||
|
||||
static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
|
||||
{
|
||||
return container_of(nb, struct dw8250_data, clk_notifier);
|
||||
}
|
||||
|
||||
static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
|
||||
{
|
||||
return container_of(work, struct dw8250_data, clk_work);
|
||||
}
|
||||
|
||||
static inline u32 dw8250_modify_msr(struct uart_port *p, unsigned int offset, u32 value)
|
||||
{
|
||||
struct dw8250_data *d = to_dw8250_data(p->private_data);
|
||||
@@ -484,46 +459,6 @@ static int dw8250_handle_irq(struct uart_port *p)
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void dw8250_clk_work_cb(struct work_struct *work)
|
||||
{
|
||||
struct dw8250_data *d = work_to_dw8250_data(work);
|
||||
struct uart_8250_port *up;
|
||||
unsigned long rate;
|
||||
|
||||
rate = clk_get_rate(d->clk);
|
||||
if (rate <= 0)
|
||||
return;
|
||||
|
||||
up = serial8250_get_port(d->data.line);
|
||||
|
||||
serial8250_update_uartclk(&up->port, rate);
|
||||
}
|
||||
|
||||
static int dw8250_clk_notifier_cb(struct notifier_block *nb,
|
||||
unsigned long event, void *data)
|
||||
{
|
||||
struct dw8250_data *d = clk_to_dw8250_data(nb);
|
||||
|
||||
/*
|
||||
* We have no choice but to defer the uartclk update due to two
|
||||
* deadlocks. First one is caused by a recursive mutex lock which
|
||||
* happens when clk_set_rate() is called from dw8250_set_termios().
|
||||
* Second deadlock is more tricky and is caused by an inverted order of
|
||||
* the clk and tty-port mutexes lock. It happens if clock rate change
|
||||
* is requested asynchronously while set_termios() is executed between
|
||||
* tty-port mutex lock and clk_set_rate() function invocation and
|
||||
* vise-versa. Anyway if we didn't have the reference clock alteration
|
||||
* in the dw8250_set_termios() method we wouldn't have needed this
|
||||
* deferred event handling complication.
|
||||
*/
|
||||
if (event == POST_RATE_CHANGE) {
|
||||
queue_work(system_dfl_wq, &d->clk_work);
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static void
|
||||
dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
|
||||
{
|
||||
@@ -547,10 +482,6 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
|
||||
clk_disable_unprepare(d->clk);
|
||||
rate = clk_round_rate(d->clk, newrate);
|
||||
if (rate > 0) {
|
||||
/*
|
||||
* Note that any clock-notifier worker will block in
|
||||
* serial8250_update_uartclk() until we are done.
|
||||
*/
|
||||
ret = clk_set_rate(d->clk, newrate);
|
||||
if (!ret)
|
||||
p->uartclk = rate;
|
||||
@@ -783,9 +714,6 @@ static int dw8250_probe(struct platform_device *pdev)
|
||||
return dev_err_probe(dev, PTR_ERR(data->clk),
|
||||
"failed to get baudclk\n");
|
||||
|
||||
INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
|
||||
data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
|
||||
|
||||
if (data->clk)
|
||||
p->uartclk = clk_get_rate(data->clk);
|
||||
|
||||
@@ -843,18 +771,6 @@ static int dw8250_probe(struct platform_device *pdev)
|
||||
if (data->data.line < 0)
|
||||
return data->data.line;
|
||||
|
||||
/*
|
||||
* Some platforms may provide a reference clock shared between several
|
||||
* devices. In this case any clock state change must be known to the
|
||||
* UART port at least post factum.
|
||||
*/
|
||||
if (data->clk) {
|
||||
err = clk_notifier_register(data->clk, &data->clk_notifier);
|
||||
if (err)
|
||||
return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
|
||||
queue_work(system_dfl_wq, &data->clk_work);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
@@ -869,12 +785,6 @@ static void dw8250_remove(struct platform_device *pdev)
|
||||
|
||||
pm_runtime_get_sync(dev);
|
||||
|
||||
if (data->clk) {
|
||||
clk_notifier_unregister(data->clk, &data->clk_notifier);
|
||||
|
||||
flush_work(&data->clk_work);
|
||||
}
|
||||
|
||||
serial8250_unregister_port(data->data.line);
|
||||
|
||||
pm_runtime_disable(dev);
|
||||
@@ -948,7 +858,15 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
|
||||
|
||||
static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
|
||||
.usr_reg = DW_UART_USR,
|
||||
.cpr_value = 0x00012f32,
|
||||
.cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
|
||||
DW_UART_CPR_AFCE_MODE |
|
||||
DW_UART_CPR_THRE_MODE |
|
||||
DW_UART_CPR_ADDITIONAL_FEATURES |
|
||||
DW_UART_CPR_FIFO_ACCESS |
|
||||
DW_UART_CPR_FIFO_STAT |
|
||||
DW_UART_CPR_SHADOW |
|
||||
DW_UART_CPR_DMA_EXTRA |
|
||||
DW_UART_CPR_FIFO_MODE_FROM_SIZE(16),
|
||||
.quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,
|
||||
};
|
||||
|
||||
@@ -962,6 +880,15 @@ static const struct dw8250_platform_data dw8250_intc10ee = {
|
||||
.quirks = DW_UART_QUIRK_IER_KICK,
|
||||
};
|
||||
|
||||
static const struct dw8250_platform_data dw8250_ultrarisc_dp1000_data = {
|
||||
.usr_reg = DW_UART_USR,
|
||||
.cpr_value = FIELD_PREP_CONST(DW_UART_CPR_ABP_DATA_WIDTH, 2) |
|
||||
DW_UART_CPR_THRE_MODE |
|
||||
DW_UART_CPR_DMA_EXTRA |
|
||||
DW_UART_CPR_FIFO_MODE_FROM_SIZE(32),
|
||||
.quirks = DW_UART_QUIRK_CPR_VALUE,
|
||||
};
|
||||
|
||||
static const struct of_device_id dw8250_of_match[] = {
|
||||
{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
|
||||
{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
|
||||
@@ -969,6 +896,7 @@ static const struct of_device_id dw8250_of_match[] = {
|
||||
{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
|
||||
{ .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
|
||||
{ .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
|
||||
{ .compatible = "ultrarisc,dp1000-uart", .data = &dw8250_ultrarisc_dp1000_data },
|
||||
{ /* Sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, dw8250_of_match);
|
||||
|
||||
@@ -13,55 +13,6 @@
|
||||
|
||||
#include "8250_dwlib.h"
|
||||
|
||||
/* Offsets for the DesignWare specific registers */
|
||||
#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
|
||||
#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
|
||||
#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
|
||||
#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
|
||||
#define DW_UART_RAR 0xc4 /* Receive Address Register */
|
||||
#define DW_UART_TAR 0xc8 /* Transmit Address Register */
|
||||
#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
|
||||
#define DW_UART_CPR 0xf4 /* Component Parameter Register */
|
||||
#define DW_UART_UCV 0xf8 /* UART Component Version */
|
||||
|
||||
/* Receive / Transmit Address Register bits */
|
||||
#define DW_UART_ADDR_MASK GENMASK(7, 0)
|
||||
|
||||
/* Line Status Register bits */
|
||||
#define DW_UART_LSR_ADDR_RCVD BIT(8)
|
||||
|
||||
/* Transceiver Control Register bits */
|
||||
#define DW_UART_TCR_RS485_EN BIT(0)
|
||||
#define DW_UART_TCR_RE_POL BIT(1)
|
||||
#define DW_UART_TCR_DE_POL BIT(2)
|
||||
#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
|
||||
#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
|
||||
#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
|
||||
#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
|
||||
|
||||
/* Line Extended Control Register bits */
|
||||
#define DW_UART_LCR_EXT_DLS_E BIT(0)
|
||||
#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
|
||||
#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
|
||||
#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
|
||||
|
||||
/* Component Parameter Register bits */
|
||||
#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
|
||||
#define DW_UART_CPR_AFCE_MODE BIT(4)
|
||||
#define DW_UART_CPR_THRE_MODE BIT(5)
|
||||
#define DW_UART_CPR_SIR_MODE BIT(6)
|
||||
#define DW_UART_CPR_SIR_LP_MODE BIT(7)
|
||||
#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
|
||||
#define DW_UART_CPR_FIFO_ACCESS BIT(9)
|
||||
#define DW_UART_CPR_FIFO_STAT BIT(10)
|
||||
#define DW_UART_CPR_SHADOW BIT(11)
|
||||
#define DW_UART_CPR_ENCODED_PARMS BIT(12)
|
||||
#define DW_UART_CPR_DMA_EXTRA BIT(13)
|
||||
#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
|
||||
|
||||
/* Helper for FIFO size calculation */
|
||||
#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
|
||||
|
||||
/*
|
||||
* divisor = div(I) + div(F)
|
||||
* "I" means integer, "F" means fractional
|
||||
|
||||
@@ -1,11 +1,82 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/* Synopsys DesignWare 8250 library header file. */
|
||||
|
||||
#ifndef _SERIAL_8250_DWLIB_H_
|
||||
#define _SERIAL_8250_DWLIB_H_
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/build_bug.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "8250.h"
|
||||
|
||||
/* Offsets for the DesignWare specific registers */
|
||||
#define DW_UART_USR 0x1f /* UART Status Register */
|
||||
#define DW_UART_DMASA 0xa8 /* DMA Software Ack */
|
||||
#define DW_UART_TCR 0xac /* Transceiver Control Register (RS485) */
|
||||
#define DW_UART_DE_EN 0xb0 /* Driver Output Enable Register */
|
||||
#define DW_UART_RE_EN 0xb4 /* Receiver Output Enable Register */
|
||||
#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
|
||||
#define DW_UART_RAR 0xc4 /* Receive Address Register */
|
||||
#define DW_UART_TAR 0xc8 /* Transmit Address Register */
|
||||
#define DW_UART_LCR_EXT 0xcc /* Line Extended Control Register */
|
||||
#define DW_UART_CPR 0xf4 /* Component Parameter Register */
|
||||
#define DW_UART_UCV 0xf8 /* UART Component Version */
|
||||
|
||||
/* Interrupt ID Register bits */
|
||||
#define DW_UART_IIR_IID GENMASK(3, 0)
|
||||
|
||||
/* Modem Control Register bits */
|
||||
#define DW_UART_MCR_SIRE BIT(6)
|
||||
|
||||
/* Line Status Register bits */
|
||||
#define DW_UART_LSR_ADDR_RCVD BIT(8)
|
||||
|
||||
/* UART Status Register bits */
|
||||
#define DW_UART_USR_BUSY BIT(0)
|
||||
|
||||
/* Transceiver Control Register bits */
|
||||
#define DW_UART_TCR_RS485_EN BIT(0)
|
||||
#define DW_UART_TCR_RE_POL BIT(1)
|
||||
#define DW_UART_TCR_DE_POL BIT(2)
|
||||
#define DW_UART_TCR_XFER_MODE GENMASK(4, 3)
|
||||
#define DW_UART_TCR_XFER_MODE_DE_DURING_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 0)
|
||||
#define DW_UART_TCR_XFER_MODE_SW_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 1)
|
||||
#define DW_UART_TCR_XFER_MODE_DE_OR_RE FIELD_PREP(DW_UART_TCR_XFER_MODE, 2)
|
||||
|
||||
/* Receive / Transmit Address Register bits */
|
||||
#define DW_UART_ADDR_MASK GENMASK(7, 0)
|
||||
|
||||
/* Line Extended Control Register bits */
|
||||
#define DW_UART_LCR_EXT_DLS_E BIT(0)
|
||||
#define DW_UART_LCR_EXT_ADDR_MATCH BIT(1)
|
||||
#define DW_UART_LCR_EXT_SEND_ADDR BIT(2)
|
||||
#define DW_UART_LCR_EXT_TRANSMIT_MODE BIT(3)
|
||||
|
||||
/* Component Parameter Register bits */
|
||||
#define DW_UART_CPR_ABP_DATA_WIDTH GENMASK(1, 0)
|
||||
#define DW_UART_CPR_AFCE_MODE BIT(4)
|
||||
#define DW_UART_CPR_THRE_MODE BIT(5)
|
||||
#define DW_UART_CPR_SIR_MODE BIT(6)
|
||||
#define DW_UART_CPR_SIR_LP_MODE BIT(7)
|
||||
#define DW_UART_CPR_ADDITIONAL_FEATURES BIT(8)
|
||||
#define DW_UART_CPR_FIFO_ACCESS BIT(9)
|
||||
#define DW_UART_CPR_FIFO_STAT BIT(10)
|
||||
#define DW_UART_CPR_SHADOW BIT(11)
|
||||
#define DW_UART_CPR_ENCODED_PARMS BIT(12)
|
||||
#define DW_UART_CPR_DMA_EXTRA BIT(13)
|
||||
#define DW_UART_CPR_FIFO_MODE GENMASK(23, 16)
|
||||
|
||||
/* Helpers for FIFO size calculation */
|
||||
#define DW_UART_CPR_FIFO_SIZE(a) (FIELD_GET(DW_UART_CPR_FIFO_MODE, (a)) * 16)
|
||||
#define DW_UART_CPR_FIFO_MODE_FROM_SIZE(size) \
|
||||
(FIELD_PREP_CONST(DW_UART_CPR_FIFO_MODE, \
|
||||
BUILD_BUG_ON_ZERO((size) > 2048) + \
|
||||
BUILD_BUG_ON_ZERO((size) % 16) + \
|
||||
((size) / 16)))
|
||||
|
||||
struct dw8250_port_data {
|
||||
/* Port properties */
|
||||
int line;
|
||||
@@ -38,3 +109,5 @@ static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
|
||||
else
|
||||
writel(reg, p->membase + offset);
|
||||
}
|
||||
|
||||
#endif /* _SERIAL_8250_DWLIB_H_ */
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/tty.h>
|
||||
#include <linux/tty_flip.h>
|
||||
#include <linux/units.h>
|
||||
|
||||
#include "8250.h"
|
||||
|
||||
@@ -521,6 +522,7 @@ static int mtk8250_probe(struct platform_device *pdev)
|
||||
struct mtk8250_data *data;
|
||||
struct resource *regs;
|
||||
int irq, err;
|
||||
struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
@@ -543,12 +545,13 @@ static int mtk8250_probe(struct platform_device *pdev)
|
||||
|
||||
data->clk_count = 0;
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
if (is_of_node(fwnode)) {
|
||||
err = mtk8250_probe_of(pdev, &uart.port, data);
|
||||
if (err)
|
||||
return err;
|
||||
} else
|
||||
} else if (!fwnode) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
spin_lock_init(&uart.port.lock);
|
||||
uart.port.mapbase = regs->start;
|
||||
@@ -564,14 +567,18 @@ static int mtk8250_probe(struct platform_device *pdev)
|
||||
uart.port.startup = mtk8250_startup;
|
||||
uart.port.set_termios = mtk8250_set_termios;
|
||||
uart.port.uartclk = clk_get_rate(data->uart_clk);
|
||||
if (!uart.port.uartclk)
|
||||
uart.port.uartclk = 26 * HZ_PER_MHZ;
|
||||
#ifdef CONFIG_SERIAL_8250_DMA
|
||||
if (data->dma)
|
||||
uart.dma = data->dma;
|
||||
#endif
|
||||
|
||||
/* Disable Rate Fix function */
|
||||
writel(0x0, uart.port.membase +
|
||||
if (is_of_node(fwnode)) {
|
||||
/* Disable Rate Fix function */
|
||||
writel(0x0, uart.port.membase +
|
||||
(MTK_UART_RATE_FIX << uart.port.regshift));
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
@@ -649,11 +656,19 @@ static const struct of_device_id mtk8250_of_match[] = {
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk8250_of_match);
|
||||
|
||||
static const struct acpi_device_id mtk8250_acpi_match[] = {
|
||||
{ "MTKI0511" },
|
||||
{ "NVDA0240" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, mtk8250_acpi_match);
|
||||
|
||||
static struct platform_driver mtk8250_platform_driver = {
|
||||
.driver = {
|
||||
.name = "mt6577-uart",
|
||||
.pm = &mtk8250_pm_ops,
|
||||
.of_match_table = mtk8250_of_match,
|
||||
.acpi_match_table = mtk8250_acpi_match,
|
||||
},
|
||||
.probe = mtk8250_probe,
|
||||
.remove = mtk8250_remove,
|
||||
|
||||
+1563
-1557
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user