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dt-bindings: drop redundant part of title (end, part three)
The Devicetree bindings document does not have to say in the title that
it is a "binding", but instead just describe the hardware.
Drop trailing "bindings" in various forms (also with trailing full
stop):
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-not -name 'trivial-devices.yaml' \
-exec sed -i -e 's/^title: \(.*\) [bB]indings\?\.\?$/title: \1/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Matti Vaittinen <mazziesaccount@gmail.com> # ROHM
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> # media
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Acked-by: Viresh Kumar <viresh.kumar@linaro.org> # cpufreq
Link: https://lore.kernel.org/r/20221216163815.522628-7-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
committed by
Rob Herring
parent
9fa3ad1a1a
commit
84e85359f4
@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CCI Interconnect Bus Masters binding
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title: CCI Interconnect Bus Masters
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maintainers:
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- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/arm/cpus.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM CPUs bindings
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title: ARM CPUs
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maintainers:
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- Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Common K3 TI-SCI bindings
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title: Common K3 TI-SCI
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maintainers:
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- Nishanth Menon <nm@ti.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/arm/sp810.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Versatile Express SP810 System Controller bindings
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title: ARM Versatile Express SP810 System Controller
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maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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@@ -4,7 +4,7 @@
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$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: STMicroelectronics STM32 ML-AHB interconnect bindings
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title: STMicroelectronics STM32 ML-AHB interconnect
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maintainers:
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- Fabien Dessenne <fabien.dessenne@foss.st.com>
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@@ -4,7 +4,7 @@
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$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: STMicroelectronics STM32 Platforms System Controller bindings
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title: STMicroelectronics STM32 Platforms System Controller
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maintainers:
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- Alexandre Torgue <alexandre.torgue@foss.st.com>
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@@ -4,7 +4,7 @@
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra194 CBB 1.0 bindings
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title: NVIDIA Tegra194 CBB 1.0
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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@@ -4,7 +4,7 @@
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$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra CBB 2.0 bindings
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title: NVIDIA Tegra CBB 2.0
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maintainers:
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- Sumit Gupta <sumitg@nvidia.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Versatile Express configuration bus bindings
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title: ARM Versatile Express configuration bus
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maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/arm/vexpress-sysreg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Versatile Express system registers bindings
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title: ARM Versatile Express system registers
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maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/ata/allwinner,sun4i-a10-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A10 AHCI SATA Controller bindings
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title: Allwinner A10 AHCI SATA Controller
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/ata/allwinner,sun8i-r40-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner R40 AHCI SATA Controller bindings
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title: Allwinner R40 AHCI SATA Controller
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments interconnect target module binding
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title: Texas Instruments interconnect target module
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maintainers:
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- Tony Lindgren <tony@atomide.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding
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title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
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maintainers:
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- Wen He <wen.he_1@nxp.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/fsl,sai-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale SAI bitclock-as-a-clock binding
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title: Freescale SAI bitclock-as-a-clock
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maintainers:
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- Michael Walle <michael@walle.cc>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/imx8m-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8M Family Clock Control Module Binding
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title: NXP i.MX8M Family Clock Control Module
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maintainers:
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- Anson Huang <Anson.Huang@nxp.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
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title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
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maintainers:
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- Aisheng Dong <aisheng.dong@nxp.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/imx8ulp-cgc-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8ULP Clock Generation & Control(CGC) Module Binding
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title: NXP i.MX8ULP Clock Generation & Control(CGC) Module
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maintainers:
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- Jacky Bai <ping.bai@nxp.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module Binding
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title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module
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maintainers:
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- Jacky Bai <ping.bai@nxp.com>
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@@ -4,7 +4,7 @@
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$id: http://devicetree.org/schemas/clock/imx93-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX93 Clock Control Module Binding
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title: NXP i.MX93 Clock Control Module
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maintainers:
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- Peng Fan <peng.fan@nxp.com>
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