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synced 2026-08-13 14:19:53 -07:00
misc: rtsx_pci: Add separate CD/WP pin polarity reversal support
Previously, the Card Detect (CD) and Write Protect (WP) pins shared the same reverse polarity setting in the configuration space. This meant both signals were reversed together, without the ability to configure them individually. This patch introduces two new parameters: sd_cd_reverse_en – enable reverse polarity for the CD pin. sd_wp_reverse_en – enable reverse polarity for the WP pin. With this change, the controller can now support: 1.Reversing both CD and WP pins together (original behavior). 2.Reversing CD and WP pins separately (newly added behavior), if supported by the configuration space. This provides greater flexibility when dealing with devices that have independent polarity requirements for CD and WP pins. Signed-off-by: Ricky Wu <ricky_wu@realtek.com> Link: https://lore.kernel.org/r/20250812063521.2427696-1-ricky_wu@realtek.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ricky Wu authored and 
Greg Kroah-Hartman committed
1 parent
6e6fe5a990
commit
807221d3c5
7 files changed
+54
-12
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@@ -79,6 +79,10 @@ static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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if (rtsx_reg_check_cd_reverse(reg))
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pcr->option.sd_cd_reverse_en = 1;
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if (rtsx_reg_check_wp_reverse(reg))
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pcr->option.sd_wp_reverse_en = 1;
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}
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static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
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@@ -127,8 +131,10 @@ static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
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/* Configure force_clock_req */
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
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else {
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
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}
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if (CHK_PCI_PID(pcr, 0x522A))
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
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@@ -350,6 +356,8 @@ void rts5227_init_params(struct rtsx_pcr *pcr)
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pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
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pcr->reg_pm_ctrl3 = PM_CTRL3;
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pcr->option.sd_cd_reverse_en = 0;
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pcr->option.sd_wp_reverse_en = 0;
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}
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static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
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@@ -508,5 +516,4 @@ void rts522a_init_params(struct rtsx_pcr *pcr)
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pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
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pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
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pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
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}
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@@ -84,6 +84,10 @@ static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr)
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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if (rtsx_reg_check_cd_reverse(reg))
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pcr->option.sd_cd_reverse_en = 1;
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if (rtsx_reg_check_wp_reverse(reg))
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pcr->option.sd_wp_reverse_en = 1;
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}
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static int rts5228_optimize_phy(struct rtsx_pcr *pcr)
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@@ -432,8 +436,10 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
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else
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rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
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else {
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rtsx_pci_write_register(pcr, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
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rtsx_pci_write_register(pcr, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
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}
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/*
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* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
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@@ -720,4 +726,6 @@ void rts5228_init_params(struct rtsx_pcr *pcr)
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hw_param->interrupt_en |= SD_OC_INT_EN;
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hw_param->ocp_glitch = SD_OCP_GLITCH_800U;
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option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930;
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option->sd_cd_reverse_en = 0;
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option->sd_wp_reverse_en = 0;
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}
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@@ -60,6 +60,7 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
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pci_read_config_dword(pdev, PCR_SETTING_REG1, ®);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
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pci_write_config_dword(pdev, 0x718, 0x0007C000);
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if (!rtsx_vendor_setting_valid(reg)) {
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pcr_dbg(pcr, "skip fetch vendor setting\n");
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@@ -82,6 +83,10 @@ static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr)
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pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
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if (rtsx_reg_check_reverse_socket(reg))
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pcr->flags |= PCR_REVERSE_SOCKET;
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if (rtsx_reg_check_cd_reverse(reg))
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pcr->option.sd_cd_reverse_en = 1;
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if (rtsx_reg_check_wp_reverse(reg))
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pcr->option.sd_wp_reverse_en = 1;
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}
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static void rts5249_init_from_cfg(struct rtsx_pcr *pcr)
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@@ -254,9 +259,11 @@ static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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/* Configure driving */
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rts5249_fill_driving(pcr, OUTPUT_3V3);
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0);
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else
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
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else {
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
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}
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rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF);
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@@ -572,6 +579,9 @@ void rts5249_init_params(struct rtsx_pcr *pcr)
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option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF;
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option->ltr_l1off_snooze_sspwrgate =
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LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF;
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option->sd_cd_reverse_en = 0;
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option->sd_wp_reverse_en = 0;
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}
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static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val)
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@@ -527,8 +527,16 @@ static void rts5264_init_from_hw(struct rtsx_pcr *pcr)
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pcr->rtd3_en = rts5264_reg_to_rtd3(lval2);
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if (rts5264_reg_check_reverse_socket(lval2))
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pcr->flags |= PCR_REVERSE_SOCKET;
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if (rts5264_reg_check_reverse_socket(lval2)) {
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if (is_version_higher_than(pcr, PID_5264, RTS5264_IC_VER_B))
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pcr->option.sd_cd_reverse_en = 1;
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else
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pcr->flags |= PCR_REVERSE_SOCKET;
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}
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if (rts5264_reg_check_wp_reverse(lval2) &&
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is_version_higher_than(pcr, PID_5264, RTS5264_IC_VER_B))
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pcr->option.sd_wp_reverse_en = 1;
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pci_read_config_dword(pdev, setting_reg1, &lval1);
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pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", setting_reg1, lval1);
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@@ -622,8 +630,10 @@ static int rts5264_extra_init_hw(struct rtsx_pcr *pcr)
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if (pcr->flags & PCR_REVERSE_SOCKET)
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rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30);
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else
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rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x00);
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else {
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rtsx_pci_write_register(pcr, PETXCFG, 0x20, option->sd_cd_reverse_en << 5);
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rtsx_pci_write_register(pcr, PETXCFG, 0x10, option->sd_wp_reverse_en << 4);
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}
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/*
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* If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
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@@ -957,4 +967,6 @@ void rts5264_init_params(struct rtsx_pcr *pcr)
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hw_param->interrupt_en |= (SD_OC_INT_EN | SD_OVP_INT_EN);
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hw_param->ocp_glitch = SD_OCP_GLITCH_800U | SDVIO_OCP_GLITCH_800U;
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option->sd_800mA_ocp_thd = RTS5264_LDO1_OCP_THD_1150;
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option->sd_cd_reverse_en = 0;
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option->sd_wp_reverse_en = 0;
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}
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@@ -14,6 +14,7 @@
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#define rts5264_reg_to_aspm(reg) \
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(((~(reg) >> 28) & 0x02) | (((reg) >> 28) & 0x01))
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#define rts5264_reg_check_reverse_socket(reg) ((reg) & 0x04)
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#define rts5264_reg_check_wp_reverse(reg) ((reg) & 0x8000)
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#define rts5264_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 22) & 0x03)
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#define rts5264_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 16) & 0x03)
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#define rts5264_reg_to_rtd3(reg) ((reg) & 0x08)
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@@ -100,6 +100,8 @@ static inline u8 map_sd_drive(int idx)
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#define rtsx_reg_to_sd30_drive_sel_3v3(reg) (((reg) >> 5) & 0x03)
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#define rtsx_reg_to_card_drive_sel(reg) ((((reg) >> 25) & 0x01) << 6)
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#define rtsx_reg_check_reverse_socket(reg) ((reg) & 0x4000)
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#define rtsx_reg_check_cd_reverse(reg) ((reg) & 0x800000)
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#define rtsx_reg_check_wp_reverse(reg) ((reg) & 0x400000)
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#define rts5209_reg_to_aspm(reg) (((reg) >> 5) & 0x03)
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#define rts5209_reg_check_ms_pmos(reg) (!((reg) & 0x08))
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#define rts5209_reg_to_sd30_drive_sel_1v8(reg) (((reg) >> 3) & 0x07)
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@@ -1160,6 +1160,8 @@ struct rtsx_cr_option {
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bool ocp_en;
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u8 sd_400mA_ocp_thd;
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u8 sd_800mA_ocp_thd;
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u8 sd_cd_reverse_en;
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u8 sd_wp_reverse_en;
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};
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/*
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