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drm/amd/display: Enable dcn42 DC

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Add support for DCN 4.2 in Display Core

Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Roman Li
2026-02-23 14:28:33 -05:00
committed by Alex Deucher
parent 083a163833
commit 6b2dd7d37b
42 changed files with 568 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
+1
View File
@@ -84,6 +84,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
case DCN_VERSION_3_51:
case DCN_VERSION_3_6:
case DCN_VERSION_4_01:
case DCN_VERSION_4_2:
*h = dal_cmd_tbl_helper_dce112_get_table2();
return true;
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+10 -1
View File
@@ -1,5 +1,5 @@
#
# Copyright 2017 Advanced Micro Devices, Inc.
# Copyright 2017-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -176,4 +176,13 @@ CLK_MGR_DCN401 = dcn401_clk_mgr.o dcn401_clk_mgr_smu_msg.o
AMD_DAL_CLK_MGR_DCN401 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn401/,$(CLK_MGR_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN401)
###############################################################################
# DCN42
###############################################################################
CLK_MGR_DCN42 = dcn42_smu.o dcn42_clk_mgr.o
AMD_DAL_CLK_MGR_DCN42 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn42/,$(CLK_MGR_DCN42))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN42)
endif
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+38 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2015 Advanced Micro Devices, Inc.
* Copyright 2015-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -846,6 +846,16 @@ void hwss_build_fast_sequence(struct dc *dc,
block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
(*num_steps)++;
}
if (current_mpc_pipe->plane_state->update_flags.bits.cm_hist_change) {
block_sequence[*num_steps].params.control_cm_hist_params.dpp
= current_mpc_pipe->plane_res.dpp;
block_sequence[*num_steps].params.control_cm_hist_params.cm_hist_control
= current_mpc_pipe->plane_state->cm_hist_control;
block_sequence[*num_steps].params.control_cm_hist_params.color_space
= current_mpc_pipe->plane_state->color_space;
block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST;
(*num_steps)++;
}
}
if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
@@ -1029,6 +1039,9 @@ void hwss_execute_sequence(struct dc *dc,
case HUBP_PROGRAM_MCACHE_ID:
hwss_program_mcache_id_and_split_coordinate(params);
break;
case DPP_PROGRAM_CM_HIST:
hwss_program_cm_hist(params);
break;
case PROGRAM_CURSOR_UPDATE_NOW:
dc->hwss.program_cursor_offload_now(
params->program_cursor_update_now_params.dc,
@@ -2054,6 +2067,16 @@ void hwss_program_mcache_id_and_split_coordinate(union block_sequence_params *pa
}
void hwss_program_cm_hist(union block_sequence_params *params)
{
struct dpp *dpp = params->control_cm_hist_params.dpp;
if (dpp && dpp->funcs->dpp_cm_hist_control)
dpp->funcs->dpp_cm_hist_control(dpp,
params->control_cm_hist_params.cm_hist_control,
params->control_cm_hist_params.color_space);
}
void get_surface_tile_visual_confirm_color(
struct pipe_ctx *pipe_ctx,
struct tg_color *color)
@@ -3370,6 +3393,20 @@ void hwss_add_opp_program_bit_depth_reduction(struct block_sequence_state *seq_s
}
}
void hwss_add_dpp_program_cm_hist(struct block_sequence_state *seq_state,
struct dpp *dpp,
struct cm_hist_control cm_hist_control,
enum dc_color_space color_space)
{
if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
seq_state->steps[*seq_state->num_steps].func = DPP_PROGRAM_CM_HIST;
seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp;
seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.cm_hist_control = cm_hist_control;
seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.color_space = color_space;
(*seq_state->num_steps)++;
}
}
void hwss_add_dc_ip_request_cntl(struct block_sequence_state *seq_state,
struct dc *dc,
bool enable)
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+7
View File
@@ -78,6 +78,7 @@
#include "dcn351/dcn351_resource.h"
#include "dcn36/dcn36_resource.h"
#include "dcn401/dcn401_resource.h"
#include "dcn42/dcn42_resource.h"
#if defined(CONFIG_DRM_AMD_DC_FP)
#include "dc_spl_translate.h"
#endif
@@ -252,6 +253,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
ASICREV_IS_GC_12_0_0_A0(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_4_01;
break;
case AMDGPU_FAMILY_GC_11_5_4:
dc_version = DCN_VERSION_4_2;
break;
default:
dc_version = DCE_VERSION_UNKNOWN;
break;
@@ -368,6 +372,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
case DCN_VERSION_4_01:
res_pool = dcn401_create_resource_pool(init_data, dc);
break;
case DCN_VERSION_4_2:
res_pool = dcn42_create_resource_pool(init_data, dc);
break;
#endif /* CONFIG_DRM_AMD_DC_FP */
default:
break;
drivers/gpu/drm/amd/display/dc/dc.h
+9 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2012-2023 Advanced Micro Devices, Inc.
* Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -733,6 +733,8 @@ struct dc_clocks {
struct {
uint8_t base_efficiency; //LP1
uint8_t low_power_efficiency; //LP2
uint8_t z8_stutter_efficiency;
int z8_stutter_period;
} stutter_efficiency;
};
@@ -1211,6 +1213,7 @@ struct dc_debug_options {
unsigned int num_fast_flips_to_steady_state_override;
bool enable_dmu_recovery;
unsigned int force_vmin_threshold;
bool enable_otg_frame_sync_pwa;
};
@@ -1419,6 +1422,7 @@ struct dc_plane_status {
struct dc_plane_address current_address;
bool is_flip_pending;
bool is_right_eye;
struct cm_hist cm_hist;
};
union surface_update_flags {
@@ -1455,6 +1459,7 @@ union surface_update_flags {
uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */
uint32_t full_update:1;
uint32_t sdr_white_level_nits:1;
uint32_t cm_hist_change:1;
} bits;
uint32_t raw;
@@ -1539,6 +1544,7 @@ struct dc_plane_state {
int sharpness_level;
enum linear_light_scaling linear_light_scaling;
unsigned int sdr_white_level_nits;
struct cm_hist_control cm_hist_control;
struct spl_sharpness_range sharpness_range;
enum sharpness_range_source sharpness_source;
};
@@ -1847,6 +1853,7 @@ struct dc_fast_update {
struct dc_transfer_func *out_transfer_func;
struct dc_csc_transform *output_csc_transform;
const struct dc_csc_transform *cursor_csc_color_matrix;
struct cm_hist_control *cm_hist_control;
};
struct dc_surface_update {
@@ -1879,6 +1886,7 @@ struct dc_surface_update {
const struct dc_csc_transform *cursor_csc_color_matrix;
unsigned int sdr_white_level_nits;
struct dc_bias_and_scale bias_and_scale;
struct cm_hist_control *cm_hist_control;
};
struct dc_underflow_debug_data {
drivers/gpu/drm/amd/display/dc/dc_helper.c
+2
View File
@@ -751,6 +751,8 @@ char *dce_version_to_string(const int version)
return "DCN 3.6";
case DCN_VERSION_4_01:
return "DCN 4.0.1";
case DCN_VERSION_4_2:
return "DCN 4.2";
default:
return "Unknown";
}
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+73
View File
@@ -271,6 +271,15 @@ enum tile_split_values_new {
DC_SURF_TILE_SPLIT_1KB = 0x4,
};
enum otg_pwa_sync_mode {
DC_OTG_PWA_FRAME_SYNC_MODE_VSYNC = 0x0,
DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP = 0x1,
};
struct otc_pwa_frame_sync {
enum otg_pwa_sync_mode pwa_sync_mode;
uint32_t pwa_frame_sync_line_offset;
};
/* TODO: These values come from hardware spec. We need to readdress this
* if they ever change.
*/
@@ -1137,6 +1146,7 @@ struct mcif_buf_params {
unsigned int warmup_pitch;
unsigned int swlock;
unsigned int p_vmid;
uint8_t tmz_id;
};
@@ -1162,5 +1172,68 @@ struct phy_state {
enum symclk_state symclk_state;
};
enum cm_hist_tap_point {
CM_HIST_TAP_POINT_1,
CM_HIST_TAP_POINT_2,
CM_HIST_TAP_POINT_3,
CM_HIST_TAP_POINT_4,
};
enum cm_hist_src {
CM_HIST_SRC1,
CM_HIST_SRC2,
CM_HIST_SRC3,
};
enum cm_hist_format {
CM_HIST_FORMAT_FIXED_POINT,
CM_HIST_FORMAT_FP16_POS,
CM_HIST_FORMAT_FP16_POS_AND_NEG,
};
enum cm_hist_read_channel_mask {
CM_HIST_READ_DISABLED,
CM_HIST_READ_CH1,
CM_HIST_READ_CH2,
CM_HIST_READ_CH1_CH2,
CM_HIST_READ_CH3,
CM_HIST_READ_CH1_CH3,
CM_HIST_READ_CH2_CH3,
CM_HIST_READ_ALL,
};
enum cm_hist_src1_mode {
CM_HIST_SRC1_MODE_R_OR_CR,
CM_HIST_SRC1_MODE_MAX_RGB,
};
enum cm_hist_src2_mode {
CM_HIST_SRC2_MODE_G_OR_Y,
CM_HIST_SRC2_MODE_RGB_TO_Y,
};
enum cm_hist_src3_mode {
CM_HIST_SRC3_MODE_B_OR_CB,
CM_HIST_SRC3_MODE_MIN_RGB,
};
struct cm_hist_control {
enum cm_hist_tap_point tap_point;
uint32_t channels_enabled;
enum cm_hist_src1_mode src_1_select;
enum cm_hist_src2_mode src_2_select;
enum cm_hist_src3_mode src_3_select;
enum cm_hist_src ch1_src;
enum cm_hist_src ch2_src;
enum cm_hist_src ch3_src;
enum cm_hist_format format;
enum cm_hist_read_channel_mask read_channel_mask;
};
struct cm_hist {
uint32_t ch1[256];
uint32_t ch2[256];
uint32_t ch3[256];
};
#endif /* DC_HW_TYPES_H */
drivers/gpu/drm/amd/display/dc/dc_types.h
+5 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
* Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -1346,6 +1346,7 @@ enum dc_cm2_gpu_mem_layout {
enum dc_cm2_gpu_mem_pixel_component_order {
DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_RGBA,
DC_CM2_GPU_MEM_PIXEL_COMPONENT_ORDER_BGRA
};
enum dc_cm2_gpu_mem_format {
@@ -1367,6 +1368,9 @@ struct dc_cm2_gpu_mem_format_parameters {
enum dc_cm2_gpu_mem_size {
DC_CM2_GPU_MEM_SIZE_171717,
DC_CM2_GPU_MEM_SIZE_333333,
DC_CM2_GPU_MEM_SIZE_454545,
DC_CM2_GPU_MEM_SIZE_656565,
DC_CM2_GPU_MEM_SIZE_TRANSFORMED,
};
drivers/gpu/drm/amd/display/dc/dccg/Makefile
+10 -1
View File
@@ -1,5 +1,5 @@
# Copyright 2022 Advanced Micro Devices, Inc.
# Copyright 2022-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -100,4 +100,13 @@ DCCG_DCN401 = dcn401_dccg.o
AMD_DAL_DCCG_DCN401 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn401/,$(DCCG_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN401)
###############################################################################
# DCN42
###############################################################################
DCCG_DCN42 = dcn42_dccg.o
AMD_DAL_DCCG_DCN42 = $(addprefix $(AMDDALPATH)/dc/dccg/dcn42/,$(DCCG_DCN42))
AMD_DISPLAY_FILES += $(AMD_DAL_DCCG_DCN42)
endif
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
+14 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2018 Advanced Micro Devices, Inc.
* Copyright 2018-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -362,6 +362,16 @@
type SYMCLK32_LE3_EN;\
type DP_DTO_ENABLE[MAX_PIPES];
#define DCCG42_REG_FIELD_LIST(type) \
type OTG0_ADD_PIXEL;\
type OTG1_ADD_PIXEL;\
type OTG2_ADD_PIXEL;\
type OTG0_DROP_PIXEL;\
type OTG1_DROP_PIXEL;\
type OTG2_DROP_PIXEL;\
type OTG3_ADD_PIXEL;\
type OTG3_DROP_PIXEL;
struct dccg_shift {
DCCG_REG_FIELD_LIST(uint8_t)
DCCG3_REG_FIELD_LIST(uint8_t)
@@ -370,6 +380,7 @@ struct dccg_shift {
DCCG32_REG_FIELD_LIST(uint8_t)
DCCG35_REG_FIELD_LIST(uint8_t)
DCCG401_REG_FIELD_LIST(uint8_t)
DCCG42_REG_FIELD_LIST(uint8_t)
};
struct dccg_mask {
@@ -380,6 +391,7 @@ struct dccg_mask {
DCCG32_REG_FIELD_LIST(uint32_t)
DCCG35_REG_FIELD_LIST(uint32_t)
DCCG401_REG_FIELD_LIST(uint32_t)
DCCG42_REG_FIELD_LIST(uint32_t)
};
#define DCCG_REG_VARIABLE_LIST \
@@ -493,6 +505,7 @@ struct dccg_mask {
struct dccg_registers {
DCCG_REG_VARIABLE_LIST;
uint32_t OTG_ADD_DROP_PIXEL_CNTL;
};
struct dcn_dccg {
drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+59 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2012-16 Advanced Micro Devices, Inc.
* Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -300,6 +300,64 @@
ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \
ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)
#define ABM_MASK_SH_LIST_DCN42(mask_sh) \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_VMAX_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
BL1_PWM_USER_LEVEL, mask_sh), \
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
ABM1_ACE_SLOPE_DATA, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_OFFSET_SLOPE_DATA, \
ABM1_ACE_OFFSET_DATA, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_OFFSET_SLOPE_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_IGNORE_MASTER_LOCK_EN, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_READBACK_DB_REG_VALUE_EN, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_DBUF_REG_UPDATE_PENDING, mask_sh), \
ABM_SF(ABM0_DC_ABM1_ACE_PWL_CNTL, \
ABM1_ACE_LOCK, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_RESULT_DATA, \
ABM1_HG_RESULT_DATA, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_RESULT_INDEX, \
ABM1_HG_RESULT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_33_40_SHIFT_INDEX, \
ABM1_HG_BIN_33_40_SHIFT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_33_64_SHIFT_FLAG, \
ABM1_HG_BIN_33_64_SHIFT_FLAG, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_41_48_SHIFT_INDEX, \
ABM1_HG_BIN_41_48_SHIFT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_49_56_SHIFT_INDEX, \
ABM1_HG_BIN_49_56_SHIFT_INDEX, mask_sh), \
ABM_SF(ABM0_DC_ABM1_HG_BIN_57_64_SHIFT_INDEX, \
ABM1_HG_BIN_57_64_SHIFT_INDEX, mask_sh)
#define ABM_REG_FIELD_LIST(type) \
type ABM1_HG_NUM_OF_BINS_SEL; \
type ABM1_HG_VMAX_SEL; \
drivers/gpu/drm/amd/display/dc/dio/Makefile
+10 -1
View File
@@ -1,5 +1,5 @@
#
# Copyright 2020 Advanced Micro Devices, Inc.
# Copyright 2020-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -123,4 +123,13 @@ DIO_DCN401 = dcn401_dio_link_encoder.o dcn401_dio_stream_encoder.o
AMD_DAL_DIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/dio/dcn401/,$(DIO_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN401)
###############################################################################
# DCN42
###############################################################################
DIO_DCN42 = dcn42_dio_link_encoder.o dcn42_dio_stream_encoder.o
AMD_DAL_DIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/dio/dcn42/,$(DIO_DCN42))
AMD_DISPLAY_FILES += $(AMD_DAL_DIO_DCN42)
endif
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
+9 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
* Copyright 2012-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -190,6 +190,7 @@ struct dcn10_stream_enc_registers {
uint32_t DIG_FE_CLK_CNTL;
uint32_t DIG_FE_EN_CNTL;
uint32_t STREAM_MAPPER_CONTROL;
uint32_t DIG_FE_AUDIO_CNTL;
};
@@ -598,6 +599,11 @@ struct dcn10_stream_enc_registers {
type DP_VID_N_INTERVAL;\
type DIG_FIFO_OUTPUT_PIXEL_PER_CYCLE;\
type DP_STEER_FIFO_ENABLE
#define SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(type) \
type DIG_FE_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\
type APG_CLOCK_ENABLE
struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN1_0(uint8_t);
uint8_t HDMI_ACP_SEND;
@@ -606,6 +612,7 @@ struct dcn10_stream_encoder_shift {
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint8_t);
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t);
};
struct dcn10_stream_encoder_mask {
@@ -616,6 +623,7 @@ struct dcn10_stream_encoder_mask {
SE_REG_FIELD_LIST_DCN3_1_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN3_5_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN4_01_COMMON(uint32_t);
SE_REG_FIELD_LIST_DCN_AUDIO_COMMON(uint32_t);
};
struct dcn10_stream_encoder {
drivers/gpu/drm/amd/display/dc/dpp/Makefile
+9 -1
View File
@@ -1,5 +1,5 @@
# Copyright 2022 Advanced Micro Devices, Inc.
# Copyright 2022-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -80,4 +80,12 @@ AMD_DAL_DPP_DCN401 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn401/,$(DPP_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN401)
###############################################################################
# DCN42
###############################################################################
DPP_DCN42 = dcn42_dpp.o
AMD_DAL_DPP_DCN42 = $(addprefix $(AMDDALPATH)/dc/dpp/dcn42/,$(DPP_DCN42))
AMD_DISPLAY_FILES += $(AMD_DAL_DPP_DCN42)
endif
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h
+4 -1
View File
@@ -1,4 +1,5 @@
/* Copyright 2023 Advanced Micro Devices, Inc.
/* SPDX-License-Identifier: MIT */
/* Copyright 2023-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -653,6 +654,8 @@
struct dcn401_dpp_registers {
DPP_REG_VARIABLE_LIST_DCN401;
uint32_t ALPHA_2BIT_LUT01;
uint32_t ALPHA_2BIT_LUT23;
};
struct dcn401_dpp_shift {
drivers/gpu/drm/amd/display/dc/gpio/Makefile
+12 -1
View File
@@ -1,5 +1,5 @@
#
# Copyright 2017 Advanced Micro Devices, Inc.
# Copyright 2017-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -132,3 +132,14 @@ AMD_DAL_GPIO_DCN401 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn401/,$(GPIO_DCN401))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN401)
###############################################################################
# DCN 4.2
###############################################################################
GPIO_DCN42 = hw_translate_dcn42.o hw_factory_dcn42.o
AMD_DAL_GPIO_DCN42 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn42/,$(GPIO_DCN42))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN42)
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
+4
View File
@@ -53,6 +53,7 @@
#include "dcn315/hw_factory_dcn315.h"
#include "dcn32/hw_factory_dcn32.h"
#include "dcn401/hw_factory_dcn401.h"
#include "dcn42/hw_factory_dcn42.h"
bool dal_hw_factory_init(
struct hw_factory *factory,
@@ -118,6 +119,9 @@ bool dal_hw_factory_init(
case DCN_VERSION_4_01:
dal_hw_factory_dcn401_init(factory);
return true;
case DCN_VERSION_4_2:
dal_hw_factory_dcn42_init(factory);
return true;
default:
ASSERT_CRITICAL(false);
return false;
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
+4
View File
@@ -53,6 +53,7 @@
#include "dcn315/hw_translate_dcn315.h"
#include "dcn32/hw_translate_dcn32.h"
#include "dcn401/hw_translate_dcn401.h"
#include "dcn42/hw_translate_dcn42.h"
/*
* This unit
@@ -119,6 +120,9 @@ bool dal_hw_translate_init(
case DCN_VERSION_4_01:
dal_hw_translate_dcn401_init(translate);
return true;
case DCN_VERSION_4_2:
dal_hw_translate_dcn42_init(translate);
return true;
default:
BREAK_TO_DEBUGGER();
return false;
drivers/gpu/drm/amd/display/dc/hpo/Makefile
+10 -1
View File
@@ -1,5 +1,5 @@
#
# Copyright 2020 Advanced Micro Devices, Inc.
# Copyright 2020-2026 Advanced Micro Devices, Inc.
#
# Permission is hereby granted, free of charge, to any person obtaining a
# copy of this software and associated documentation files (the "Software"),
@@ -47,4 +47,13 @@ HPO_DCN32 = dcn32_hpo_dp_link_encoder.o
AMD_DAL_HPO_DCN32 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn32/,$(HPO_DCN32))
AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN32)
###############################################################################
# DCN42
###############################################################################
HPO_DCN42 = dcn42_hpo_dp_link_encoder.o
AMD_DAL_HPO_DCN42 = $(addprefix $(AMDDALPATH)/dc/hpo/dcn42/,$(HPO_DCN42))
AMD_DISPLAY_FILES += $(AMD_DAL_HPO_DCN42)
endif
drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.h
+8 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright 2019 Advanced Micro Devices, Inc.
* Copyright 2019-2026 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -208,17 +208,24 @@
type CRC_CONT_MODE_ENABLE;\
type HBLANK_MINIMUM_SYMBOL_WIDTH
#define DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
type DP_STREAM_ENC_APG_CLOCK_EN
#define DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\
DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh),\
SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_APG_CLOCK_EN, mask_sh)
struct dcn31_hpo_dp_stream_encoder_registers {
DCN3_1_HPO_DP_STREAM_ENC_REGS;
};
struct dcn31_hpo_dp_stream_encoder_shift {
DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);
};
struct dcn31_hpo_dp_stream_encoder_mask {
DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
DCN4_2_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);
};
struct dcn31_hpo_dp_stream_encoder {
@@ -241,5 +248,4 @@ void dcn31_hpo_dp_stream_encoder_construct(
const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,
const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask);
#endif // __DAL_DCN31_HPO_STREAM_ENCODER_H__

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