mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'sh-for-v6.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux
Pull sh updates from John Paul Adrian Glaubitz:
"While the previously announced patch series for converting arch/sh to
device trees is not yet ready for inclusion to mainline and therefore
didn't make it for this pull request, there are still a small number
changes for v6.7 which include one platform (board plus CPU and driver
code) removal plus two fixes.
The removal sent in by Arnd Bergmann concerns the microdev board which
was an early SuperH prototype board that was never used in production.
With the board removed, we were able to drop the now unused code for
the SH4-202 CPU and well as the driver code for the superhyway bus and
a custom implementation for ioport_map() and ioport_unmap() which will
allow us to simplify ioport handling in the future.
Another patch set by Geert Uytterhoeven revives SuperH BIOS
earlyprintk support which got accidentally disabled in
e76fe57447 ("sh: Remove old early serial console code V2"), the
second patch in the series updates the documentation.
Finally, a patch by Masami Hiramatsu fixes a regression reported by
the kernel test robot which uncovered that arch/sh is not implementing
arch_cmpxchg_local() and therefore needs use __generic_cmpxchg_local()
instead"
* tag 'sh-for-v6.7-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux:
locking/atomic: sh: Use generic_cmpxchg_local for arch_cmpxchg_local()
Documentation: kernel-parameters: Add earlyprintk=bios on SH
sh: bios: Revive earlyprintk support
sh: machvec: Remove custom ioport_{un,}map()
sh: Remove superhyway bus support
sh: Remove unused SH4-202 support
sh: Remove stale microdev board
This commit is contained in:
Linus Torvalds
@@ -1335,6 +1335,7 @@
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earlyprintk=dbgp[debugController#]
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earlyprintk=pciserial[,force],bus:device.function[,baudrate]
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earlyprintk=xdbc[xhciController#]
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earlyprintk=bios
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earlyprintk is useful when the kernel crashes before
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the normal console is initialized. It is not enabled by
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@@ -1365,6 +1366,8 @@
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The sclp output can only be used on s390.
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The bios output can only be used on SuperH.
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The optional "force" to "pciserial" enables use of a
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PCI device even when its classcode is not of the
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UART class.
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@@ -43,12 +43,6 @@ mach-x3proto
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Busses
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======
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SuperHyway
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----------
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.. kernel-doc:: drivers/sh/superhyway/superhyway.c
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:export:
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Maple
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-----
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+1
-11
@@ -124,8 +124,7 @@ config ARCH_HAS_ILOG2_U64
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config NO_IOPORT_MAP
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def_bool !PCI
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depends on !SH_SH4202_MICRODEV && !SH_SHMIN && !SH_HP6XX && \
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!SH_SOLUTION_ENGINE
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depends on !SH_SHMIN && !SH_HP6XX && !SH_SOLUTION_ENGINE
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config IO_TRAPPED
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bool
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@@ -384,10 +383,6 @@ config CPU_SUBTYPE_SH7760
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bool "Support SH7760 processor"
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select CPU_SH4
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config CPU_SUBTYPE_SH4_202
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bool "Support SH4-202 processor"
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select CPU_SH4
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# SH-4A Processor Support
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config CPU_SUBTYPE_SH7723
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@@ -518,7 +513,6 @@ config SH_PCLK_FREQ
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CPU_SUBTYPE_SH7263 || \
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CPU_SUBTYPE_MXG
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default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
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default "66000000" if CPU_SUBTYPE_SH4_202
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default "50000000"
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help
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This option is used to specify the peripheral clock frequency.
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@@ -743,10 +737,6 @@ endmenu
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menu "Bus options"
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config SUPERHYWAY
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tristate "SuperHyway Bus support"
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depends on CPU_SUBTYPE_SH4_202
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config MAPLE
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bool "Maple Bus support"
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depends on SH_DREAMCAST
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@@ -22,6 +22,17 @@ config STACK_DEBUG
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every function call and will therefore incur a major
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performance hit. Most users should say N.
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config EARLY_PRINTK
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bool "Early printk"
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depends on SH_STANDARD_BIOS
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help
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Say Y here to redirect kernel printk messages to the serial port
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used by the SH-IPL bootloader, starting very early in the boot
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process and ending when the kernel's serial console is initialised.
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This option is only useful while porting the kernel to a new machine,
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when the kernel may crash or hang before the serial console is
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initialised. If unsure, say N.
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config 4KSTACKS
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bool "Use 4Kb for kernel stacks instead of 8Kb"
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depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
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@@ -289,13 +289,6 @@ config SH_EDOSK7760
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Select if configuring for a Renesas EDOSK7760
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evaluation board.
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config SH_SH4202_MICRODEV
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bool "SH4-202 MicroDev"
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depends on CPU_SUBTYPE_SH4_202
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help
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Select SH4-202 MicroDev if configuring for a SuperH MicroDev board
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with an SH4-202 CPU.
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config SH_LANDISK
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bool "LANDISK"
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depends on CPU_SUBTYPE_SH7751R
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@@ -33,7 +33,6 @@ obj-$(CONFIG_SH_SDK7780) += mach-sdk7780/
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obj-$(CONFIG_SH_SDK7786) += mach-sdk7786/
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obj-$(CONFIG_SH_X3PROTO) += mach-x3proto/
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obj-$(CONFIG_SH_SH7763RDP) += mach-sh7763rdp/
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obj-$(CONFIG_SH_SH4202_MICRODEV)+= mach-microdev/
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obj-$(CONFIG_SH_LANDISK) += mach-landisk/
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obj-$(CONFIG_SH_LBOX_RE2) += mach-lboxre2/
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obj-$(CONFIG_SH_RSK) += mach-rsk/
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@@ -1,6 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the SuperH MicroDev specific parts of the kernel
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#
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obj-y := setup.o irq.o io.o fdc37c93xapm.o
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@@ -1,157 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Setup for the SMSC FDC37C93xAPM
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*
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* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
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* Copyright (C) 2003, 2004 SuperH, Inc.
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* Copyright (C) 2004, 2005 Paul Mundt
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*
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* SuperH SH4-202 MicroDev board support.
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <mach/microdev.h>
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#define SMSC_CONFIG_PORT_ADDR (0x3F0)
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#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
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#define SMSC_DATA_PORT_ADDR (SMSC_INDEX_PORT_ADDR + 1)
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#define SMSC_ENTER_CONFIG_KEY 0x55
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#define SMSC_EXIT_CONFIG_KEY 0xaa
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#define SMCS_LOGICAL_DEV_INDEX 0x07 /* Logical Device Number */
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#define SMSC_DEVICE_ID_INDEX 0x20 /* Device ID */
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#define SMSC_DEVICE_REV_INDEX 0x21 /* Device Revision */
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#define SMSC_ACTIVATE_INDEX 0x30 /* Activate */
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#define SMSC_PRIMARY_BASE_INDEX 0x60 /* Primary Base Address */
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#define SMSC_SECONDARY_BASE_INDEX 0x62 /* Secondary Base Address */
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#define SMSC_PRIMARY_INT_INDEX 0x70 /* Primary Interrupt Select */
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#define SMSC_SECONDARY_INT_INDEX 0x72 /* Secondary Interrupt Select */
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#define SMSC_HDCS0_INDEX 0xf0 /* HDCS0 Address Decoder */
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#define SMSC_HDCS1_INDEX 0xf1 /* HDCS1 Address Decoder */
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#define SMSC_IDE1_DEVICE 1 /* IDE #1 logical device */
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#define SMSC_IDE2_DEVICE 2 /* IDE #2 logical device */
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#define SMSC_PARALLEL_DEVICE 3 /* Parallel Port logical device */
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#define SMSC_SERIAL1_DEVICE 4 /* Serial #1 logical device */
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#define SMSC_SERIAL2_DEVICE 5 /* Serial #2 logical device */
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#define SMSC_KEYBOARD_DEVICE 7 /* Keyboard logical device */
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#define SMSC_CONFIG_REGISTERS 8 /* Configuration Registers (Aux I/O) */
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#define SMSC_READ_INDEXED(index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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inb(SMSC_DATA_PORT_ADDR); })
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#define SMSC_WRITE_INDEXED(val, index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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outb((val), SMSC_DATA_PORT_ADDR); })
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#define IDE1_PRIMARY_BASE 0x01f0 /* Task File Registe base for IDE #1 */
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#define IDE1_SECONDARY_BASE 0x03f6 /* Miscellaneous AT registers for IDE #1 */
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#define IDE2_PRIMARY_BASE 0x0170 /* Task File Registe base for IDE #2 */
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#define IDE2_SECONDARY_BASE 0x0376 /* Miscellaneous AT registers for IDE #2 */
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#define SERIAL1_PRIMARY_BASE 0x03f8
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#define SERIAL2_PRIMARY_BASE 0x02f8
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#define MSB(x) ( (x) >> 8 )
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#define LSB(x) ( (x) & 0xff )
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/* General-Purpose base address on CPU-board FPGA */
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#define MICRODEV_FPGA_GP_BASE 0xa6100000ul
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static int __init smsc_superio_setup(void)
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{
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unsigned char devid, devrev;
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/* Initially the chip is in run state */
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/* Put it into configuration state */
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outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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/* Read device ID info */
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devid = SMSC_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
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devrev = SMSC_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
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if ((devid == 0x30) && (devrev == 0x01))
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printk("SMSC FDC37C93xAPM SuperIO device detected\n");
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else
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return -ENODEV;
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/* Select the keyboard device */
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SMSC_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_KEYBOARD, SMSC_PRIMARY_INT_INDEX);
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_MOUSE, SMSC_SECONDARY_INT_INDEX);
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/* Select the Serial #1 device */
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SMSC_WRITE_INDEXED(SMSC_SERIAL1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(SERIAL1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL1, SMSC_PRIMARY_INT_INDEX);
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/* Select the Serial #2 device */
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SMSC_WRITE_INDEXED(SMSC_SERIAL2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(SERIAL2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS0_INDEX);
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/* enable the interrupts */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_SERIAL2, SMSC_PRIMARY_INT_INDEX);
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/* Select the IDE#1 device */
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SMSC_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
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SMSC_WRITE_INDEXED(MSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE1_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(MSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
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SMSC_WRITE_INDEXED(LSB(IDE1_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
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SMSC_WRITE_INDEXED(0x0c, SMSC_HDCS0_INDEX);
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SMSC_WRITE_INDEXED(0x00, SMSC_HDCS1_INDEX);
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/* select the interrupt */
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SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE1, SMSC_PRIMARY_INT_INDEX);
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/* Select the IDE#2 device */
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SMSC_WRITE_INDEXED(SMSC_IDE2_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
|
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SMSC_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* program with port addresses */
|
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SMSC_WRITE_INDEXED(MSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+0);
|
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SMSC_WRITE_INDEXED(LSB(IDE2_PRIMARY_BASE), SMSC_PRIMARY_BASE_INDEX+1);
|
||||
SMSC_WRITE_INDEXED(MSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+0);
|
||||
SMSC_WRITE_INDEXED(LSB(IDE2_SECONDARY_BASE), SMSC_SECONDARY_BASE_INDEX+1);
|
||||
/* select the interrupt */
|
||||
SMSC_WRITE_INDEXED(MICRODEV_FPGA_IRQ_IDE2, SMSC_PRIMARY_INT_INDEX);
|
||||
|
||||
/* Select the configuration registers */
|
||||
SMSC_WRITE_INDEXED(SMSC_CONFIG_REGISTERS, SMCS_LOGICAL_DEV_INDEX);
|
||||
/* enable the appropriate GPIO pins for IDE functionality:
|
||||
* bit[0] In/Out 1==input; 0==output
|
||||
* bit[1] Polarity 1==invert; 0==no invert
|
||||
* bit[2] Int Enb #1 1==Enable Combined IRQ #1; 0==disable
|
||||
* bit[3:4] Function Select 00==original; 01==Alternate Function #1
|
||||
*/
|
||||
SMSC_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
|
||||
SMSC_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
|
||||
SMSC_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
|
||||
SMSC_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
|
||||
SMSC_WRITE_INDEXED(0x08, 0xe8); /* GP20 = nIDE2_OE */
|
||||
|
||||
/* Exit the configuration state */
|
||||
outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(smsc_superio_setup);
|
||||
@@ -1,123 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* linux/arch/sh/boards/superh/microdev/io.c
|
||||
*
|
||||
* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
|
||||
* Copyright (C) 2003, 2004 SuperH, Inc.
|
||||
* Copyright (C) 2004 Paul Mundt
|
||||
*
|
||||
* SuperH SH4-202 MicroDev board support.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/wait.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/microdev.h>
|
||||
|
||||
/*
|
||||
* we need to have a 'safe' address to re-direct all I/O requests
|
||||
* that we do not explicitly wish to handle. This safe address
|
||||
* must have the following properies:
|
||||
*
|
||||
* * writes are ignored (no exception)
|
||||
* * reads are benign (no side-effects)
|
||||
* * accesses of width 1, 2 and 4-bytes are all valid.
|
||||
*
|
||||
* The Processor Version Register (PVR) has these properties.
|
||||
*/
|
||||
#define PVR 0xff000030 /* Processor Version Register */
|
||||
|
||||
|
||||
#define IO_IDE2_BASE 0x170ul /* I/O base for SMSC FDC37C93xAPM IDE #2 */
|
||||
#define IO_IDE1_BASE 0x1f0ul /* I/O base for SMSC FDC37C93xAPM IDE #1 */
|
||||
#define IO_ISP1161_BASE 0x290ul /* I/O port for Philips ISP1161x USB chip */
|
||||
#define IO_SERIAL2_BASE 0x2f8ul /* I/O base for SMSC FDC37C93xAPM Serial #2 */
|
||||
#define IO_LAN91C111_BASE 0x300ul /* I/O base for SMSC LAN91C111 Ethernet chip */
|
||||
#define IO_IDE2_MISC 0x376ul /* I/O misc for SMSC FDC37C93xAPM IDE #2 */
|
||||
#define IO_SUPERIO_BASE 0x3f0ul /* I/O base for SMSC FDC37C93xAPM SuperIO chip */
|
||||
#define IO_IDE1_MISC 0x3f6ul /* I/O misc for SMSC FDC37C93xAPM IDE #1 */
|
||||
#define IO_SERIAL1_BASE 0x3f8ul /* I/O base for SMSC FDC37C93xAPM Serial #1 */
|
||||
|
||||
#define IO_ISP1161_EXTENT 0x04ul /* I/O extent for Philips ISP1161x USB chip */
|
||||
#define IO_LAN91C111_EXTENT 0x10ul /* I/O extent for SMSC LAN91C111 Ethernet chip */
|
||||
#define IO_SUPERIO_EXTENT 0x02ul /* I/O extent for SMSC FDC37C93xAPM SuperIO chip */
|
||||
#define IO_IDE_EXTENT 0x08ul /* I/O extent for IDE Task Register set */
|
||||
#define IO_SERIAL_EXTENT 0x10ul
|
||||
|
||||
#define IO_LAN91C111_PHYS 0xa7500000ul /* Physical address of SMSC LAN91C111 Ethernet chip */
|
||||
#define IO_ISP1161_PHYS 0xa7700000ul /* Physical address of Philips ISP1161x USB chip */
|
||||
#define IO_SUPERIO_PHYS 0xa7800000ul /* Physical address of SMSC FDC37C93xAPM SuperIO chip */
|
||||
|
||||
/*
|
||||
* map I/O ports to memory-mapped addresses
|
||||
*/
|
||||
void __iomem *microdev_ioport_map(unsigned long offset, unsigned int len)
|
||||
{
|
||||
unsigned long result;
|
||||
|
||||
if ((offset >= IO_LAN91C111_BASE) &&
|
||||
(offset < IO_LAN91C111_BASE + IO_LAN91C111_EXTENT)) {
|
||||
/*
|
||||
* SMSC LAN91C111 Ethernet chip
|
||||
*/
|
||||
result = IO_LAN91C111_PHYS + offset - IO_LAN91C111_BASE;
|
||||
} else if ((offset >= IO_SUPERIO_BASE) &&
|
||||
(offset < IO_SUPERIO_BASE + IO_SUPERIO_EXTENT)) {
|
||||
/*
|
||||
* SMSC FDC37C93xAPM SuperIO chip
|
||||
*
|
||||
* Configuration Registers
|
||||
*/
|
||||
result = IO_SUPERIO_PHYS + (offset << 1);
|
||||
} else if (((offset >= IO_IDE1_BASE) &&
|
||||
(offset < IO_IDE1_BASE + IO_IDE_EXTENT)) ||
|
||||
(offset == IO_IDE1_MISC)) {
|
||||
/*
|
||||
* SMSC FDC37C93xAPM SuperIO chip
|
||||
*
|
||||
* IDE #1
|
||||
*/
|
||||
result = IO_SUPERIO_PHYS + (offset << 1);
|
||||
} else if (((offset >= IO_IDE2_BASE) &&
|
||||
(offset < IO_IDE2_BASE + IO_IDE_EXTENT)) ||
|
||||
(offset == IO_IDE2_MISC)) {
|
||||
/*
|
||||
* SMSC FDC37C93xAPM SuperIO chip
|
||||
*
|
||||
* IDE #2
|
||||
*/
|
||||
result = IO_SUPERIO_PHYS + (offset << 1);
|
||||
} else if ((offset >= IO_SERIAL1_BASE) &&
|
||||
(offset < IO_SERIAL1_BASE + IO_SERIAL_EXTENT)) {
|
||||
/*
|
||||
* SMSC FDC37C93xAPM SuperIO chip
|
||||
*
|
||||
* Serial #1
|
||||
*/
|
||||
result = IO_SUPERIO_PHYS + (offset << 1);
|
||||
} else if ((offset >= IO_SERIAL2_BASE) &&
|
||||
(offset < IO_SERIAL2_BASE + IO_SERIAL_EXTENT)) {
|
||||
/*
|
||||
* SMSC FDC37C93xAPM SuperIO chip
|
||||
*
|
||||
* Serial #2
|
||||
*/
|
||||
result = IO_SUPERIO_PHYS + (offset << 1);
|
||||
} else if ((offset >= IO_ISP1161_BASE) &&
|
||||
(offset < IO_ISP1161_BASE + IO_ISP1161_EXTENT)) {
|
||||
/*
|
||||
* Philips USB ISP1161x chip
|
||||
*/
|
||||
result = IO_ISP1161_PHYS + offset - IO_ISP1161_BASE;
|
||||
} else {
|
||||
/*
|
||||
* safe default.
|
||||
*/
|
||||
printk("Warning: unexpected port in %s( offset = 0x%lx )\n",
|
||||
__func__, offset);
|
||||
result = PVR;
|
||||
}
|
||||
|
||||
return (void __iomem *)result;
|
||||
}
|
||||
@@ -1,150 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/sh/boards/superh/microdev/irq.c
|
||||
*
|
||||
* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
|
||||
*
|
||||
* SuperH SH4-202 MicroDev board support.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <asm/io.h>
|
||||
#include <mach/microdev.h>
|
||||
|
||||
#define NUM_EXTERNAL_IRQS 16 /* IRL0 .. IRL15 */
|
||||
|
||||
static const struct {
|
||||
unsigned char fpgaIrq;
|
||||
unsigned char mapped;
|
||||
const char *name;
|
||||
} fpgaIrqTable[NUM_EXTERNAL_IRQS] = {
|
||||
{ 0, 0, "unused" }, /* IRQ #0 IRL=15 0x200 */
|
||||
{ MICRODEV_FPGA_IRQ_KEYBOARD, 1, "keyboard" }, /* IRQ #1 IRL=14 0x220 */
|
||||
{ MICRODEV_FPGA_IRQ_SERIAL1, 1, "Serial #1"}, /* IRQ #2 IRL=13 0x240 */
|
||||
{ MICRODEV_FPGA_IRQ_ETHERNET, 1, "Ethernet" }, /* IRQ #3 IRL=12 0x260 */
|
||||
{ MICRODEV_FPGA_IRQ_SERIAL2, 0, "Serial #2"}, /* IRQ #4 IRL=11 0x280 */
|
||||
{ 0, 0, "unused" }, /* IRQ #5 IRL=10 0x2a0 */
|
||||
{ 0, 0, "unused" }, /* IRQ #6 IRL=9 0x2c0 */
|
||||
{ MICRODEV_FPGA_IRQ_USB_HC, 1, "USB" }, /* IRQ #7 IRL=8 0x2e0 */
|
||||
{ MICRODEV_IRQ_PCI_INTA, 1, "PCI INTA" }, /* IRQ #8 IRL=7 0x300 */
|
||||
{ MICRODEV_IRQ_PCI_INTB, 1, "PCI INTB" }, /* IRQ #9 IRL=6 0x320 */
|
||||
{ MICRODEV_IRQ_PCI_INTC, 1, "PCI INTC" }, /* IRQ #10 IRL=5 0x340 */
|
||||
{ MICRODEV_IRQ_PCI_INTD, 1, "PCI INTD" }, /* IRQ #11 IRL=4 0x360 */
|
||||
{ MICRODEV_FPGA_IRQ_MOUSE, 1, "mouse" }, /* IRQ #12 IRL=3 0x380 */
|
||||
{ MICRODEV_FPGA_IRQ_IDE2, 1, "IDE #2" }, /* IRQ #13 IRL=2 0x3a0 */
|
||||
{ MICRODEV_FPGA_IRQ_IDE1, 1, "IDE #1" }, /* IRQ #14 IRL=1 0x3c0 */
|
||||
{ 0, 0, "unused" }, /* IRQ #15 IRL=0 0x3e0 */
|
||||
};
|
||||
|
||||
#if (MICRODEV_LINUX_IRQ_KEYBOARD != 1)
|
||||
# error Inconsistancy in defining the IRQ# for Keyboard!
|
||||
#endif
|
||||
|
||||
#if (MICRODEV_LINUX_IRQ_ETHERNET != 3)
|
||||
# error Inconsistancy in defining the IRQ# for Ethernet!
|
||||
#endif
|
||||
|
||||
#if (MICRODEV_LINUX_IRQ_USB_HC != 7)
|
||||
# error Inconsistancy in defining the IRQ# for USB!
|
||||
#endif
|
||||
|
||||
#if (MICRODEV_LINUX_IRQ_MOUSE != 12)
|
||||
# error Inconsistancy in defining the IRQ# for PS/2 Mouse!
|
||||
#endif
|
||||
|
||||
#if (MICRODEV_LINUX_IRQ_IDE2 != 13)
|
||||
# error Inconsistancy in defining the IRQ# for secondary IDE!
|
||||
#endif
|
||||
|
||||
#if (MICRODEV_LINUX_IRQ_IDE1 != 14)
|
||||
# error Inconsistancy in defining the IRQ# for primary IDE!
|
||||
#endif
|
||||
|
||||
static void disable_microdev_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
unsigned int fpgaIrq;
|
||||
|
||||
if (irq >= NUM_EXTERNAL_IRQS)
|
||||
return;
|
||||
if (!fpgaIrqTable[irq].mapped)
|
||||
return;
|
||||
|
||||
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
|
||||
|
||||
/* disable interrupts on the FPGA INTC register */
|
||||
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
|
||||
}
|
||||
|
||||
static void enable_microdev_irq(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
unsigned long priorityReg, priorities, pri;
|
||||
unsigned int fpgaIrq;
|
||||
|
||||
if (unlikely(irq >= NUM_EXTERNAL_IRQS))
|
||||
return;
|
||||
if (unlikely(!fpgaIrqTable[irq].mapped))
|
||||
return;
|
||||
|
||||
pri = 15 - irq;
|
||||
|
||||
fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
|
||||
priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
|
||||
|
||||
/* set priority for the interrupt */
|
||||
priorities = __raw_readl(priorityReg);
|
||||
priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
|
||||
priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
|
||||
__raw_writel(priorities, priorityReg);
|
||||
|
||||
/* enable interrupts on the FPGA INTC register */
|
||||
__raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
|
||||
}
|
||||
|
||||
static struct irq_chip microdev_irq_type = {
|
||||
.name = "MicroDev-IRQ",
|
||||
.irq_unmask = enable_microdev_irq,
|
||||
.irq_mask = disable_microdev_irq,
|
||||
};
|
||||
|
||||
/* This function sets the desired irq handler to be a MicroDev type */
|
||||
static void __init make_microdev_irq(unsigned int irq)
|
||||
{
|
||||
disable_irq_nosync(irq);
|
||||
irq_set_chip_and_handler(irq, µdev_irq_type, handle_level_irq);
|
||||
disable_microdev_irq(irq_get_irq_data(irq));
|
||||
}
|
||||
|
||||
extern void __init init_microdev_irq(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* disable interrupts on the FPGA INTC register */
|
||||
__raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG);
|
||||
|
||||
for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
|
||||
make_microdev_irq(i);
|
||||
}
|
||||
|
||||
extern void microdev_print_fpga_intc_status(void)
|
||||
{
|
||||
volatile unsigned int * const intenb = (unsigned int*)MICRODEV_FPGA_INTENB_REG;
|
||||
volatile unsigned int * const intdsb = (unsigned int*)MICRODEV_FPGA_INTDSB_REG;
|
||||
volatile unsigned int * const intpria = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(0);
|
||||
volatile unsigned int * const intprib = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(8);
|
||||
volatile unsigned int * const intpric = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(16);
|
||||
volatile unsigned int * const intprid = (unsigned int*)MICRODEV_FPGA_INTPRI_REG(24);
|
||||
volatile unsigned int * const intsrc = (unsigned int*)MICRODEV_FPGA_INTSRC_REG;
|
||||
volatile unsigned int * const intreq = (unsigned int*)MICRODEV_FPGA_INTREQ_REG;
|
||||
|
||||
printk("-------------------------- microdev_print_fpga_intc_status() ------------------\n");
|
||||
printk("FPGA_INTENB = 0x%08x\n", *intenb);
|
||||
printk("FPGA_INTDSB = 0x%08x\n", *intdsb);
|
||||
printk("FPGA_INTSRC = 0x%08x\n", *intsrc);
|
||||
printk("FPGA_INTREQ = 0x%08x\n", *intreq);
|
||||
printk("FPGA_INTPRI[3..0] = %08x:%08x:%08x:%08x\n", *intprid, *intpric, *intprib, *intpria);
|
||||
printk("-------------------------------------------------------------------------------\n");
|
||||
}
|
||||
@@ -1,197 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/sh/boards/superh/microdev/setup.c
|
||||
*
|
||||
* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
|
||||
* Copyright (C) 2003, 2004 SuperH, Inc.
|
||||
* Copyright (C) 2004, 2005 Paul Mundt
|
||||
*
|
||||
* SuperH SH4-202 MicroDev board support.
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <video/s1d13xxxfb.h>
|
||||
#include <mach/microdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machvec.h>
|
||||
#include <linux/sizes.h>
|
||||
|
||||
static struct resource smc91x_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x300,
|
||||
.end = 0x300 + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = MICRODEV_LINUX_IRQ_ETHERNET,
|
||||
.end = MICRODEV_LINUX_IRQ_ETHERNET,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device smc91x_device = {
|
||||
.name = "smc91x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(smc91x_resources),
|
||||
.resource = smc91x_resources,
|
||||
};
|
||||
|
||||
static struct s1d13xxxfb_regval s1d13806_initregs[] = {
|
||||
{ S1DREG_MISC, 0x00 },
|
||||
{ S1DREG_COM_DISP_MODE, 0x00 },
|
||||
{ S1DREG_GPIO_CNF0, 0x00 },
|
||||
{ S1DREG_GPIO_CNF1, 0x00 },
|
||||
{ S1DREG_GPIO_CTL0, 0x00 },
|
||||
{ S1DREG_GPIO_CTL1, 0x00 },
|
||||
{ S1DREG_CLK_CNF, 0x02 },
|
||||
{ S1DREG_LCD_CLK_CNF, 0x01 },
|
||||
{ S1DREG_CRT_CLK_CNF, 0x03 },
|
||||
{ S1DREG_MPLUG_CLK_CNF, 0x03 },
|
||||
{ S1DREG_CPU2MEM_WST_SEL, 0x02 },
|
||||
{ S1DREG_SDRAM_REF_RATE, 0x03 },
|
||||
{ S1DREG_SDRAM_TC0, 0x00 },
|
||||
{ S1DREG_SDRAM_TC1, 0x01 },
|
||||
{ S1DREG_MEM_CNF, 0x80 },
|
||||
{ S1DREG_PANEL_TYPE, 0x25 },
|
||||
{ S1DREG_MOD_RATE, 0x00 },
|
||||
{ S1DREG_LCD_DISP_HWIDTH, 0x63 },
|
||||
{ S1DREG_LCD_NDISP_HPER, 0x1e },
|
||||
{ S1DREG_TFT_FPLINE_START, 0x06 },
|
||||
{ S1DREG_TFT_FPLINE_PWIDTH, 0x03 },
|
||||
{ S1DREG_LCD_DISP_VHEIGHT0, 0x57 },
|
||||
{ S1DREG_LCD_DISP_VHEIGHT1, 0x02 },
|
||||
{ S1DREG_LCD_NDISP_VPER, 0x00 },
|
||||
{ S1DREG_TFT_FPFRAME_START, 0x0a },
|
||||
{ S1DREG_TFT_FPFRAME_PWIDTH, 0x81 },
|
||||
{ S1DREG_LCD_DISP_MODE, 0x03 },
|
||||
{ S1DREG_LCD_MISC, 0x00 },
|
||||
{ S1DREG_LCD_DISP_START0, 0x00 },
|
||||
{ S1DREG_LCD_DISP_START1, 0x00 },
|
||||
{ S1DREG_LCD_DISP_START2, 0x00 },
|
||||
{ S1DREG_LCD_MEM_OFF0, 0x90 },
|
||||
{ S1DREG_LCD_MEM_OFF1, 0x01 },
|
||||
{ S1DREG_LCD_PIX_PAN, 0x00 },
|
||||
{ S1DREG_LCD_DISP_FIFO_HTC, 0x00 },
|
||||
{ S1DREG_LCD_DISP_FIFO_LTC, 0x00 },
|
||||
{ S1DREG_CRT_DISP_HWIDTH, 0x63 },
|
||||
{ S1DREG_CRT_NDISP_HPER, 0x1f },
|
||||
{ S1DREG_CRT_HRTC_START, 0x04 },
|
||||
{ S1DREG_CRT_HRTC_PWIDTH, 0x8f },
|
||||
{ S1DREG_CRT_DISP_VHEIGHT0, 0x57 },
|
||||
{ S1DREG_CRT_DISP_VHEIGHT1, 0x02 },
|
||||
{ S1DREG_CRT_NDISP_VPER, 0x1b },
|
||||
{ S1DREG_CRT_VRTC_START, 0x00 },
|
||||
{ S1DREG_CRT_VRTC_PWIDTH, 0x83 },
|
||||
{ S1DREG_TV_OUT_CTL, 0x10 },
|
||||
{ S1DREG_CRT_DISP_MODE, 0x05 },
|
||||
{ S1DREG_CRT_DISP_START0, 0x00 },
|
||||
{ S1DREG_CRT_DISP_START1, 0x00 },
|
||||
{ S1DREG_CRT_DISP_START2, 0x00 },
|
||||
{ S1DREG_CRT_MEM_OFF0, 0x20 },
|
||||
{ S1DREG_CRT_MEM_OFF1, 0x03 },
|
||||
{ S1DREG_CRT_PIX_PAN, 0x00 },
|
||||
{ S1DREG_CRT_DISP_FIFO_HTC, 0x00 },
|
||||
{ S1DREG_CRT_DISP_FIFO_LTC, 0x00 },
|
||||
{ S1DREG_LCD_CUR_CTL, 0x00 },
|
||||
{ S1DREG_LCD_CUR_START, 0x01 },
|
||||
{ S1DREG_LCD_CUR_XPOS0, 0x00 },
|
||||
{ S1DREG_LCD_CUR_XPOS1, 0x00 },
|
||||
{ S1DREG_LCD_CUR_YPOS0, 0x00 },
|
||||
{ S1DREG_LCD_CUR_YPOS1, 0x00 },
|
||||
{ S1DREG_LCD_CUR_BCTL0, 0x00 },
|
||||
{ S1DREG_LCD_CUR_GCTL0, 0x00 },
|
||||
{ S1DREG_LCD_CUR_RCTL0, 0x00 },
|
||||
{ S1DREG_LCD_CUR_BCTL1, 0x1f },
|
||||
{ S1DREG_LCD_CUR_GCTL1, 0x3f },
|
||||
{ S1DREG_LCD_CUR_RCTL1, 0x1f },
|
||||
{ S1DREG_LCD_CUR_FIFO_HTC, 0x00 },
|
||||
{ S1DREG_CRT_CUR_CTL, 0x00 },
|
||||
{ S1DREG_CRT_CUR_START, 0x01 },
|
||||
{ S1DREG_CRT_CUR_XPOS0, 0x00 },
|
||||
{ S1DREG_CRT_CUR_XPOS1, 0x00 },
|
||||
{ S1DREG_CRT_CUR_YPOS0, 0x00 },
|
||||
{ S1DREG_CRT_CUR_YPOS1, 0x00 },
|
||||
{ S1DREG_CRT_CUR_BCTL0, 0x00 },
|
||||
{ S1DREG_CRT_CUR_GCTL0, 0x00 },
|
||||
{ S1DREG_CRT_CUR_RCTL0, 0x00 },
|
||||
{ S1DREG_CRT_CUR_BCTL1, 0x1f },
|
||||
{ S1DREG_CRT_CUR_GCTL1, 0x3f },
|
||||
{ S1DREG_CRT_CUR_RCTL1, 0x1f },
|
||||
{ S1DREG_CRT_CUR_FIFO_HTC, 0x00 },
|
||||
{ S1DREG_BBLT_CTL0, 0x00 },
|
||||
{ S1DREG_BBLT_CTL1, 0x00 },
|
||||
{ S1DREG_BBLT_CC_EXP, 0x00 },
|
||||
{ S1DREG_BBLT_OP, 0x00 },
|
||||
{ S1DREG_BBLT_SRC_START0, 0x00 },
|
||||
{ S1DREG_BBLT_SRC_START1, 0x00 },
|
||||
{ S1DREG_BBLT_SRC_START2, 0x00 },
|
||||
{ S1DREG_BBLT_DST_START0, 0x00 },
|
||||
{ S1DREG_BBLT_DST_START1, 0x00 },
|
||||
{ S1DREG_BBLT_DST_START2, 0x00 },
|
||||
{ S1DREG_BBLT_MEM_OFF0, 0x00 },
|
||||
{ S1DREG_BBLT_MEM_OFF1, 0x00 },
|
||||
{ S1DREG_BBLT_WIDTH0, 0x00 },
|
||||
{ S1DREG_BBLT_WIDTH1, 0x00 },
|
||||
{ S1DREG_BBLT_HEIGHT0, 0x00 },
|
||||
{ S1DREG_BBLT_HEIGHT1, 0x00 },
|
||||
{ S1DREG_BBLT_BGC0, 0x00 },
|
||||
{ S1DREG_BBLT_BGC1, 0x00 },
|
||||
{ S1DREG_BBLT_FGC0, 0x00 },
|
||||
{ S1DREG_BBLT_FGC1, 0x00 },
|
||||
{ S1DREG_LKUP_MODE, 0x00 },
|
||||
{ S1DREG_LKUP_ADDR, 0x00 },
|
||||
{ S1DREG_PS_CNF, 0x10 },
|
||||
{ S1DREG_PS_STATUS, 0x00 },
|
||||
{ S1DREG_CPU2MEM_WDOGT, 0x00 },
|
||||
{ S1DREG_COM_DISP_MODE, 0x02 },
|
||||
};
|
||||
|
||||
static struct s1d13xxxfb_pdata s1d13806_platform_data = {
|
||||
.initregs = s1d13806_initregs,
|
||||
.initregssize = ARRAY_SIZE(s1d13806_initregs),
|
||||
};
|
||||
|
||||
static struct resource s1d13806_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x07200000,
|
||||
.end = 0x07200000 + SZ_2M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 0x07000000,
|
||||
.end = 0x07000000 + SZ_2M - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device s1d13806_device = {
|
||||
.name = "s1d13806fb",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s1d13806_resources),
|
||||
.resource = s1d13806_resources,
|
||||
|
||||
.dev = {
|
||||
.platform_data = &s1d13806_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *microdev_devices[] __initdata = {
|
||||
&smc91x_device,
|
||||
&s1d13806_device,
|
||||
};
|
||||
|
||||
static int __init microdev_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(microdev_devices, ARRAY_SIZE(microdev_devices));
|
||||
}
|
||||
device_initcall(microdev_devices_setup);
|
||||
|
||||
/*
|
||||
* The Machine Vector
|
||||
*/
|
||||
static struct sh_machine_vector mv_sh4202_microdev __initmv = {
|
||||
.mv_name = "SH4-202 MicroDev",
|
||||
.mv_ioport_map = microdev_ioport_map,
|
||||
.mv_init_irq = init_microdev_irq,
|
||||
};
|
||||
@@ -1,42 +0,0 @@
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_CPU_SUBTYPE_SH4_202=y
|
||||
CONFIG_FLATMEM_MANUAL=y
|
||||
CONFIG_SH_SH4202_MICRODEV=y
|
||||
CONFIG_SH_DMA=y
|
||||
CONFIG_SH_DMA_API=y
|
||||
CONFIG_HEARTBEAT=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_CMDLINE_OVERWRITE=y
|
||||
CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/hda1"
|
||||
CONFIG_SUPERHYWAY=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_FW_LOADER is not set
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_SMC91X=y
|
||||
# CONFIG_INPUT is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
@@ -6,6 +6,5 @@
|
||||
obj-y += dma/ platform_early.o
|
||||
|
||||
obj-$(CONFIG_PCI) += pci/
|
||||
obj-$(CONFIG_SUPERHYWAY) += superhyway/
|
||||
obj-$(CONFIG_PUSH_SWITCH) += push-switch.o
|
||||
obj-$(CONFIG_HEARTBEAT) += heartbeat.o
|
||||
|
||||
@@ -1,7 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Makefile for the SuperHyway specific kernel interface routines under Linux.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += ops-sh4-202.o
|
||||
|
||||
@@ -1,168 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* arch/sh/drivers/superhyway/ops-sh4-202.c
|
||||
*
|
||||
* SuperHyway bus support for SH4-202
|
||||
*
|
||||
* Copyright (C) 2005 Paul Mundt
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/superhyway.h>
|
||||
#include <linux/string.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#define PHYS_EMI_CBLOCK P4SEGADDR(0x1ec00000)
|
||||
#define PHYS_EMI_DBLOCK P4SEGADDR(0x08000000)
|
||||
#define PHYS_FEMI_CBLOCK P4SEGADDR(0x1f800000)
|
||||
#define PHYS_FEMI_DBLOCK P4SEGADDR(0x00000000)
|
||||
|
||||
#define PHYS_EPBR_BLOCK P4SEGADDR(0x1de00000)
|
||||
#define PHYS_DMAC_BLOCK P4SEGADDR(0x1fa00000)
|
||||
#define PHYS_PBR_BLOCK P4SEGADDR(0x1fc00000)
|
||||
|
||||
static struct resource emi_resources[] = {
|
||||
[0] = {
|
||||
.start = PHYS_EMI_CBLOCK,
|
||||
.end = PHYS_EMI_CBLOCK + 0x00300000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = PHYS_EMI_DBLOCK,
|
||||
.end = PHYS_EMI_DBLOCK + 0x08000000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct superhyway_device emi_device = {
|
||||
.name = "emi",
|
||||
.num_resources = ARRAY_SIZE(emi_resources),
|
||||
.resource = emi_resources,
|
||||
};
|
||||
|
||||
static struct resource femi_resources[] = {
|
||||
[0] = {
|
||||
.start = PHYS_FEMI_CBLOCK,
|
||||
.end = PHYS_FEMI_CBLOCK + 0x00100000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = PHYS_FEMI_DBLOCK,
|
||||
.end = PHYS_FEMI_DBLOCK + 0x08000000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct superhyway_device femi_device = {
|
||||
.name = "femi",
|
||||
.num_resources = ARRAY_SIZE(femi_resources),
|
||||
.resource = femi_resources,
|
||||
};
|
||||
|
||||
static struct resource epbr_resources[] = {
|
||||
[0] = {
|
||||
.start = P4SEGADDR(0x1e7ffff8),
|
||||
.end = P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = PHYS_EPBR_BLOCK,
|
||||
.end = PHYS_EPBR_BLOCK + 0x00a00000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct superhyway_device epbr_device = {
|
||||
.name = "epbr",
|
||||
.num_resources = ARRAY_SIZE(epbr_resources),
|
||||
.resource = epbr_resources,
|
||||
};
|
||||
|
||||
static struct resource dmac_resource = {
|
||||
.start = PHYS_DMAC_BLOCK,
|
||||
.end = PHYS_DMAC_BLOCK + 0x00100000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
};
|
||||
|
||||
static struct superhyway_device dmac_device = {
|
||||
.name = "dmac",
|
||||
.num_resources = 1,
|
||||
.resource = &dmac_resource,
|
||||
};
|
||||
|
||||
static struct resource pbr_resources[] = {
|
||||
[0] = {
|
||||
.start = P4SEGADDR(0x1ffffff8),
|
||||
.end = P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1),
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = PHYS_PBR_BLOCK,
|
||||
.end = PHYS_PBR_BLOCK + 0x00400000 - (sizeof(u32) * 2) - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
};
|
||||
|
||||
static struct superhyway_device pbr_device = {
|
||||
.name = "pbr",
|
||||
.num_resources = ARRAY_SIZE(pbr_resources),
|
||||
.resource = pbr_resources,
|
||||
};
|
||||
|
||||
static struct superhyway_device *sh4202_devices[] __initdata = {
|
||||
&emi_device, &femi_device, &epbr_device, &dmac_device, &pbr_device,
|
||||
};
|
||||
|
||||
static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
|
||||
{
|
||||
u32 vcrh, vcrl;
|
||||
u64 tmp;
|
||||
|
||||
/*
|
||||
* XXX: Even though the SH4-202 Evaluation Device documentation
|
||||
* indicates that VCRL is mapped first with VCRH at a + 0x04
|
||||
* offset, the opposite seems to be true.
|
||||
*
|
||||
* Some modules (PBR and ePBR for instance) also appear to have
|
||||
* VCRL/VCRH flipped in the documentation, but on the SH4-202
|
||||
* itself it appears that these are all consistently mapped with
|
||||
* VCRH preceding VCRL.
|
||||
*
|
||||
* Do not trust the documentation, for it is evil.
|
||||
*/
|
||||
vcrh = __raw_readl(base);
|
||||
vcrl = __raw_readl(base + sizeof(u32));
|
||||
|
||||
tmp = ((u64)vcrh << 32) | vcrl;
|
||||
memcpy(vcr, &tmp, sizeof(u64));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
|
||||
{
|
||||
u64 tmp = *(u64 *)&vcr;
|
||||
|
||||
__raw_writel((tmp >> 32) & 0xffffffff, base);
|
||||
__raw_writel(tmp & 0xffffffff, base + sizeof(u32));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct superhyway_ops sh4202_superhyway_ops = {
|
||||
.read_vcr = sh4202_read_vcr,
|
||||
.write_vcr = sh4202_write_vcr,
|
||||
};
|
||||
|
||||
struct superhyway_bus superhyway_channels[] = {
|
||||
{ &sh4202_superhyway_ops, },
|
||||
{ 0, },
|
||||
};
|
||||
|
||||
int __init superhyway_scan_bus(struct superhyway_bus *bus)
|
||||
{
|
||||
return superhyway_add_devices(bus, sh4202_devices,
|
||||
ARRAY_SIZE(sh4202_devices));
|
||||
}
|
||||
|
||||
@@ -71,4 +71,13 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
|
||||
(unsigned long)_n_, sizeof(*(ptr))); \
|
||||
})
|
||||
|
||||
#include <asm-generic/cmpxchg-local.h>
|
||||
|
||||
#define arch_cmpxchg_local(ptr, o, n) ({ \
|
||||
(__typeof__(*ptr))__generic_cmpxchg_local((ptr), \
|
||||
(unsigned long)(o), \
|
||||
(unsigned long)(n), \
|
||||
sizeof(*(ptr))); \
|
||||
})
|
||||
|
||||
#endif /* __ASM_SH_CMPXCHG_H */
|
||||
|
||||
@@ -181,7 +181,7 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
|
||||
{ \
|
||||
volatile type *__addr; \
|
||||
\
|
||||
__addr = __ioport_map(port, sizeof(type)); \
|
||||
__addr = (void __iomem *)sh_io_port_base + port; \
|
||||
*__addr = val; \
|
||||
slow; \
|
||||
} \
|
||||
@@ -191,7 +191,7 @@ static inline type pfx##in##bwlq##p(unsigned long port) \
|
||||
volatile type *__addr; \
|
||||
type __val; \
|
||||
\
|
||||
__addr = __ioport_map(port, sizeof(type)); \
|
||||
__addr = (void __iomem *)sh_io_port_base + port; \
|
||||
__val = *__addr; \
|
||||
slow; \
|
||||
\
|
||||
|
||||
@@ -19,11 +19,6 @@ struct sh_machine_vector {
|
||||
int (*mv_irq_demux)(int irq);
|
||||
void (*mv_init_irq)(void);
|
||||
|
||||
#ifdef CONFIG_HAS_IOPORT_MAP
|
||||
void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
|
||||
void (*mv_ioport_unmap)(void __iomem *);
|
||||
#endif
|
||||
|
||||
int (*mv_clk_init)(void);
|
||||
int (*mv_mode_pins)(void);
|
||||
|
||||
|
||||
@@ -1,69 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0
|
||||
*
|
||||
* linux/include/asm-sh/microdev.h
|
||||
*
|
||||
* Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com)
|
||||
*
|
||||
* Definitions for the SuperH SH4-202 MicroDev board.
|
||||
*/
|
||||
#ifndef __ASM_SH_MICRODEV_H
|
||||
#define __ASM_SH_MICRODEV_H
|
||||
|
||||
extern void init_microdev_irq(void);
|
||||
extern void microdev_print_fpga_intc_status(void);
|
||||
|
||||
/*
|
||||
* The following are useful macros for manipulating the interrupt
|
||||
* controller (INTC) on the CPU-board FPGA. should be noted that there
|
||||
* is an INTC on the FPGA, and a separate INTC on the SH4-202 core -
|
||||
* these are two different things, both of which need to be prorammed to
|
||||
* correctly route - unfortunately, they have the same name and
|
||||
* abbreviations!
|
||||
*/
|
||||
#define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */
|
||||
#define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */
|
||||
#define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */
|
||||
#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interrupt mask to enable/disable INTC in CPU-board FPGA */
|
||||
#define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */
|
||||
#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */
|
||||
#define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */
|
||||
#define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */
|
||||
#define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */
|
||||
|
||||
|
||||
/*
|
||||
* The following are the IRQ numbers for the Linux Kernel for external
|
||||
* interrupts. i.e. the numbers seen by 'cat /proc/interrupt'.
|
||||
*/
|
||||
#define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
|
||||
#define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */
|
||||
#define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */
|
||||
#define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
|
||||
#define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */
|
||||
#define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
|
||||
#define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */
|
||||
#define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */
|
||||
|
||||
/*
|
||||
* The following are the IRQ numbers for the INTC on the FPGA for
|
||||
* external interrupts. i.e. the bits in the INTC registers in the
|
||||
* FPGA.
|
||||
*/
|
||||
#define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */
|
||||
#define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */
|
||||
#define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */
|
||||
#define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */
|
||||
#define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */
|
||||
#define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */
|
||||
#define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */
|
||||
#define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */
|
||||
|
||||
#define MICRODEV_IRQ_PCI_INTA 8
|
||||
#define MICRODEV_IRQ_PCI_INTB 9
|
||||
#define MICRODEV_IRQ_PCI_INTC 10
|
||||
#define MICRODEV_IRQ_PCI_INTD 11
|
||||
|
||||
#define __IO_PREFIX microdev
|
||||
#include <asm/io_generic.h>
|
||||
|
||||
#endif /* __ASM_SH_MICRODEV_H */
|
||||
@@ -23,15 +23,11 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7091) += setup-sh7750.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7751) += setup-sh7750.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += setup-sh7750.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o
|
||||
obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o
|
||||
|
||||
# Primary on-chip clocks (common)
|
||||
ifndef CONFIG_CPU_SH4A
|
||||
clock-$(CONFIG_CPU_SH4) := clock-sh4.o
|
||||
endif
|
||||
|
||||
# Additional clocks by subtype
|
||||
clock-$(CONFIG_CPU_SUBTYPE_SH4_202) += clock-sh4-202.o
|
||||
|
||||
obj-y += $(clock-y)
|
||||
obj-$(CONFIG_PERF_EVENTS) += $(perf-y)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user