mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
"This has been sitting in -next for a while with no objections and all
MIPS defconfigs except one are building fine; that one platform got
broken by another patch in your tree and I'm going to submit a patch
separately.
- a handful of fixes that didn't make 3.11
- a few bits of Octeon 3 support with more to come for a later
release
- platform enhancements for Octeon, ath79, Lantiq, Netlogic and
Ralink SOCs
- a GPIO driver for the Octeon
- some dusting off of the DECstation code
- the usual dose of cleanups"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (65 commits)
MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible code
MIPS: kexec: Fix random crashes while loading crashkernel
MIPS: kdump: Skip walking indirection page for crashkernels
MIPS: DECstation HRT calibration bug fixes
MIPS: Export copy_from_user_page() (needed by lustre)
MIPS: Add driver for the built-in PCI controller of the RT3883 SoC
MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000
MIPS: ralink: Add support for reset-controller API
MIPS: ralink: mt7620: Add cpu-feature-override header
MIPS: ralink: mt7620: Add spi clock definition
MIPS: ralink: mt7620: Add wdt clock definition
MIPS: ralink: mt7620: Improve clock frequency detection
MIPS: ralink: mt7620: This SoC has EHCI and OHCI hosts
MIPS: ralink: mt7620: Add verbose ram info
MIPS: ralink: Probe clocksources from OF
MIPS: ralink: Add support for systick timer found on newer ralink SoC
MIPS: ralink: Add support for periodic timer irq
MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards
MIPS: Netlogic: Add support for USB on XLP2xx
MIPS: Netlogic: XLP2xx update for I2C controller
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,190 @@
|
||||
* Mediatek/Ralink RT3883 PCI controller
|
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|
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1) Main node
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Required properties:
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- compatible: must be "ralink,rt3883-pci"
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- reg: specifies the physical base address of the controller and
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the length of the memory mapped region.
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- #address-cells: specifies the number of cells needed to encode an
|
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address. The value must be 1.
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||||
|
||||
- #size-cells: specifies the number of cells used to represent the size
|
||||
of an address. The value must be 1.
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|
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- ranges: specifies the translation between child address space and parent
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address space
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Optional properties:
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- status: indicates the operational status of the device.
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Value must be either "disabled" or "okay".
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2) Child nodes
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The main node must have two child nodes which describes the built-in
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interrupt controller and the PCI host bridge.
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a) Interrupt controller:
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Required properties:
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- interrupt-controller: identifies the node as an interrupt controller
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|
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0. As such, 'interrupt-map' nodes do not
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have to specify a parent unit address.
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- #interrupt-cells: specifies the number of cells needed to encode an
|
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interrupt source. The value must be 1.
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|
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- interrupt-parent: the phandle for the interrupt controller that
|
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services interrupts for this device.
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|
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- interrupts: specifies the interrupt source of the parent interrupt
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controller. The format of the interrupt specifier depends on the
|
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parent interrupt controller.
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b) PCI host bridge:
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|
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Required properties:
|
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- #address-cells: specifies the number of cells needed to encode an
|
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address. The value must be 0.
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- #size-cells: specifies the number of cells used to represent the size
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of an address. The value must be 2.
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|
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- device_type: must be "pci"
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- bus-range: PCI bus numbers covered
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- ranges: specifies the ranges for the PCI memory and I/O regions
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- interrupt-map-mask,
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- interrupt-map: standard PCI properties to define the mapping of the
|
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PCI interface to interrupt numbers.
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The PCI host bridge node migh have additional sub-nodes representing
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the onboard PCI devices/PCI slots. Each such sub-node must have the
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following mandatory properties:
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- reg: used only for interrupt mapping, so only the first four bytes
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are used to refer to the correct bus number and device number.
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- device_type: must be "pci"
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If a given sub-node represents a PCI bridge it must have following
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mandatory properties as well:
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- #address-cells: must be set to <3>
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- #size-cells: must set to <2>
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- #interrupt-cells: must be set to <1>
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- interrupt-map-mask,
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- interrupt-map: standard PCI properties to define the mapping of the
|
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PCI interface to interrupt numbers.
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|
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Besides the required properties the sub-nodes may have these optional
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properties:
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- status: indicates the operational status of the sub-node.
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Value must be either "disabled" or "okay".
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3) Example:
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a) SoC specific dtsi file:
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pci@10140000 {
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compatible = "ralink,rt3883-pci";
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reg = <0x10140000 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges; /* direct mapping */
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status = "disabled";
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pciintc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <4>;
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};
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host-bridge {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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bus-range = <0 255>;
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ranges = <
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0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
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0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
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>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 17 */
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0x8800 0 0 1 &pciintc 18
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0x8800 0 0 2 &pciintc 18
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0x8800 0 0 3 &pciintc 18
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0x8800 0 0 4 &pciintc 18
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/* IDSEL 18 */
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0x9000 0 0 1 &pciintc 19
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0x9000 0 0 2 &pciintc 19
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0x9000 0 0 3 &pciintc 19
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0x9000 0 0 4 &pciintc 19
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>;
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pci-bridge@1 {
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reg = <0x0800 0 0 0 0>;
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device_type = "pci";
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#interrupt-cells = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupt-map-mask = <0x0 0 0 0>;
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interrupt-map = <0x0 0 0 0 &pciintc 20>;
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status = "disabled";
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};
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pci-slot@17 {
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reg = <0x8800 0 0 0 0>;
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device_type = "pci";
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status = "disabled";
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};
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pci-slot@18 {
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reg = <0x9000 0 0 0 0>;
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device_type = "pci";
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status = "disabled";
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};
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};
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};
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b) Board specific dts file:
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pci@10140000 {
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status = "okay";
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host-bridge {
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pci-bridge@1 {
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status = "okay";
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};
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};
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};
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+5
-14
@@ -95,6 +95,7 @@ config ATH79
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select CSRC_R4K
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select DMA_NONCOHERENT
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select HAVE_CLK
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select CLKDEV_LOOKUP
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select IRQ_CPU
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select MIPS_MACHINE
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select SYS_HAS_CPU_MIPS32_R2
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@@ -131,7 +132,6 @@ config BCM63XX
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select IRQ_CPU
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
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select NR_CPUS_DEFAULT_2
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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@@ -445,6 +445,8 @@ config RALINK
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select SYS_HAS_EARLY_PRINTK
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select HAVE_MACH_CLKDEV
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select CLKDEV_LOOKUP
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select ARCH_HAS_RESET_CONTROLLER
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select RESET_CONTROLLER
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config SGI_IP22
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bool "SGI IP22 (Indy/Indigo2)"
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@@ -609,7 +611,6 @@ config SIBYTE_SWARM
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select BOOT_ELF32
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select DMA_COHERENT
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select HAVE_PATA_PLATFORM
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select NR_CPUS_DEFAULT_2
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select SIBYTE_SB1250
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_SB1
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@@ -623,7 +624,6 @@ config SIBYTE_LITTLESUR
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select BOOT_ELF32
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select DMA_COHERENT
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select HAVE_PATA_PLATFORM
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select NR_CPUS_DEFAULT_2
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select SIBYTE_SB1250
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_SB1
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@@ -635,7 +635,6 @@ config SIBYTE_SENTOSA
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bool "Sibyte BCM91250E-Sentosa"
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select BOOT_ELF32
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select DMA_COHERENT
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select NR_CPUS_DEFAULT_2
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select SIBYTE_SB1250
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select SWAP_IO_SPACE
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select SYS_HAS_CPU_SB1
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@@ -731,6 +730,7 @@ config CAVIUM_OCTEON_SOC
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select USB_ARCH_HAS_OHCI
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select USB_ARCH_HAS_EHCI
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select HOLES_IN_ZONE
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select ARCH_REQUIRE_GPIOLIB
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help
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This option supports all of the Octeon reference boards from Cavium
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Networks. It builds a kernel that dynamically determines the Octeon
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@@ -1860,7 +1860,6 @@ config MIPS_MT_SMP
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select MIPS_MT
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select NR_CPUS_DEFAULT_2
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select SMP
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select SYS_SUPPORTS_SCHED_SMT if SMP
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select SYS_SUPPORTS_SMP
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@@ -2171,12 +2170,6 @@ config SYS_SUPPORTS_MIPS_CMP
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config SYS_SUPPORTS_SMP
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bool
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config NR_CPUS_DEFAULT_1
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bool
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config NR_CPUS_DEFAULT_2
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bool
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config NR_CPUS_DEFAULT_4
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bool
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@@ -2194,10 +2187,8 @@ config NR_CPUS_DEFAULT_64
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config NR_CPUS
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int "Maximum number of CPUs (2-64)"
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range 1 64 if NR_CPUS_DEFAULT_1
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range 2 64
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depends on SMP
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default "1" if NR_CPUS_DEFAULT_1
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default "2" if NR_CPUS_DEFAULT_2
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default "4" if NR_CPUS_DEFAULT_4
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default "8" if NR_CPUS_DEFAULT_8
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default "16" if NR_CPUS_DEFAULT_16
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+29
-5
@@ -194,6 +194,8 @@ include $(srctree)/arch/mips/Kbuild.platforms
|
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ifdef CONFIG_PHYSICAL_START
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load-y = $(CONFIG_PHYSICAL_START)
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endif
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entry-y = 0x$(shell $(NM) vmlinux 2>/dev/null \
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| grep "\bkernel_entry\b" | cut -f1 -d \ )
|
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cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
|
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drivers-$(CONFIG_PCI) += arch/mips/pci/
|
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@@ -225,6 +227,9 @@ KBUILD_CFLAGS += $(cflags-y)
|
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KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
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KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
|
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bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
|
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VMLINUX_ENTRY_ADDRESS=$(entry-y)
|
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|
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LDFLAGS += -m $(ld-emul)
|
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|
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ifdef CONFIG_CC_STACKPROTECTOR
|
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@@ -254,9 +259,25 @@ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
|
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# suspend and hibernation support
|
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drivers-$(CONFIG_PM) += arch/mips/power/
|
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|
||||
# boot image targets (arch/mips/boot/)
|
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boot-y := vmlinux.bin
|
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boot-y += vmlinux.ecoff
|
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boot-y += vmlinux.srec
|
||||
ifeq ($(shell expr $(load-y) \< 0xffffffff80000000 2> /dev/null), 0)
|
||||
boot-y += uImage
|
||||
boot-y += uImage.gz
|
||||
endif
|
||||
|
||||
# compressed boot image targets (arch/mips/boot/compressed/)
|
||||
bootz-y := vmlinuz
|
||||
bootz-y += vmlinuz.bin
|
||||
bootz-y += vmlinuz.ecoff
|
||||
bootz-y += vmlinuz.srec
|
||||
|
||||
ifdef CONFIG_LASAT
|
||||
rom.bin rom.sw: vmlinux
|
||||
$(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
|
||||
$(Q)$(MAKE) $(build)=arch/mips/lasat/image \
|
||||
$(bootvars-y) $@
|
||||
endif
|
||||
|
||||
#
|
||||
@@ -280,13 +301,14 @@ vmlinux.64: vmlinux
|
||||
all: $(all-y)
|
||||
|
||||
# boot
|
||||
vmlinux.bin vmlinux.ecoff vmlinux.srec: $(vmlinux-32) FORCE
|
||||
$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) arch/mips/boot/$@
|
||||
$(boot-y): $(vmlinux-32) FORCE
|
||||
$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) \
|
||||
$(bootvars-y) arch/mips/boot/$@
|
||||
|
||||
# boot/compressed
|
||||
vmlinuz vmlinuz.bin vmlinuz.ecoff vmlinuz.srec: $(vmlinux-32) FORCE
|
||||
$(bootz-y): $(vmlinux-32) FORCE
|
||||
$(Q)$(MAKE) $(build)=arch/mips/boot/compressed \
|
||||
VMLINUX_LOAD_ADDRESS=$(load-y) 32bit-bfd=$(32bit-bfd) $@
|
||||
$(bootvars-y) 32bit-bfd=$(32bit-bfd) $@
|
||||
|
||||
|
||||
CLEAN_FILES += vmlinux.32 vmlinux.64
|
||||
@@ -323,6 +345,8 @@ define archhelp
|
||||
echo ' vmlinuz.ecoff - ECOFF zboot image'
|
||||
echo ' vmlinuz.bin - Raw binary zboot image'
|
||||
echo ' vmlinuz.srec - SREC zboot image'
|
||||
echo ' uImage - U-Boot image'
|
||||
echo ' uImage.gz - U-Boot image (gzip)'
|
||||
echo
|
||||
echo ' These will be default as appropriate for a configured platform.'
|
||||
endef
|
||||
|
||||
+151
-111
@@ -16,6 +16,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
|
||||
#include <asm/div64.h>
|
||||
|
||||
@@ -31,92 +32,132 @@ struct clk {
|
||||
unsigned long rate;
|
||||
};
|
||||
|
||||
static struct clk ath79_ref_clk;
|
||||
static struct clk ath79_cpu_clk;
|
||||
static struct clk ath79_ddr_clk;
|
||||
static struct clk ath79_ahb_clk;
|
||||
static struct clk ath79_wdt_clk;
|
||||
static struct clk ath79_uart_clk;
|
||||
static void __init ath79_add_sys_clkdev(const char *id, unsigned long rate)
|
||||
{
|
||||
struct clk *clk;
|
||||
int err;
|
||||
|
||||
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
||||
if (!clk)
|
||||
panic("failed to allocate %s clock structure", id);
|
||||
|
||||
clk->rate = rate;
|
||||
|
||||
err = clk_register_clkdev(clk, id, NULL);
|
||||
if (err)
|
||||
panic("unable to register %s clock device", id);
|
||||
}
|
||||
|
||||
static void __init ar71xx_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
unsigned long cpu_rate;
|
||||
unsigned long ddr_rate;
|
||||
unsigned long ahb_rate;
|
||||
u32 pll;
|
||||
u32 freq;
|
||||
u32 div;
|
||||
|
||||
ath79_ref_clk.rate = AR71XX_BASE_FREQ;
|
||||
ref_rate = AR71XX_BASE_FREQ;
|
||||
|
||||
pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
|
||||
|
||||
div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
|
||||
freq = div * ath79_ref_clk.rate;
|
||||
freq = div * ref_rate;
|
||||
|
||||
div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
|
||||
ath79_cpu_clk.rate = freq / div;
|
||||
cpu_rate = freq / div;
|
||||
|
||||
div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
|
||||
ath79_ddr_clk.rate = freq / div;
|
||||
ddr_rate = freq / div;
|
||||
|
||||
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
|
||||
ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
|
||||
ahb_rate = cpu_rate / div;
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ahb_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ahb_clk.rate;
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
}
|
||||
|
||||
static void __init ar724x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
unsigned long cpu_rate;
|
||||
unsigned long ddr_rate;
|
||||
unsigned long ahb_rate;
|
||||
u32 pll;
|
||||
u32 freq;
|
||||
u32 div;
|
||||
|
||||
ath79_ref_clk.rate = AR724X_BASE_FREQ;
|
||||
ref_rate = AR724X_BASE_FREQ;
|
||||
pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
|
||||
|
||||
div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
|
||||
freq = div * ath79_ref_clk.rate;
|
||||
freq = div * ref_rate;
|
||||
|
||||
div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
|
||||
freq *= div;
|
||||
|
||||
ath79_cpu_clk.rate = freq;
|
||||
cpu_rate = freq;
|
||||
|
||||
div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
|
||||
ath79_ddr_clk.rate = freq / div;
|
||||
ddr_rate = freq / div;
|
||||
|
||||
div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
|
||||
ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
|
||||
ahb_rate = cpu_rate / div;
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ahb_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ahb_clk.rate;
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
}
|
||||
|
||||
static void __init ar913x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
unsigned long cpu_rate;
|
||||
unsigned long ddr_rate;
|
||||
unsigned long ahb_rate;
|
||||
u32 pll;
|
||||
u32 freq;
|
||||
u32 div;
|
||||
|
||||
ath79_ref_clk.rate = AR913X_BASE_FREQ;
|
||||
ref_rate = AR913X_BASE_FREQ;
|
||||
pll = ath79_pll_rr(AR913X_PLL_REG_CPU_CONFIG);
|
||||
|
||||
div = ((pll >> AR913X_PLL_DIV_SHIFT) & AR913X_PLL_DIV_MASK);
|
||||
freq = div * ath79_ref_clk.rate;
|
||||
freq = div * ref_rate;
|
||||
|
||||
ath79_cpu_clk.rate = freq;
|
||||
cpu_rate = freq;
|
||||
|
||||
div = ((pll >> AR913X_DDR_DIV_SHIFT) & AR913X_DDR_DIV_MASK) + 1;
|
||||
ath79_ddr_clk.rate = freq / div;
|
||||
ddr_rate = freq / div;
|
||||
|
||||
div = (((pll >> AR913X_AHB_DIV_SHIFT) & AR913X_AHB_DIV_MASK) + 1) * 2;
|
||||
ath79_ahb_clk.rate = ath79_cpu_clk.rate / div;
|
||||
ahb_rate = cpu_rate / div;
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ahb_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ahb_clk.rate;
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ahb", NULL);
|
||||
}
|
||||
|
||||
static void __init ar933x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
unsigned long cpu_rate;
|
||||
unsigned long ddr_rate;
|
||||
unsigned long ahb_rate;
|
||||
u32 clock_ctrl;
|
||||
u32 cpu_config;
|
||||
u32 freq;
|
||||
@@ -124,21 +165,21 @@ static void __init ar933x_clocks_init(void)
|
||||
|
||||
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
|
||||
if (t & AR933X_BOOTSTRAP_REF_CLK_40)
|
||||
ath79_ref_clk.rate = (40 * 1000 * 1000);
|
||||
ref_rate = (40 * 1000 * 1000);
|
||||
else
|
||||
ath79_ref_clk.rate = (25 * 1000 * 1000);
|
||||
ref_rate = (25 * 1000 * 1000);
|
||||
|
||||
clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
|
||||
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
|
||||
ath79_cpu_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_ahb_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_ddr_clk.rate = ath79_ref_clk.rate;
|
||||
cpu_rate = ref_rate;
|
||||
ahb_rate = ref_rate;
|
||||
ddr_rate = ref_rate;
|
||||
} else {
|
||||
cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
|
||||
|
||||
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
|
||||
AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
|
||||
freq = ath79_ref_clk.rate / t;
|
||||
freq = ref_rate / t;
|
||||
|
||||
t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
|
||||
AR933X_PLL_CPU_CONFIG_NINT_MASK;
|
||||
@@ -153,19 +194,24 @@ static void __init ar933x_clocks_init(void)
|
||||
|
||||
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
|
||||
AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
|
||||
ath79_cpu_clk.rate = freq / t;
|
||||
cpu_rate = freq / t;
|
||||
|
||||
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
|
||||
AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
|
||||
ath79_ddr_clk.rate = freq / t;
|
||||
ddr_rate = freq / t;
|
||||
|
||||
t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
|
||||
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
|
||||
ath79_ahb_clk.rate = freq / t;
|
||||
ahb_rate = freq / t;
|
||||
}
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ahb", NULL);
|
||||
clk_add_alias("uart", NULL, "ref", NULL);
|
||||
}
|
||||
|
||||
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
|
||||
@@ -174,12 +220,12 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
|
||||
u64 t;
|
||||
u32 ret;
|
||||
|
||||
t = ath79_ref_clk.rate;
|
||||
t = ref;
|
||||
t *= nint;
|
||||
do_div(t, ref_div);
|
||||
ret = t;
|
||||
|
||||
t = ath79_ref_clk.rate;
|
||||
t = ref;
|
||||
t *= nfrac;
|
||||
do_div(t, ref_div * frac);
|
||||
ret += t;
|
||||
@@ -190,6 +236,10 @@ static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
|
||||
|
||||
static void __init ar934x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
unsigned long cpu_rate;
|
||||
unsigned long ddr_rate;
|
||||
unsigned long ahb_rate;
|
||||
u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
|
||||
u32 cpu_pll, ddr_pll;
|
||||
u32 bootstrap;
|
||||
@@ -199,9 +249,9 @@ static void __init ar934x_clocks_init(void)
|
||||
|
||||
bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
|
||||
if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
|
||||
ath79_ref_clk.rate = 40 * 1000 * 1000;
|
||||
ref_rate = 40 * 1000 * 1000;
|
||||
else
|
||||
ath79_ref_clk.rate = 25 * 1000 * 1000;
|
||||
ref_rate = 25 * 1000 * 1000;
|
||||
|
||||
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
|
||||
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
|
||||
@@ -227,7 +277,7 @@ static void __init ar934x_clocks_init(void)
|
||||
frac = 1 << 6;
|
||||
}
|
||||
|
||||
cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
|
||||
cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
|
||||
nfrac, frac, out_div);
|
||||
|
||||
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
|
||||
@@ -254,7 +304,7 @@ static void __init ar934x_clocks_init(void)
|
||||
frac = 1 << 10;
|
||||
}
|
||||
|
||||
ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
|
||||
ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
|
||||
nfrac, frac, out_div);
|
||||
|
||||
clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
|
||||
@@ -263,49 +313,58 @@ static void __init ar934x_clocks_init(void)
|
||||
AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
|
||||
ath79_cpu_clk.rate = ath79_ref_clk.rate;
|
||||
cpu_rate = ref_rate;
|
||||
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
||||
ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
|
||||
cpu_rate = cpu_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
|
||||
cpu_rate = ddr_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
||||
AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
|
||||
ath79_ddr_clk.rate = ath79_ref_clk.rate;
|
||||
ddr_rate = ref_rate;
|
||||
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
||||
ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
|
||||
ddr_rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
|
||||
ddr_rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
||||
AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
|
||||
ath79_ahb_clk.rate = ath79_ref_clk.rate;
|
||||
ahb_rate = ref_rate;
|
||||
else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
||||
ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
|
||||
ahb_rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
|
||||
ahb_rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ref", NULL);
|
||||
clk_add_alias("uart", NULL, "ref", NULL);
|
||||
|
||||
iounmap(dpll_base);
|
||||
}
|
||||
|
||||
static void __init qca955x_clocks_init(void)
|
||||
{
|
||||
unsigned long ref_rate;
|
||||
unsigned long cpu_rate;
|
||||
unsigned long ddr_rate;
|
||||
unsigned long ahb_rate;
|
||||
u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
|
||||
u32 cpu_pll, ddr_pll;
|
||||
u32 bootstrap;
|
||||
|
||||
bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
|
||||
if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
|
||||
ath79_ref_clk.rate = 40 * 1000 * 1000;
|
||||
ref_rate = 40 * 1000 * 1000;
|
||||
else
|
||||
ath79_ref_clk.rate = 25 * 1000 * 1000;
|
||||
ref_rate = 25 * 1000 * 1000;
|
||||
|
||||
pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
|
||||
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
|
||||
@@ -317,8 +376,8 @@ static void __init qca955x_clocks_init(void)
|
||||
frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
|
||||
QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
|
||||
|
||||
cpu_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||
cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
|
||||
cpu_pll = nint * ref_rate / ref_div;
|
||||
cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
|
||||
cpu_pll /= (1 << out_div);
|
||||
|
||||
pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
|
||||
@@ -331,8 +390,8 @@ static void __init qca955x_clocks_init(void)
|
||||
frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
|
||||
QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
|
||||
|
||||
ddr_pll = nint * ath79_ref_clk.rate / ref_div;
|
||||
ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
|
||||
ddr_pll = nint * ref_rate / ref_div;
|
||||
ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
|
||||
ddr_pll /= (1 << out_div);
|
||||
|
||||
clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
|
||||
@@ -341,34 +400,39 @@ static void __init qca955x_clocks_init(void)
|
||||
QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
|
||||
ath79_cpu_clk.rate = ath79_ref_clk.rate;
|
||||
cpu_rate = ref_rate;
|
||||
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
|
||||
ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
|
||||
cpu_rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
|
||||
cpu_rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
|
||||
QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
|
||||
ath79_ddr_clk.rate = ath79_ref_clk.rate;
|
||||
ddr_rate = ref_rate;
|
||||
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
|
||||
ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
|
||||
ddr_rate = cpu_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
|
||||
ddr_rate = ddr_pll / (postdiv + 1);
|
||||
|
||||
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
|
||||
QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
|
||||
|
||||
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
|
||||
ath79_ahb_clk.rate = ath79_ref_clk.rate;
|
||||
ahb_rate = ref_rate;
|
||||
else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
|
||||
ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
|
||||
ahb_rate = ddr_pll / (postdiv + 1);
|
||||
else
|
||||
ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
|
||||
ahb_rate = cpu_pll / (postdiv + 1);
|
||||
|
||||
ath79_wdt_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_uart_clk.rate = ath79_ref_clk.rate;
|
||||
ath79_add_sys_clkdev("ref", ref_rate);
|
||||
ath79_add_sys_clkdev("cpu", cpu_rate);
|
||||
ath79_add_sys_clkdev("ddr", ddr_rate);
|
||||
ath79_add_sys_clkdev("ahb", ahb_rate);
|
||||
|
||||
clk_add_alias("wdt", NULL, "ref", NULL);
|
||||
clk_add_alias("uart", NULL, "ref", NULL);
|
||||
}
|
||||
|
||||
void __init ath79_clocks_init(void)
|
||||
@@ -387,46 +451,27 @@ void __init ath79_clocks_init(void)
|
||||
qca955x_clocks_init();
|
||||
else
|
||||
BUG();
|
||||
}
|
||||
|
||||
pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, "
|
||||
"Ref:%lu.%03luMHz",
|
||||
ath79_cpu_clk.rate / 1000000,
|
||||
(ath79_cpu_clk.rate / 1000) % 1000,
|
||||
ath79_ddr_clk.rate / 1000000,
|
||||
(ath79_ddr_clk.rate / 1000) % 1000,
|
||||
ath79_ahb_clk.rate / 1000000,
|
||||
(ath79_ahb_clk.rate / 1000) % 1000,
|
||||
ath79_ref_clk.rate / 1000000,
|
||||
(ath79_ref_clk.rate / 1000) % 1000);
|
||||
unsigned long __init
|
||||
ath79_get_sys_clk_rate(const char *id)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned long rate;
|
||||
|
||||
clk = clk_get(NULL, id);
|
||||
if (IS_ERR(clk))
|
||||
panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
|
||||
|
||||
rate = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
/*
|
||||
* Linux clock API
|
||||
*/
|
||||
struct clk *clk_get(struct device *dev, const char *id)
|
||||
{
|
||||
if (!strcmp(id, "ref"))
|
||||
return &ath79_ref_clk;
|
||||
|
||||
if (!strcmp(id, "cpu"))
|
||||
return &ath79_cpu_clk;
|
||||
|
||||
if (!strcmp(id, "ddr"))
|
||||
return &ath79_ddr_clk;
|
||||
|
||||
if (!strcmp(id, "ahb"))
|
||||
return &ath79_ahb_clk;
|
||||
|
||||
if (!strcmp(id, "wdt"))
|
||||
return &ath79_wdt_clk;
|
||||
|
||||
if (!strcmp(id, "uart"))
|
||||
return &ath79_uart_clk;
|
||||
|
||||
return ERR_PTR(-ENOENT);
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get);
|
||||
|
||||
int clk_enable(struct clk *clk)
|
||||
{
|
||||
return 0;
|
||||
@@ -443,8 +488,3 @@ unsigned long clk_get_rate(struct clk *clk)
|
||||
return clk->rate;
|
||||
}
|
||||
EXPORT_SYMBOL(clk_get_rate);
|
||||
|
||||
void clk_put(struct clk *clk)
|
||||
{
|
||||
}
|
||||
EXPORT_SYMBOL(clk_put);
|
||||
|
||||
@@ -21,6 +21,8 @@
|
||||
#define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
|
||||
|
||||
void ath79_clocks_init(void);
|
||||
unsigned long ath79_get_sys_clk_rate(const char *id);
|
||||
|
||||
void ath79_ddr_wb_flush(unsigned int reg);
|
||||
|
||||
void ath79_gpio_function_enable(u32 mask);
|
||||
|
||||
@@ -81,21 +81,19 @@ static struct platform_device ar933x_uart_device = {
|
||||
|
||||
void __init ath79_register_uart(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned long uart_clk_rate;
|
||||
|
||||
clk = clk_get(NULL, "uart");
|
||||
if (IS_ERR(clk))
|
||||
panic("unable to get UART clock, err=%ld", PTR_ERR(clk));
|
||||
uart_clk_rate = ath79_get_sys_clk_rate("uart");
|
||||
|
||||
if (soc_is_ar71xx() ||
|
||||
soc_is_ar724x() ||
|
||||
soc_is_ar913x() ||
|
||||
soc_is_ar934x() ||
|
||||
soc_is_qca955x()) {
|
||||
ath79_uart_data[0].uartclk = clk_get_rate(clk);
|
||||
ath79_uart_data[0].uartclk = uart_clk_rate;
|
||||
platform_device_register(&ath79_uart_device);
|
||||
} else if (soc_is_ar933x()) {
|
||||
ar933x_uart_data.uartclk = clk_get_rate(clk);
|
||||
ar933x_uart_data.uartclk = uart_clk_rate;
|
||||
platform_device_register(&ar933x_uart_device);
|
||||
} else {
|
||||
BUG();
|
||||
|
||||
+17
-6
@@ -200,7 +200,6 @@ void __init plat_mem_setup(void)
|
||||
|
||||
ath79_detect_sys_type();
|
||||
detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
|
||||
ath79_clocks_init();
|
||||
|
||||
_machine_restart = ath79_restart;
|
||||
_machine_halt = ath79_halt;
|
||||
@@ -209,13 +208,25 @@ void __init plat_mem_setup(void)
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
unsigned long cpu_clk_rate;
|
||||
unsigned long ahb_clk_rate;
|
||||
unsigned long ddr_clk_rate;
|
||||
unsigned long ref_clk_rate;
|
||||
|
||||
clk = clk_get(NULL, "cpu");
|
||||
if (IS_ERR(clk))
|
||||
panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
|
||||
ath79_clocks_init();
|
||||
|
||||
mips_hpt_frequency = clk_get_rate(clk) / 2;
|
||||
cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
|
||||
ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
|
||||
ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
|
||||
ref_clk_rate = ath79_get_sys_clk_rate("ref");
|
||||
|
||||
pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz",
|
||||
cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
|
||||
ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
|
||||
ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
|
||||
ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
|
||||
|
||||
mips_hpt_frequency = cpu_clk_rate / 2;
|
||||
}
|
||||
|
||||
static int __init ath79_setup(void)
|
||||
|
||||
@@ -4,3 +4,4 @@ vmlinux.*
|
||||
zImage
|
||||
zImage.tmp
|
||||
calc_vmlinuz_load_addr
|
||||
uImage
|
||||
|
||||
@@ -40,3 +40,18 @@ quiet_cmd_srec = OBJCOPY $@
|
||||
cmd_srec = $(OBJCOPY) -S -O srec $(strip-flags) $(VMLINUX) $@
|
||||
$(obj)/vmlinux.srec: $(VMLINUX) FORCE
|
||||
$(call if_changed,srec)
|
||||
|
||||
UIMAGE_LOADADDR = $(VMLINUX_LOAD_ADDRESS)
|
||||
UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS)
|
||||
|
||||
$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,gzip)
|
||||
|
||||
targets += uImage.gz
|
||||
$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz FORCE
|
||||
$(call if_changed,uimage,gzip)
|
||||
|
||||
targets += uImage
|
||||
$(obj)/uImage: $(obj)/uImage.gz FORCE
|
||||
@ln -sf $(notdir $<) $@
|
||||
@echo ' Image $@ is ready'
|
||||
|
||||
@@ -25,7 +25,7 @@ KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
|
||||
|
||||
KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
|
||||
-DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
|
||||
-DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
|
||||
-DKERNEL_ENTRY=$(VMLINUX_ENTRY_ADDRESS)
|
||||
|
||||
targets := head.o decompress.o dbg.o uart-16550.o uart-alchemy.o
|
||||
|
||||
|
||||
+1
@@ -0,0 +1 @@
|
||||
../../../../../include/dt-bindings
|
||||
@@ -1776,7 +1776,7 @@ asmlinkage void plat_irq_dispatch(void)
|
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
|
||||
void fixup_irqs(void)
|
||||
void octeon_fixup_irqs(void)
|
||||
{
|
||||
irq_cpu_offline();
|
||||
}
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
* written by Ralf Baechle <ralf@linux-mips.org>
|
||||
*/
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/console.h>
|
||||
@@ -1139,3 +1140,30 @@ static int __init edac_devinit(void)
|
||||
return err;
|
||||
}
|
||||
device_initcall(edac_devinit);
|
||||
|
||||
static void __initdata *octeon_dummy_iospace;
|
||||
|
||||
static int __init octeon_no_pci_init(void)
|
||||
{
|
||||
/*
|
||||
* Initially assume there is no PCI. The PCI/PCIe platform code will
|
||||
* later re-initialize these to correct values if they are present.
|
||||
*/
|
||||
octeon_dummy_iospace = vzalloc(IO_SPACE_LIMIT);
|
||||
set_io_port_base((unsigned long)octeon_dummy_iospace);
|
||||
ioport_resource.start = MAX_RESOURCE;
|
||||
ioport_resource.end = 0;
|
||||
return 0;
|
||||
}
|
||||
core_initcall(octeon_no_pci_init);
|
||||
|
||||
static int __init octeon_no_pci_release(void)
|
||||
{
|
||||
/*
|
||||
* Release the allocated memory if a real IO space is there.
|
||||
*/
|
||||
if ((unsigned long)octeon_dummy_iospace != mips_io_port_base)
|
||||
vfree(octeon_dummy_iospace);
|
||||
return 0;
|
||||
}
|
||||
late_initcall(octeon_no_pci_release);
|
||||
|
||||
@@ -255,8 +255,6 @@ static void octeon_cpus_done(void)
|
||||
/* State of each CPU. */
|
||||
DEFINE_PER_CPU(int, cpu_state);
|
||||
|
||||
extern void fixup_irqs(void);
|
||||
|
||||
static int octeon_cpu_disable(void)
|
||||
{
|
||||
unsigned int cpu = smp_processor_id();
|
||||
@@ -267,7 +265,7 @@ static int octeon_cpu_disable(void)
|
||||
set_cpu_online(cpu, false);
|
||||
cpu_clear(cpu, cpu_callin_map);
|
||||
local_irq_disable();
|
||||
fixup_irqs();
|
||||
octeon_fixup_irqs();
|
||||
local_irq_enable();
|
||||
|
||||
flush_cache_all();
|
||||
|
||||
@@ -0,0 +1,159 @@
|
||||
CONFIG_LANTIQ=y
|
||||
CONFIG_XRX200_PHY_FW=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
# CONFIG_COMPACTION is not set
|
||||
# CONFIG_CROSS_MEMORY_ATTACH is not set
|
||||
CONFIG_HZ_100=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_RD_GZIP is not set
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
# CONFIG_AIO is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
# CONFIG_IOSCHED_CFQ is not set
|
||||
# CONFIG_COREDUMP is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_ADVANCED_ROUTER=y
|
||||
CONFIG_IP_MULTIPLE_TABLES=y
|
||||
CONFIG_IP_ROUTE_MULTIPATH=y
|
||||
CONFIG_IP_ROUTE_VERBOSE=y
|
||||
CONFIG_IP_MROUTE=y
|
||||
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
|
||||
CONFIG_ARPD=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
CONFIG_TCP_CONG_ADVANCED=y
|
||||
# CONFIG_TCP_CONG_BIC is not set
|
||||
# CONFIG_TCP_CONG_WESTWOOD is not set
|
||||
# CONFIG_TCP_CONG_HTCP is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_BRIDGE_NETFILTER is not set
|
||||
CONFIG_NF_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_FTP=m
|
||||
CONFIG_NF_CONNTRACK_IRC=m
|
||||
CONFIG_NETFILTER_XT_TARGET_CT=m
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=m
|
||||
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
|
||||
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MAC=m
|
||||
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
|
||||
CONFIG_NETFILTER_XT_MATCH_STATE=m
|
||||
CONFIG_NF_CONNTRACK_IPV4=m
|
||||
# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_IP_NF_RAW=m
|
||||
CONFIG_BRIDGE=y
|
||||
# CONFIG_BRIDGE_IGMP_SNOOPING is not set
|
||||
CONFIG_VLAN_8021Q=y
|
||||
CONFIG_NET_SCHED=y
|
||||
CONFIG_HAMRADIO=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
# CONFIG_FIRMWARE_IN_KERNEL is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_COMPLEX_MAPPINGS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_LANTIQ=y
|
||||
CONFIG_EEPROM_93CX6=m
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_LANTIQ_ETOP=y
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PPP=m
|
||||
CONFIG_PPP_FILTER=y
|
||||
CONFIG_PPP_MULTILINK=y
|
||||
CONFIG_PPPOE=m
|
||||
CONFIG_PPP_ASYNC=m
|
||||
CONFIG_ISDN=y
|
||||
CONFIG_INPUT=m
|
||||
CONFIG_INPUT_POLLDEV=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_MISC=y
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_VT is not set
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_GPIO_MM_LANTIQ=y
|
||||
CONFIG_GPIO_STP_XWAY=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_WATCHDOG=y
|
||||
# CONFIG_HID is not set
|
||||
# CONFIG_USB_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_STORAGE_DEBUG=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_STAGING=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_DNOTIFY is not set
|
||||
# CONFIG_PROC_PAGE_MONITOR is not set
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_XATTR=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_SUMMARY=y
|
||||
CONFIG_JFFS2_FS_XATTR=y
|
||||
# CONFIG_JFFS2_FS_POSIX_ACL is not set
|
||||
# CONFIG_JFFS2_FS_SECURITY is not set
|
||||
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
|
||||
# CONFIG_JFFS2_ZLIB is not set
|
||||
CONFIG_SQUASHFS=y
|
||||
# CONFIG_SQUASHFS_ZLIB is not set
|
||||
CONFIG_SQUASHFS_XZ=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_STRIP_ASM_SYMS=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CRYPTO_MANAGER=m
|
||||
CONFIG_CRYPTO_ARC4=m
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_CRC32_SARWATE=y
|
||||
CONFIG_AVERAGE=y
|
||||
@@ -126,12 +126,13 @@ int rtc_mips_set_mmss(unsigned long nowtime)
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
u32 start, end;
|
||||
int i = HZ / 10;
|
||||
int i = HZ / 8;
|
||||
|
||||
/* Set up the rate of periodic DS1287 interrupts. */
|
||||
ds1287_set_base_clock(HZ);
|
||||
|
||||
if (cpu_has_counter) {
|
||||
ds1287_timer_state();
|
||||
while (!ds1287_timer_state())
|
||||
;
|
||||
|
||||
@@ -143,7 +144,7 @@ void __init plat_time_init(void)
|
||||
|
||||
end = read_c0_count();
|
||||
|
||||
mips_hpt_frequency = (end - start) * 10;
|
||||
mips_hpt_frequency = (end - start) * 8;
|
||||
printk(KERN_INFO "MIPS counter frequency %dHz\n",
|
||||
mips_hpt_frequency);
|
||||
} else if (IOASIC)
|
||||
|
||||
@@ -1,2 +1,15 @@
|
||||
# MIPS headers
|
||||
generic-y += cputime.h
|
||||
generic-y += current.h
|
||||
generic-y += emergency-restart.h
|
||||
generic-y += local64.h
|
||||
generic-y += mutex.h
|
||||
generic-y += parport.h
|
||||
generic-y += percpu.h
|
||||
generic-y += scatterlist.h
|
||||
generic-y += sections.h
|
||||
generic-y += segment.h
|
||||
generic-y += serial.h
|
||||
generic-y += trace_clock.h
|
||||
generic-y += ucontext.h
|
||||
generic-y += xor.h
|
||||
|
||||
@@ -65,44 +65,33 @@ static inline unsigned long bmips_read_zscm_reg(unsigned int offset)
|
||||
{
|
||||
unsigned long ret;
|
||||
|
||||
__asm__ __volatile__(
|
||||
".set push\n"
|
||||
".set noreorder\n"
|
||||
"cache %1, 0(%2)\n"
|
||||
"sync\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"mfc0 %0, $28, 3\n"
|
||||
"_ssnop\n"
|
||||
".set pop\n"
|
||||
: "=&r" (ret)
|
||||
: "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
|
||||
: "memory");
|
||||
barrier();
|
||||
cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
|
||||
__sync();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
ret = read_c0_ddatalo();
|
||||
_ssnop();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void bmips_write_zscm_reg(unsigned int offset, unsigned long data)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
".set push\n"
|
||||
".set noreorder\n"
|
||||
"mtc0 %0, $28, 3\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"cache %1, 0(%2)\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
"_ssnop\n"
|
||||
: /* no outputs */
|
||||
: "r" (data),
|
||||
"i" (Index_Store_Tag_S), "r" (ZSCM_REG_BASE + offset)
|
||||
: "memory");
|
||||
write_c0_ddatalo(data);
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
_ssnop();
|
||||
barrier();
|
||||
}
|
||||
|
||||
#endif /* !defined(__ASSEMBLY__) */
|
||||
|
||||
@@ -141,6 +141,9 @@
|
||||
#define PRID_IMP_CAVIUM_CN68XX 0x9100
|
||||
#define PRID_IMP_CAVIUM_CN66XX 0x9200
|
||||
#define PRID_IMP_CAVIUM_CN61XX 0x9300
|
||||
#define PRID_IMP_CAVIUM_CNF71XX 0x9400
|
||||
#define PRID_IMP_CAVIUM_CN78XX 0x9500
|
||||
#define PRID_IMP_CAVIUM_CN70XX 0x9600
|
||||
|
||||
/*
|
||||
* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
|
||||
@@ -176,6 +179,7 @@
|
||||
|
||||
#define PRID_IMP_NETLOGIC_XLP8XX 0x1000
|
||||
#define PRID_IMP_NETLOGIC_XLP3XX 0x1100
|
||||
#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
|
||||
|
||||
/*
|
||||
* Definitions for 7:0 on legacy processors
|
||||
@@ -272,7 +276,7 @@ enum cpu_type_enum {
|
||||
*/
|
||||
CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
|
||||
CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
|
||||
CPU_XLR, CPU_XLP,
|
||||
CPU_CAVIUM_OCTEON3, CPU_XLR, CPU_XLP,
|
||||
|
||||
CPU_LAST
|
||||
};
|
||||
|
||||
@@ -1,6 +0,0 @@
|
||||
#ifndef __MIPS_CPUTIME_H
|
||||
#define __MIPS_CPUTIME_H
|
||||
|
||||
#include <asm-generic/cputime.h>
|
||||
|
||||
#endif /* __MIPS_CPUTIME_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user