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Merge tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "Core changes:

   - Add new generic callbacks to populate per-pin pin controllers
     creating groups and functions from the device tree building out
     pinctrl_generic_to_map() and move the Spacemit driver over to use
     this

   - Generic board-level pin control driver using the mux framework

  New pin controller drivers:

   - Amlogic (meson) A9 SoC

   - Aspeed AST2700 SoC0 and SoC1

   - nVidia Tegra264 and Tegra238

   - Qualcomm Nord TLMM, Shikra TLMM, SM6350 LPASS LPI, and IPQ9650 TLMM

   - Renesas RZ/G3L SoC

   - UltraRISC DP1000

  Improvements:

   - Handle pull up/pull down properly in the Renesas RZG2L driver

   - Fix up nVidia Tegra 234 DT bindings

   - Fix up pin definitions in the Qualcomm Eliza driver

   - Qualcomm PM8010 GPIO support in the PM8010

   - Qualcomm SM6115 EGPIO support in the SM6115

   - Switch Qualcomm LPASS LPI drivers to use runtime PM for power
     management

   - Clean up the Qualcomm Kconfig business a bit to include the
     necessary drivers for each subarch

   - Fix output glitch in the Amlogic (meson) A4 pin controller

   - Move the Airoha driver from the Mediatek directory to its own
     directory. It is too different from other Mediatek hardware

   - A slew of fixes to the Airoha AN7581 and AN7583 drivers"

* tag 'pinctrl-v7.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (151 commits)
  pinctrl: Export pinctrl_get_group_selector()
  pinctrl: Match DT helper types
  pinctrl: qcom: Register functions before enabling pinctrl
  pinctrl: meson: amlogic-a4: use nolock get range
  pinctrl: ultrarisc: Add UltraRISC DP1000 pinctrl driver
  dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller
  pinctrl: qcom: Remove unused macro definitions
  pinctrl: tegra: PINCTRL_TEGRA264 should depend on ARCH_TEGRA
  pinctrl: tegra: PINCTRL_TEGRA238 should depend on ARCH_TEGRA
  pinctrl: tegra238: add missing AON pin groups
  dt-bindings: pinctrl: tegra238: add missing AON pin groups
  pinctrl: airoha: an7583: remove undefined groups from pcm_spi pin function
  pinctrl: airoha: an7583: fix phy1_led1 pin function
  pinctrl: airoha: an7583: add missed gpio22 pin group
  pinctrl: airoha: an7583: fix gpio21 pin group
  pinctrl: airoha: fix pwm pin function for an7581 and an7583
  pinctrl: airoha: an7583: fix incorrect led mapping in phy4_led1 pin function
  pinctrl: airoha: an7581: fix incorrect led mapping in phy4_led1 pin function
  pinctrl: airoha: an7583: fix misprint in gpio19 pinconf
  pinctrl: airoha: an7581: fix misprint in gpio19 pinconf
  ...
This commit is contained in:
Linus Torvalds
2026-06-18 15:03:21 -07:00
parent 7c6742507c 8b2c4f88c6
commit 53c7db5c19
180 changed files with 16417 additions and 1100 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml
+4 -4
View File
@@ -34,7 +34,7 @@ properties:
interrupts:
minItems: 2
maxItems: 10
maxItems: 11
description:
One interrupt per external interrupt bank supported on the
controller, sorted by bank number ascending order.
@@ -61,7 +61,7 @@ properties:
bank found in the controller
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 10
maxItems: 11
patternProperties:
# It's pretty scary, but the basic idea is that:
@@ -130,8 +130,8 @@ allOf:
then:
properties:
interrupts:
minItems: 10
maxItems: 10
minItems: 11
maxItems: 11
- if:
properties:
Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml
+1
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@@ -17,6 +17,7 @@ properties:
oneOf:
- enum:
- amlogic,pinctrl-a4
- amlogic,pinctrl-a9
- amlogic,pinctrl-s6
- amlogic,pinctrl-s7
- items:
Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml
+188
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@@ -0,0 +1,188 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED AST2700 SoC0 Pin Controller
maintainers:
- Billy Tsai <billy_tsai@aspeedtech.com>
description: >
The AST2700 features a dual-SoC architecture with two interconnected SoCs,
each having its own System Control Unit (SCU) for independent pin control.
This pin controller manages the pin multiplexing for SoC0.
The SoC0 pin controller manages pin functions including eMMC, VGA DDC,
dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces.
properties:
compatible:
const: aspeed,ast2700-soc0-pinctrl
reg:
maxItems: 1
patternProperties:
'-state$':
description: |
Pin control state.
If 'function' is present, the node describes a pinmux state and must
specify 'groups'.
For pin configuration, exactly one of 'groups' or 'pins' must be
specified in each state node. Group-level configuration applies to all
pins in the group. Pin-level configuration may be supplied in a
separate state node for individual pins; when both group-level and
pin-level configuration apply to the same pin, the pin-level
configuration takes precedence.
type: object
allOf:
- $ref: pinmux-node.yaml#
- $ref: pincfg-node.yaml#
- if:
required:
- function
then:
required:
- groups
- oneOf:
- required:
- groups
- required:
- pins
additionalProperties: false
properties:
function:
enum:
- EMMC
- JTAGDDR
- JTAGM0
- JTAGPCIEA
- JTAGPCIEB
- JTAGPSP
- JTAGSSP
- JTAGTSP
- JTAGUSB3A
- JTAGUSB3B
- PCIERC0PERST
- PCIERC1PERST
- TSPRSTN
- UFSCLKI
- USB2AD0
- USB2AD1
- USB2AH
- USB2AHP
- USB2AHPD0
- USB2AXH
- USB2AXH2B
- USB2AXHD1
- USB2AXHP
- USB2AXHP2B
- USB2AXHPD1
- USB2BD0
- USB2BD1
- USB2BH
- USB2BHP
- USB2BHPD0
- USB2BXH
- USB2BXH2A
- USB2BXHD1
- USB2BXHP
- USB2BXHP2A
- USB2BXHPD1
- USB3AXH
- USB3AXH2B
- USB3AXHD
- USB3AXHP
- USB3AXHP2B
- USB3AXHPD
- USB3BXH
- USB3BXH2A
- USB3BXHD
- USB3BXHP
- USB3BXHP2A
- USB3BXHPD
- VB
- VGADDC
groups:
enum:
- EMMCCDN
- EMMCG1
- EMMCG4
- EMMCG8
- EMMCWPN
- JTAG0
- PCIERC0PERST
- PCIERC1PERST
- TSPRSTN
- UFSCLKI
- USB2A
- USB2AAP
- USB2ABP
- USB2ADAP
- USB2AH
- USB2AHAP
- USB2B
- USB2BAP
- USB2BBP
- USB2BDBP
- USB2BH
- USB2BHBP
- USB3A
- USB3AAP
- USB3ABP
- USB3B
- USB3BAP
- USB3BBP
- VB0
- VB1
- VGADDC
pins:
enum:
- AB13
- AB14
- AC13
- AC14
- AD13
- AD14
- AE13
- AE14
- AE15
- AF13
- AF14
- AF15
drive-strength:
enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41]
bias-disable: true
bias-pull-up: true
bias-pull-down: true
required:
- compatible
- reg
allOf:
- $ref: pinctrl.yaml#
additionalProperties: false
examples:
- |
pinctrl@400 {
compatible = "aspeed,ast2700-soc0-pinctrl";
reg = <0x400 0x318>;
emmc-state {
function = "EMMC";
groups = "EMMCG1";
};
};
Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml
+760
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File diff suppressed because it is too large Load Diff
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
+1
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@@ -17,6 +17,7 @@ properties:
enum:
- mediatek,mt2701-pinctrl
- mediatek,mt2712-pinctrl
- mediatek,mt6392-pinctrl
- mediatek,mt6397-pinctrl
- mediatek,mt7623-pinctrl
- mediatek,mt8127-pinctrl
Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml
+8
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@@ -152,6 +152,14 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
slew-rate:
description: |
Set the slew rate. Valid arguments are described as below:
0: Normal slew rate
1: Slower slew
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
required:
- pinmux
Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml
+5
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@@ -67,6 +67,11 @@ properties:
# PIN CONFIGURATION NODES
patternProperties:
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
'-pins$':
type: object
additionalProperties: false
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml
+5 -1
View File
@@ -58,7 +58,11 @@ patternProperties:
drive_soc_gpio27_pee6, drive_ao_retention_n_pee2,
drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ]
unevaluatedProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml
+5 -1
View File
@@ -115,7 +115,11 @@ patternProperties:
drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
drive_sdmmc1_dat0_pj2 ]
unevaluatedProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml
+102
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@@ -0,0 +1,102 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra238 AON Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra238-pinmux-aon
reg:
maxItems: 1
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra238-pinmux-common.yaml
properties:
nvidia,pins:
items:
enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
soc_gpio25_paa6, soc_gpio26_paa7,
hdmi_cec_pbb0,
spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
uart3_rx_pcc6, gen2_i2c_scl_pcc7,
gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1,
gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4,
dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7,
pwm3_pee0, pwm7_pee1, soc_gpio49_pee2,
soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5,
soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2,
soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5,
soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0,
soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3,
uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6,
uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1,
uart5_cts_phh2, soc_gpio86_phh3,
# drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH)
drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1,
drive_vcomp_alert_paa2, drive_pwm1_paa3,
drive_batt_oc_paa4, drive_soc_gpio04_paa5,
drive_soc_gpio25_paa6, drive_soc_gpio26_paa7,
drive_hdmi_cec_pbb0,
drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3,
drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5,
drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7,
drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1,
drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3,
drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5,
drive_soc_gpio19_pdd6, drive_pwm2_pdd7,
drive_pwm3_pee0, drive_pwm7_pee1,
drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,
drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,
drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,
drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,
drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,
drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,
drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,
drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0,
drive_uart5_tx_pgg7, drive_uart5_rx_phh0,
drive_uart2_tx_pgg2, drive_uart2_rx_pgg3,
drive_uart2_cts_pgg5, drive_uart2_rts_pgg4,
drive_uart5_cts_phh2, drive_uart5_rts_phh1 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@c300000 {
compatible = "nvidia,tegra238-pinmux-aon";
reg = <0x0c300000 0x4000>;
pinctrl-names = "cec";
pinctrl-0 = <&cec_state>;
cec_state: pinmux-cec {
cec {
nvidia,pins = "hdmi_cec_pbb0";
nvidia,function = "hdmi_cec";
};
};
};
...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml
+73
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@@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra238 Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
$ref: nvidia,tegra-pinmux-common.yaml
properties:
nvidia,function:
enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat,
i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0,
usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din,
spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout,
gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat,
i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat,
dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd,
i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd,
uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk,
i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk,
i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk,
i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk,
i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out,
pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l,
pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l,
dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n,
uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk,
sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2,
sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec,
gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk,
spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din,
ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0,
ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd,
uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7,
gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat,
rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8,
nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux,
dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat,
dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk,
i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in,
sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk,
ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n,
ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso,
spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0,
spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat,
dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3,
tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3,
sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b,
tsc_edge_out0c, soc_therm_oc2 ]
# out of the common properties, only these are allowed for Tegra238
nvidia,pins: true
nvidia,pull: true
nvidia,tristate: true
nvidia,schmitt: true
nvidia,enable-input: true
nvidia,open-drain: true
nvidia,lock: true
nvidia,drive-type: true
nvidia,io-hv: true
required:
- nvidia,pins
additionalProperties: false
...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml
+219
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@@ -0,0 +1,219 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra238 Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra238-pinmux
reg:
maxItems: 1
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra238-pinmux-common.yaml
properties:
nvidia,pins:
items:
enum: [ gpu_pwr_req_pa0, gp_pwm5_pa1, gp_pwm6_pa2, spi3_sck_pa3,
spi3_miso_pa4, spi3_mosi_pa5, spi3_cs0_pa6, spi3_cs1_pa7,
spi1_sck_pb0, spi1_miso_pb1, spi1_mosi_pb2, spi1_cs0_pb3,
spi1_cs1_pb4, pwr_i2c_scl_pc0, pwr_i2c_sda_pc1,
extperiph1_clk_pc2, extperiph2_clk_pc3, cam_i2c_scl_pc4,
cam_i2c_sda_pc5, soc_gpio23_pc6, soc_gpio24_pc7,
soc_gpio27_pd0, soc_gpio55_pd1, soc_gpio29_pd2,
soc_gpio33_pd3, soc_gpio32_pd4, soc_gpio35_pd5,
soc_gpio37_pd6, soc_gpio56_pd7, uart1_tx_pe0,
uart1_rx_pe1, uart1_rts_pe2, uart1_cts_pe3,
soc_gpio13_pf0, soc_gpio14_pf1, soc_gpio15_pf2,
soc_gpio16_pf3, soc_gpio17_pf4, soc_gpio18_pf5,
soc_gpio20_pf6, soc_gpio21_pf7, soc_gpio22_pg0,
soc_gpio06_pg1, uart4_tx_pg2, uart4_rx_pg3,
uart4_rts_pg4, uart4_cts_pg5, soc_gpio41_pg6,
soc_gpio42_pg7, soc_gpio43_ph0, soc_gpio44_ph1,
gen1_i2c_scl_ph2, gen1_i2c_sda_ph3, cpu_pwr_req_ph4,
soc_gpio07_ph5, dap3_clk_pj0, dap3_dout_pj1,
dap3_din_pj2, dap3_fs_pj3, soc_gpio57_pj4,
soc_gpio58_pj5, soc_gpio59_pj6, soc_gpio60_pj7,
soc_gpio45_pk0, soc_gpio46_pk1, soc_gpio47_pk2,
soc_gpio48_pk3, qspi0_sck_pl0, qspi0_io0_pl1,
qspi0_io1_pl2, qspi0_cs_n_pl3, soc_gpio152_pl4,
soc_gpio153_pl5, soc_gpio154_pl6, soc_gpio155_pl7,
soc_gpio156_pm0, soc_gpio157_pm1, soc_gpio158_pm2,
soc_gpio159_pm3, soc_gpio160_pm4, soc_gpio161_pm5,
soc_gpio162_pm6, uart7_tx_pm7, uart7_rx_pn0,
uart7_rts_pn1, uart7_cts_pn2, soc_gpio167_pp0,
soc_gpio168_pp1, soc_gpio169_pp2, soc_gpio170_pp3,
dap4_sclk_pp4, dap4_dout_pp5, dap4_din_pp6, dap4_fs_pp7,
soc_gpio171_pq0, soc_gpio172_pq1, soc_gpio173_pq2,
soc_gpio61_pr0, soc_gpio62_pr1, soc_gpio63_pr2,
soc_gpio64_pr3, soc_gpio65_pr4, soc_gpio66_pr5,
soc_gpio67_pr6, soc_gpio68_pr7, gen4_i2c_scl_ps0,
gen4_i2c_sda_ps1, soc_gpio75_ps2, gen7_i2c_scl_ps3,
gen7_i2c_sda_ps4, soc_gpio78_ps5, gen9_i2c_scl_ps6,
gen9_i2c_sda_ps7, soc_gpio81_pt0, soc_gpio36_pt1,
soc_gpio53_pt2, soc_gpio38_pt3, soc_gpio40_pt4,
soc_gpio34_pt5, usb_vbus_en0_pt6, usb_vbus_en1_pt7,
sdmmc1_clk_pu0, sdmmc1_cmd_pu1, sdmmc1_dat0_pu2,
sdmmc1_dat1_pu3, sdmmc1_dat2_pu4, sdmmc1_dat3_pu5,
ufs0_ref_clk_pv0, ufs0_rst_n_pv1, pex_l0_clkreq_n_pw0,
pex_l0_rst_n_pw1, pex_l1_clkreq_n_pw2,
pex_l1_rst_n_pw3, pex_l2_clkreq_n_pw4,
pex_l2_rst_n_pw5, pex_l3_clkreq_n_pw6,
pex_l3_rst_n_pw7, pex_wake_n_px0, dp_aux_ch0_hpd_px1,
bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2,
pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5,
soc_gpio25_paa6, soc_gpio26_paa7, hdmi_cec_pbb0,
spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5,
uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3,
dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6,
pwm2_pdd7, pwm3_pee0, pwm7_pee1, soc_gpio49_pee2,
soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5,
soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2,
soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5,
soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0,
soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3,
uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6,
uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1,
uart5_cts_phh2, soc_gpio86_phh3, sdmmc1_comp,
# drive groups
drive_soc_gpio36_pt1, drive_soc_gpio53_pt2,
drive_soc_gpio38_pt3, drive_soc_gpio40_pt4,
drive_soc_gpio75_ps2, drive_soc_gpio81_pt0,
drive_soc_gpio78_ps5, drive_soc_gpio34_pt5,
drive_gen7_i2c_scl_ps3, drive_gen7_i2c_sda_ps4,
drive_gen4_i2c_sda_ps1, drive_gen4_i2c_scl_ps0,
drive_gen9_i2c_sda_ps7, drive_gen9_i2c_scl_ps6,
drive_usb_vbus_en0_pt6, drive_usb_vbus_en1_pt7,
drive_soc_gpio61_pr0, drive_soc_gpio62_pr1,
drive_soc_gpio63_pr2, drive_soc_gpio64_pr3,
drive_soc_gpio65_pr4, drive_soc_gpio66_pr5,
drive_soc_gpio67_pr6, drive_soc_gpio68_pr7,
drive_spi3_miso_pa4, drive_spi1_cs0_pb3,
drive_spi3_cs0_pa6, drive_spi1_miso_pb1,
drive_spi3_cs1_pa7, drive_spi1_sck_pb0,
drive_spi3_sck_pa3, drive_spi1_cs1_pb4,
drive_spi1_mosi_pb2, drive_spi3_mosi_pa5,
drive_gpu_pwr_req_pa0, drive_gp_pwm5_pa1,
drive_gp_pwm6_pa2, drive_extperiph2_clk_pc3,
drive_extperiph1_clk_pc2, drive_cam_i2c_sda_pc5,
drive_cam_i2c_scl_pc4, drive_soc_gpio23_pc6,
drive_soc_gpio24_pc7, drive_soc_gpio27_pd0,
drive_soc_gpio29_pd2, drive_soc_gpio32_pd4,
drive_soc_gpio33_pd3, drive_soc_gpio35_pd5,
drive_soc_gpio37_pd6, drive_soc_gpio56_pd7,
drive_soc_gpio55_pd1, drive_uart1_cts_pe3,
drive_uart1_rts_pe2, drive_uart1_rx_pe1,
drive_uart1_tx_pe0, drive_pwr_i2c_scl_pc0,
drive_pwr_i2c_sda_pc1, drive_cpu_pwr_req_ph4,
drive_uart4_cts_pg5, drive_uart4_rts_pg4,
drive_uart4_rx_pg3, drive_uart4_tx_pg2,
drive_gen1_i2c_scl_ph2, drive_gen1_i2c_sda_ph3,
drive_soc_gpio20_pf6, drive_soc_gpio21_pf7,
drive_soc_gpio22_pg0, drive_soc_gpio13_pf0,
drive_soc_gpio14_pf1, drive_soc_gpio15_pf2,
drive_soc_gpio16_pf3, drive_soc_gpio17_pf4,
drive_soc_gpio18_pf5, drive_soc_gpio41_pg6,
drive_soc_gpio42_pg7, drive_soc_gpio43_ph0,
drive_soc_gpio44_ph1, drive_soc_gpio06_pg1,
drive_soc_gpio07_ph5, drive_dap4_sclk_pp4,
drive_dap4_dout_pp5, drive_dap4_din_pp6,
drive_dap4_fs_pp7, drive_soc_gpio167_pp0,
drive_soc_gpio168_pp1, drive_soc_gpio169_pp2,
drive_soc_gpio170_pp3, drive_soc_gpio171_pq0,
drive_soc_gpio172_pq1, drive_soc_gpio173_pq2,
drive_soc_gpio45_pk0, drive_soc_gpio46_pk1,
drive_soc_gpio47_pk2, drive_soc_gpio48_pk3,
drive_soc_gpio57_pj4, drive_soc_gpio58_pj5,
drive_soc_gpio59_pj6, drive_soc_gpio60_pj7,
drive_dap3_fs_pj3, drive_dap3_clk_pj0,
drive_dap3_din_pj2, drive_dap3_dout_pj1,
drive_pex_l2_clkreq_n_pw4, drive_pex_wake_n_px0,
drive_pex_l1_clkreq_n_pw2, drive_pex_l1_rst_n_pw3,
drive_pex_l0_clkreq_n_pw0, drive_pex_l0_rst_n_pw1,
drive_pex_l2_rst_n_pw5, drive_pex_l3_clkreq_n_pw6,
drive_pex_l3_rst_n_pw7, drive_dp_aux_ch0_hpd_px1,
drive_qspi0_io0_pl1, drive_qspi0_io1_pl2,
drive_qspi0_sck_pl0, drive_qspi0_cs_n_pl3,
drive_soc_gpio156_pm0, drive_soc_gpio155_pl7,
drive_soc_gpio160_pm4, drive_soc_gpio154_pl6,
drive_soc_gpio152_pl4, drive_soc_gpio153_pl5,
drive_soc_gpio161_pm5, drive_soc_gpio162_pm6,
drive_soc_gpio159_pm3, drive_soc_gpio157_pm1,
drive_soc_gpio158_pm2, drive_uart7_cts_pn2,
drive_uart7_rts_pn1, drive_uart7_tx_pm7,
drive_uart7_rx_pn0, drive_sdmmc1_clk_pu0,
drive_sdmmc1_cmd_pu1, drive_sdmmc1_dat3_pu5,
drive_sdmmc1_dat2_pu4, drive_sdmmc1_dat1_pu3,
drive_sdmmc1_dat0_pu2, drive_ufs0_rst_n_pv1,
drive_ufs0_ref_clk_pv0, drive_batt_oc_paa4,
drive_bootv_ctl_n_paa0, drive_vcomp_alert_paa2,
drive_hdmi_cec_pbb0, drive_touch_clk_pdd3,
drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
drive_soc_gpio49_pee2, drive_soc_gpio50_pee4,
drive_soc_gpio82_pee3, drive_soc_gpio71_pff2,
drive_soc_gpio76_pff7, drive_soc_gpio74_pff5,
drive_soc_gpio00_paa1, drive_soc_gpio19_pdd6,
drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,
drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6,
drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5,
drive_soc_gpio73_pff4, drive_soc_gpio70_pff1,
drive_soc_gpio04_paa5, drive_soc_gpio85_pgg6,
drive_soc_gpio69_pff0, drive_soc_gpio25_paa6,
drive_soc_gpio26_paa7, drive_uart5_tx_pgg7,
drive_uart5_rx_phh0, drive_uart2_tx_pgg2,
drive_uart2_rx_pgg3, drive_uart2_cts_pgg5,
drive_uart2_rts_pgg4, drive_uart5_cts_phh2,
drive_uart5_rts_phh1, drive_pwm7_pee1,
drive_pwm2_pdd7, drive_pwm3_pee0, drive_pwm1_paa3,
drive_spi2_cs1_pcc4, drive_dmic1_clk_pdd4,
drive_dmic1_dat_pdd5, drive_sdmmc1_comp ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@2430000 {
compatible = "nvidia,tegra238-pinmux";
reg = <0x2430000 0x17000>;
pinctrl-names = "pex_rst";
pinctrl-0 = <&pex_rst_c5_out_state>;
pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
pexrst {
nvidia,pins = "pex_l3_rst_n_pw7";
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
};
};
...
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 AON Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra264-pinmux-aon
reg:
maxItems: 1
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra264-pinmux-common.yaml
properties:
nvidia,pins:
items:
enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
drive_ao_retention_n_paa2, drive_batt_oc_paa3,
drive_power_on_paa5, drive_vcomp_alert_paa1,
drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@c7a2000 {
compatible = "nvidia,tegra264-pinmux-aon";
reg = <0xc7a2000 0x2000>;
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux-default {
uart0 {
nvidia,pins = "uart0_tx_pcc5";
nvidia,function = "uarta_txd";
};
};
};
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 Pinmux Common Properties
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
$ref: nvidia,tegra-pinmux-common.yaml
properties:
nvidia,function:
enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd,
dp_aux_ch2_hpd, dp_aux_ch3_hpd, gp_pwm2, gp_pwm3, i2c7_clk,
i2c7_dat, i2c9_clk, i2c9_dat, uartk_cts, uartk_rts, uartk_rxd,
uartk_txd, spi3_cs0, spi3_cs3, spi3_din, spi3_dout, spi3_sck,
uartf_cts, uartf_rts, uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1,
spi1_din, spi1_dout, spi1_sck, extperiph2_clk, extperiph1_clk,
i2c12_clk, i2c12_dat, nv_therm_fan_tach0, gp_pwm9, uartj_cts,
uartj_rts, uartj_rxd, uartj_txd, i2c0_clk, i2c0_dat, i2c1_clk,
i2c1_dat, i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in,
gp_pwm10, uarte_cts, uarte_rts, uarte_rxd, uarte_txd, i2c5_dat,
i2c5_clk, i2s6_sdata_in, i2s6_sdata_out, i2s6_lrck, i2s6_sclk,
i2s4_sdata_out, i2s4_sclk, i2s4_sdata_in, i2s4_lrck, spi5_cs0,
spi5_din, spi5_dout, spi5_sck, aud_mclk, i2s1_sclk, i2s1_sdata_in,
i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, xhalt_trig,
gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, pe1_rst_l,
pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, sgmii0_sma_mdio,
sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, eth1_mdio, pe4_clkreq_l,
pe4_rst_l, pe5_clkreq_l, pe5_rst_l, eth0_mdio, eth0_mdc, eth1_mdc,
eth2_mdio, eth2_mdc, eth3_mdio, eth3_mdc, qspi0_cs_n, qspi0_io0,
qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, sdmmc1_clk, sdmmc1_cmd,
sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, sdmmc1_dat1, sdmmc1_dat0,
qspi3_sck, qspi3_cs0, qspi3_io0, qspi3_io1, dcb_vsync, dcb_hsync,
dsa_lspii, dce_vsync, dce_hsync, dch_vsync, dch_hsync, bl_en,
bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in,
extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck,
sdmmc1_cd, i2s7_sdata_in, spi4_sck, spi4_din, spi4_dout, spi4_cs0,
spi4_cs1, gp_pwm5, i2c14_clk, i2c14_dat, i2s8_sclk, i2s8_sdata_out,
i2s8_lrck, i2s8_sdata_in, i2c16_clk, i2c16_dat, i2s3_sclk,
i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, pm_trig1, pm_trig0,
qspi2_sck, qspi2_cs0, qspi2_io0, qspi2_io1, dcc_vsync, dcc_hsync,
rsvd2, dcf_vsync, dcf_hsync, soundwire1_clk, soundwire1_dat0,
soundwire1_dat1, soundwire1_dat2, dmic2_clk, dmic2_dat,
nv_therm_fan_tach1, i2c15_clk, i2c15_dat, i2s7_lrck,
ccla_la_trigger_mux, i2s7_sclk, i2s7_sdata_out, dmic1_dat,
dmic1_clk, dcd_vsync, dcd_hsync, rsvd3, dcg_vsync, dcg_hsync,
dspk1_clk, dspk1_dat, soc_therm_oc2, istctrl_ist_done_n,
soc_therm_oc1, tsc_edge_out0c, tsc_edge_out0d, tsc_edge_out0a,
tsc_edge_out0b, touch_clk, hdmi_cec, i2c2_clk, i2c2_dat, i2c3_clk,
i2c3_dat, gp_pwm4, uarta_txd, uarta_rxd, spi2_sck, spi2_din,
spi2_dout, spi2_cs0, tsc_sync1, tsc_edge_out3, tsc_edge_out0,
tsc_edge_out1, tsc_sync0, soundwire0_clk, soundwire0_dat0,
l0l1_rst_out_n, l2_rst_out_n, uartl_txd, uartl_rxd, i2s9_sclk,
i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, dmic5_clk,
tsc_edge_out2 ]
# out of the common properties, only these are allowed for Tegra264
nvidia,pins: true
nvidia,pull: true
nvidia,tristate: true
nvidia,schmitt: true
nvidia,enable-input: true
nvidia,open-drain: true
nvidia,lock: true
nvidia,drive-type: true
nvidia,io-hv: true
required:
- nvidia,pins
# We would typically use unevaluatedProperties here but that has the
# downside that all the properties in the common bindings become valid
# for all chip generations. In this case, however, we want the per-SoC
# bindings to be able to override which of the common properties are
# allowed, since not all pinmux generations support the same sets of
# properties. This way, the common bindings define the format of the
# properties but the per-SoC bindings define which of them apply to a
# given chip.
additionalProperties: false
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-main.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 Main Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra264-pinmux-main
reg:
maxItems: 1
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra264-pinmux-common.yaml
properties:
nvidia,pins:
items:
enum: [ pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4,
ufs0_rst_n_pa5, soc_gpio250_pf0, soc_gpio251_pf1,
soc_gpio252_pf2, dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4,
dp_aux_ch2_hpd_pf5, dp_aux_ch3_hpd_pf6, pwm2_pf7, pwm3_pg0,
gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3,
gen9_i2c_sda_pg4, sdmmc1_clk_px0, sdmmc1_cmd_px1,
sdmmc1_dat0_px2, sdmmc1_dat1_px3, sdmmc1_dat2_px4,
sdmmc1_dat3_px5, sdmmc1_comp, soc_gpio124_pl0,
soc_gpio125_pl1, fan_tach0_pl2, soc_gpio127_pl3,
soc_gpio128_pl4, soc_gpio129_pl5, soc_gpio130_pl6,
soc_gpio131_pl7, gp_pwm9_pm0, soc_gpio133_pm1, uart9_tx_pm2,
uart9_rx_pm3, uart9_rts_n_pm4, uart9_cts_n_pm5,
soc_gpio170_pu0, soc_gpio171_pu1, soc_gpio172_pu2,
soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5,
soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0,
pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4,
uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0,
dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3,
gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6,
pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1,
dap6_sclk_pp2, dap6_dout_pp3, dap6_din_pp4, dap6_fs_pp5,
dap4_sclk_pp6, dap4_dout_pp7, dap4_din_pq0, dap4_fs_pq1,
spi5_sck_pq2, spi5_miso_pq3, spi5_mosi_pq4, spi5_cs0_pq5,
soc_gpio152_pq6, soc_gpio153_pq7, aud_mclk_pr0,
soc_gpio155_pr1, dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4,
dap1_fs_pr5, gen11_i2c_scl_pr6, gen11_i2c_sda_pr7,
soc_gpio350_ps0, soc_gpio351_ps1, qspi0_sck_pt0,
qspi0_cs_n_pt1, qspi0_io0_pt2, qspi0_io1_pt3, qspi0_io2_pt4,
qspi0_io3_pt5, soc_gpio192_pt6, soc_gpio270_py0,
soc_gpio271_py1, soc_gpio272_py2, soc_gpio273_py3,
soc_gpio274_py4, soc_gpio275_py5, soc_gpio276_py6,
soc_gpio277_py7, soc_gpio278_pz0, soc_gpio279_pz1,
xhalt_trig_pz2, soc_gpio281_pz3, soc_gpio282_pz4,
soc_gpio283_pz5, soc_gpio284_pz6, soc_gpio285_pz7,
soc_gpio286_pal0, soc_gpio287_pal1, soc_gpio288_pal2,
cpu_pwr_req_ph0, gpu_pwr_req_ph1, uart10_tx_ph2,
uart10_rx_ph3, uart10_rts_n_ph4, uart10_cts_n_ph5,
spi3_sck_ph6, spi3_miso_ph7, spi3_mosi_pj0, spi3_cs0_pj1,
spi3_cs3_pj2, uart5_tx_pj3, uart5_rx_pj4, uart5_rts_n_pj5,
uart5_cts_n_pj6, spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1,
spi1_cs0_pk2, spi1_cs1_pk3, extperiph1_clk_pk4,
extperiph2_clk_pk5, gen12_i2c_scl_pk6, gen12_i2c_sda_pk7,
drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1,
drive_uart10_cts_n_ph5, drive_uart10_rts_n_ph4,
drive_uart10_rx_ph3, drive_uart10_tx_ph2,
drive_spi3_cs0_pj1, drive_spi3_cs3_pj2,
drive_spi3_miso_ph7, drive_spi3_mosi_pj0,
drive_spi3_sck_ph6, drive_uart5_cts_n_pj6,
drive_uart5_rts_n_pj5, drive_uart5_rx_pj4,
drive_uart5_tx_pj3, drive_spi1_cs0_pk2,
drive_spi1_cs1_pk3, drive_spi1_miso_pk0,
drive_spi1_mosi_pk1, drive_spi1_sck_pj7,
drive_extperiph2_clk_pk5, drive_extperiph1_clk_pk4,
drive_gen12_i2c_scl_pk6, drive_gen12_i2c_sda_pk7,
drive_soc_gpio124_pl0, drive_soc_gpio125_pl1,
drive_fan_tach0_pl2, drive_soc_gpio127_pl3,
drive_soc_gpio128_pl4, drive_soc_gpio129_pl5,
drive_soc_gpio130_pl6, drive_soc_gpio131_pl7,
drive_gp_pwm9_pm0, drive_soc_gpio133_pm1,
drive_uart9_cts_n_pm5, drive_uart9_rts_n_pm4,
drive_uart9_rx_pm3, drive_uart9_tx_pm2,
drive_sdmmc1_clk_px0, drive_sdmmc1_cmd_px1,
drive_sdmmc1_dat3_px5, drive_sdmmc1_dat2_px4,
drive_sdmmc1_dat1_px3, drive_sdmmc1_dat0_px2,
drive_qspi0_cs_n_pt1, drive_qspi0_io0_pt2,
drive_qspi0_io1_pt3, drive_qspi0_io2_pt4,
drive_qspi0_io3_pt5, drive_qspi0_sck_pt0,
drive_soc_gpio192_pt6, drive_soc_gpio138_pp0,
drive_soc_gpio139_pp1, drive_dap6_din_pp4,
drive_dap6_dout_pp3, drive_dap6_fs_pp5,
drive_dap6_sclk_pp2, drive_dap4_dout_pp7,
drive_dap4_sclk_pp6, drive_dap4_din_pq0,
drive_dap4_fs_pq1, drive_spi5_cs0_pq5,
drive_spi5_miso_pq3, drive_spi5_mosi_pq4,
drive_spi5_sck_pq2, drive_soc_gpio152_pq6,
drive_soc_gpio153_pq7, drive_soc_gpio155_pr1,
drive_aud_mclk_pr0, drive_dap1_sclk_pr2,
drive_dap1_in_pr4, drive_dap1_out_pr3,
drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6,
drive_gen11_i2c_sda_pr7, drive_soc_gpio350_ps0,
drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4,
drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2,
drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1,
drive_dap2_clk_pv6, drive_dap2_din_pv7,
drive_dap2_dout_pw0, drive_pwm10_pv1,
drive_soc_gpio170_pu0, drive_soc_gpio171_pu1,
drive_soc_gpio172_pu2, drive_soc_gpio173_pu3,
drive_soc_gpio174_pu4, drive_soc_gpio175_pu5,
drive_soc_gpio176_pu6, drive_soc_gpio177_pu7,
drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5,
drive_uart4_rts_n_pv4, drive_uart4_rx_pv3,
drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7,
drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0,
drive_soc_gpio251_pf1, drive_soc_gpio252_pf2,
drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4,
drive_dp_aux_ch2_hpd_pf5, drive_dp_aux_ch3_hpd_pf6,
drive_pwm2_pf7, drive_pwm3_pg0,
drive_gen7_i2c_scl_pg1, drive_gen7_i2c_sda_pg2,
drive_gen9_i2c_scl_pg3, drive_gen9_i2c_sda_pg4,
drive_soc_gpio270_py0, drive_soc_gpio271_py1,
drive_soc_gpio272_py2, drive_soc_gpio273_py3,
drive_soc_gpio274_py4, drive_soc_gpio275_py5,
drive_soc_gpio276_py6, drive_soc_gpio277_py7,
drive_soc_gpio278_pz0, drive_soc_gpio279_pz1,
drive_soc_gpio282_pz4, drive_soc_gpio283_pz5,
drive_soc_gpio284_pz6, drive_soc_gpio285_pz7,
drive_soc_gpio286_pal0, drive_soc_gpio287_pal1,
drive_soc_gpio288_pal2, drive_xhalt_trig_pz2,
drive_soc_gpio281_pz3 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@c281000 {
compatible = "nvidia,tegra264-pinmux-main";
reg = <0xc281000 0xc000>;
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux-default {
sdmmc1 {
nvidia,pins = "sdmmc1_clk_px0";
nvidia,function = "sdmmc1_cd";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml
+78
View File
@@ -0,0 +1,78 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 UPHY Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra264-pinmux-uphy
reg:
maxItems: 1
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra264-pinmux-common.yaml
properties:
nvidia,pins:
items:
enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1,
pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4,
eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3,
eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0,
pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3,
pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5,
sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6,
soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3,
ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0,
drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1,
drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3,
drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1,
drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6,
drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0,
drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2,
drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2,
drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5,
drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1,
drive_soc_gpio113_pb6, drive_soc_gpio114_pb7,
drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2,
drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@82e0000 {
compatible = "nvidia,tegra264-pinmux-uphy";
reg = <0x82e0000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
pinmux_default: pinmux-default {
pex {
nvidia,pins = "pex_l1_rst_n_pb1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml
+57
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@@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/pinctrl-multiplexer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic pinctrl device for on-board MUX Chips
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
Generic pinctrl device for on-board MUX Chips, which switch SoC signals
between different peripherals (e.g. MMC and UART).
The MUX select lines are often driven by a I2C GPIO expander.
properties:
compatible:
const: pinctrl-multiplexer
patternProperties:
'-grp$':
type: object
additionalProperties: false
properties:
mux-states:
maxItems: 1
required:
- mux-states
required:
- compatible
allOf:
- $ref: pinctrl.yaml#
unevaluatedProperties: false
examples:
- |
pinctrl-mux {
compatible = "pinctrl-multiplexer";
uart-grp {
mux-states = <&mux 0>;
};
spi-grp {
mux-states = <&mux 1>;
};
i2c-grp {
mux-states = <&mux 2>;
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl.yaml
+1 -1
View File
@@ -27,7 +27,7 @@ description: |
properties:
$nodename:
pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$"
pattern: "^(pinctrl|pinmux)(@[0-9a-f]+|-[a-z0-9]+)?$"
"#pinctrl-cells":
description: >
Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
+16 -10
View File
@@ -86,16 +86,22 @@ $defs:
qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
qlink_big_request, qlink_little_enable,
qlink_little_request, qlink_wmss, qspi0, qspi_clk,
qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,
sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,
tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,
tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk,
uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,
vsense_trigger_mirnat, wcn_sw_ctrl ]
qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira,
qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb,
qup1_se3, qup1_se4_01, qup1_se4_23,
qup1_se5, qup1_se6, qup1_se6_l1_mira,
qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb,
qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb,
qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1,
qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb,
qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5,
qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1,
sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2,
tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4,
uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk,
uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy,
vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ]
required:
- pins
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml
-5
View File
@@ -36,11 +36,6 @@ patternProperties:
$ref: "#/$defs/qcom-ipq4019-tlmm-state"
additionalProperties: false
"-hog(-[0-9]+)?$":
type: object
required:
- gpio-hog
$defs:
qcom-ipq4019-tlmm-state:
type: object

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