mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "There's a bunch of patches here across drivers/clk/ to migrate drivers to use struct clk_ops::determine_rate() instead of the round_rate() one so that we can remove the round_rate clk_op entirely. Brian has taken up that task which nobody else has wanted to do for close to a decade. Thanks Brian! This is all prerequisite work to get to the real task of improving the clk rate setting process. Once we have determine_rate() used everywhere, we'll be able to do things like chain the rate request structs in linked lists to order the rate setting operations or add more parameters without having to change every clk driver in existence. It's also nice to not have multiple ways to do something which just causes confusion for clk driver authors. Overall I'm glad this is getting done. Beyond this change we also have a tweak to the clk_lookup() function in the core framework to use hashing on the clk name instead of a clk tree walk with string comparisons. We _still_ rely on the clk name to be unique, because historically we've used globally unique strings to describe the clk tree topology. This tree walk becomes increasingly slow as more clks are added to the system. Searching from the roots for a duplicate is simple but pretty dumb and it wastes boot time so we're using a hash table as an improvement. Ideally we wouldn't rely on the strings to be unique at all, relegating them to simply debug information, but that is future work that will likely require some sort of Kconfig knob indicating strings aren't used for topology description. Outside of the core framework changes we have the usual new SoC support and fixes to clk drivers for things that were discovered once the clks were used by consumer drivers. Nothing in particular is jumping out at me in the "misc" pile, except maybe the Amlogic driver that has gone through a refactoring. That series got a fix from testing in -next though so it seems likely that things have been getting good test coverage for a couple weeks already" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits) clk: microchip: core: remove duplicate roclk_determine_rate() reset: aspeed: register AST2700 reset auxiliary bus device dt-bindings: clock: ast2700: modify soc0/1 clock define clk: tegra: do not overallocate memory for bpmp clocks clk: ep93xx: Use int type to store negative error codes clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver clk: loongson2: Add clock definitions for Loongson-2K0300 SoC clk: loongson2: Avoid hardcoding firmware name of the reference clock clk: loongson2: Allow zero divisors for dividers clk: loongson2: Support scale clocks with an alternative mode clk: loongson2: Allow specifying clock flags for gate clock dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible clk: clocking-wizard: Fix output clock register offset for Versal platforms clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver() clk: mmp: pxa1908: Instantiate power driver through auxiliary bus clk: s2mps11: add support for S2MPG10 PMIC clock dt-bindings: clock: samsung,s2mps11: add s2mpg10 dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings clk: stm32: introduce clocks for STM32MP21 platform dt-bindings: stm32: add STM32MP21 clocks and reset bindings ...
This commit is contained in:
Linus Torvalds
@@ -42,6 +42,9 @@ properties:
|
||||
- const: clkin2
|
||||
- const: s_axi_aclk
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
@@ -65,4 +68,5 @@ examples:
|
||||
reg = <0xff000000 0x1000>;
|
||||
clocks = <&osc 1>, <&clkc 15>;
|
||||
clock-names = "clkin1", "s_axi_aclk";
|
||||
clock-output-names = "spi_sclk";
|
||||
};
|
||||
|
||||
@@ -1,26 +0,0 @@
|
||||
Fujitsu CRG11 clock driver bindings
|
||||
-----------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : Shall contain "fujitsu,mb86s70-crg11"
|
||||
- #clock-cells : Shall be 3 {cntrlr domain port}
|
||||
|
||||
The consumer specifies the desired clock pointing to its phandle.
|
||||
|
||||
Example:
|
||||
|
||||
clock: crg11 {
|
||||
compatible = "fujitsu,mb86s70-crg11";
|
||||
#clock-cells = <3>;
|
||||
};
|
||||
|
||||
mhu: mhu0@2b1f0000 {
|
||||
#mbox-cells = <1>;
|
||||
compatible = "arm,mhu";
|
||||
reg = <0 0x2B1F0000 0x1000>;
|
||||
interrupts = <0 36 4>, /* LP Non-Sec */
|
||||
<0 35 4>, /* HP Non-Sec */
|
||||
<0 37 4>; /* Secure */
|
||||
clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
|
||||
clock-names = "clk";
|
||||
};
|
||||
@@ -16,6 +16,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- loongson,ls2k0300-clk
|
||||
- loongson,ls2k0500-clk
|
||||
- loongson,ls2k-clk # This is for Loongson-2K1000
|
||||
- loongson,ls2k2000-clk
|
||||
@@ -24,8 +25,7 @@ properties:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: 100m ref
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
@@ -38,11 +38,23 @@ properties:
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h
|
||||
for the full list of Loongson-2 SoC clock IDs.
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: loongson,ls2k0300-clk
|
||||
then:
|
||||
properties:
|
||||
clock-names: false
|
||||
else:
|
||||
required:
|
||||
- clock-names
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
@@ -0,0 +1,112 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8196
|
||||
|
||||
maintainers:
|
||||
- Guangjie Song <guangjie.song@mediatek.com>
|
||||
- Laura Nao <laura.nao@collabora.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek SoCs is structured like below:
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The device nodes provide clock gate control in different IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8196-imp-iic-wrap-c
|
||||
- mediatek,mt8196-imp-iic-wrap-e
|
||||
- mediatek,mt8196-imp-iic-wrap-n
|
||||
- mediatek,mt8196-imp-iic-wrap-w
|
||||
- mediatek,mt8196-mdpsys0
|
||||
- mediatek,mt8196-mdpsys1
|
||||
- mediatek,mt8196-pericfg-ao
|
||||
- mediatek,mt8196-pextp0cfg-ao
|
||||
- mediatek,mt8196-pextp1cfg-ao
|
||||
- mediatek,mt8196-ufscfg-ao
|
||||
- mediatek,mt8196-vencsys
|
||||
- mediatek,mt8196-vencsys-c1
|
||||
- mediatek,mt8196-vencsys-c2
|
||||
- mediatek,mt8196-vdecsys
|
||||
- mediatek,mt8196-vdecsys-soc
|
||||
- mediatek,mt8196-vdisp-ao
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
description:
|
||||
Reset lines for PEXTP0/1 and UFS blocks.
|
||||
|
||||
mediatek,hardware-voter:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Phandle to the "Hardware Voter" (HWV), as named in the vendor
|
||||
documentation for MT8196/MT6991.
|
||||
|
||||
The HWV is a SoC-internal fixed-function MCU used to collect votes from
|
||||
both the Application Processor and other remote processors within the SoC.
|
||||
It is intended to transparently enable or disable hardware resources (such
|
||||
as power domains or clocks) based on internal vote aggregation handled by
|
||||
the MCU's internal state machine.
|
||||
|
||||
However, in practice, this design is incomplete. While the HWV performs
|
||||
some internal vote aggregation,software is still required to
|
||||
- Manually enable power supplies externally, if present and if required
|
||||
- Manually enable parent clocks via direct MMIO writes to clock controllers
|
||||
- Enable the FENC after the clock has been ungated via direct MMIO
|
||||
writes to clock controllers
|
||||
|
||||
As such, the HWV behaves more like a hardware-managed clock reference
|
||||
counter than a true voter. Furthermore, it is not a separate
|
||||
controller. It merely serves as an alternative interface to the same
|
||||
underlying clock or power controller. Actual control still requires
|
||||
direct access to the controller's own MMIO register space, in
|
||||
addition to writing to the HWV's MMIO region.
|
||||
|
||||
For this reason, a custom phandle is used here - drivers need to directly
|
||||
access the HWV MMIO region in a syscon-like fashion, due to how the
|
||||
hardware is wired. This differs from true hardware voting systems, which
|
||||
typically do not require custom phandles and rely instead on generic APIs
|
||||
(clocks, power domains, interconnects).
|
||||
|
||||
The name "hardware-voter" is retained to match vendor documentation, but
|
||||
this should not be reused or misunderstood as a proper voting mechanism.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pericfg_ao: clock-controller@16640000 {
|
||||
compatible = "mediatek,mt8196-pericfg-ao", "syscon";
|
||||
reg = <0x16640000 0x1000>;
|
||||
mediatek,hardware-voter = <&scp_hwv>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
- |
|
||||
pextp0cfg_ao: clock-controller@169b0000 {
|
||||
compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";
|
||||
reg = <0x169b0000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,107 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek System Clock Controller for MT8196
|
||||
|
||||
maintainers:
|
||||
- Guangjie Song <guangjie.song@mediatek.com>
|
||||
- Laura Nao <laura.nao@collabora.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek SoCs is structured like below:
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll
|
||||
provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.
|
||||
The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which
|
||||
provide the clock source to other IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8196-apmixedsys
|
||||
- mediatek,mt8196-armpll-b-pll-ctrl
|
||||
- mediatek,mt8196-armpll-bl-pll-ctrl
|
||||
- mediatek,mt8196-armpll-ll-pll-ctrl
|
||||
- mediatek,mt8196-apmixedsys-gp2
|
||||
- mediatek,mt8196-ccipll-pll-ctrl
|
||||
- mediatek,mt8196-mfgpll-pll-ctrl
|
||||
- mediatek,mt8196-mfgpll-sc0-pll-ctrl
|
||||
- mediatek,mt8196-mfgpll-sc1-pll-ctrl
|
||||
- mediatek,mt8196-ptppll-pll-ctrl
|
||||
- mediatek,mt8196-topckgen
|
||||
- mediatek,mt8196-topckgen-gp2
|
||||
- mediatek,mt8196-vlpckgen
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
mediatek,hardware-voter:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: |
|
||||
Phandle to the "Hardware Voter" (HWV), as named in the vendor
|
||||
documentation for MT8196/MT6991.
|
||||
|
||||
The HWV is a SoC-internal fixed-function MCU used to collect votes from
|
||||
both the Application Processor and other remote processors within the SoC.
|
||||
It is intended to transparently enable or disable hardware resources (such
|
||||
as power domains or clocks) based on internal vote aggregation handled by
|
||||
the MCU's internal state machine.
|
||||
|
||||
However, in practice, this design is incomplete. While the HWV performs
|
||||
some internal vote aggregation,software is still required to
|
||||
- Manually enable power supplies externally, if present and if required
|
||||
- Manually enable parent clocks via direct MMIO writes to clock controllers
|
||||
- Enable the FENC after the clock has been ungated via direct MMIO
|
||||
writes to clock controllers
|
||||
|
||||
As such, the HWV behaves more like a hardware-managed clock reference
|
||||
counter than a true voter. Furthermore, it is not a separate
|
||||
controller. It merely serves as an alternative interface to the same
|
||||
underlying clock or power controller. Actual control still requires
|
||||
direct access to the controller's own MMIO register space, in
|
||||
addition to writing to the HWV's MMIO region.
|
||||
|
||||
For this reason, a custom phandle is used here - drivers need to directly
|
||||
access the HWV MMIO region in a syscon-like fashion, due to how the
|
||||
hardware is wired. This differs from true hardware voting systems, which
|
||||
typically do not require custom phandles and rely instead on generic APIs
|
||||
(clocks, power domains, interconnects).
|
||||
|
||||
The name "hardware-voter" is retained to match vendor documentation, but
|
||||
this should not be reused or misunderstood as a proper voting mechanism.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
apmixedsys_clk: syscon@10000800 {
|
||||
compatible = "mediatek,mt8196-apmixedsys", "syscon";
|
||||
reg = <0x10000800 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
- |
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8196-topckgen", "syscon";
|
||||
reg = <0x10000000 0x800>;
|
||||
mediatek,hardware-voter = <&scp_hwv>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
@@ -76,6 +76,9 @@ properties:
|
||||
- const: mediatek,mt2701-vdecsys
|
||||
- const: syscon
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -86,6 +89,18 @@ required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8183-mfgcfg
|
||||
then:
|
||||
properties:
|
||||
power-domains: true
|
||||
else:
|
||||
properties:
|
||||
power-domains: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -9,16 +9,21 @@ title: Qualcomm Global Clock & Reset Controller on MSM8953
|
||||
maintainers:
|
||||
- Adam Skladowski <a_skl39@protonmail.com>
|
||||
- Sireesh Kodali <sireeshkodali@protonmail.com>
|
||||
- Barnabas Czeman <barnabas.czeman@mainlining.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8953.
|
||||
domains on MSM8937 or MSM8953.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8917.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-msm8953
|
||||
enum:
|
||||
- qcom,gcc-msm8937
|
||||
- qcom,gcc-msm8953
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@@ -0,0 +1,98 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on GLYMUR
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains for the MDSS instances on GLYMUR SoC.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,dispcc-glymur.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board CXO clock
|
||||
- description: Board sleep clock
|
||||
- description: DisplayPort 0 link clock
|
||||
- description: DisplayPort 0 VCO div clock
|
||||
- description: DisplayPort 1 link clock
|
||||
- description: DisplayPort 1 VCO div clock
|
||||
- description: DisplayPort 2 link clock
|
||||
- description: DisplayPort 2 VCO div clock
|
||||
- description: DisplayPort 3 link clock
|
||||
- description: DisplayPort 3 VCO div clock
|
||||
- description: DSI 0 PLL byte clock
|
||||
- description: DSI 0 PLL DSI clock
|
||||
- description: DSI 1 PLL byte clock
|
||||
- description: DSI 1 PLL DSI clock
|
||||
- description: Standalone PHY 0 PLL link clock
|
||||
- description: Standalone PHY 0 VCO div clock
|
||||
- description: Standalone PHY 1 PLL link clock
|
||||
- description: Standalone PHY 1 VCO div clock
|
||||
|
||||
power-domains:
|
||||
description:
|
||||
A phandle and PM domain specifier for the MMCX power domain.
|
||||
maxItems: 1
|
||||
|
||||
required-opps:
|
||||
description:
|
||||
A phandle to an OPP node describing required MMCX performance point.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- power-domains
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom,rpmhpd.h>
|
||||
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,glymur-dispcc";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&mdss_dp_phy0 0>,
|
||||
<&mdss_dp_phy0 1>,
|
||||
<&mdss_dp_phy1 0>,
|
||||
<&mdss_dp_phy1 1>,
|
||||
<&mdss_dp_phy2 0>,
|
||||
<&mdss_dp_phy2 1>,
|
||||
<&mdss_dp_phy3 0>,
|
||||
<&mdss_dp_phy3 1>,
|
||||
<&mdss_dsi0_phy 0>,
|
||||
<&mdss_dsi0_phy 1>,
|
||||
<&mdss_dsi1_phy 0>,
|
||||
<&mdss_dsi1_phy 1>,
|
||||
<&mdss_phy0_link 0>,
|
||||
<&mdss_phy0_vco_div 0>,
|
||||
<&mdss_phy1_link 1>,
|
||||
<&mdss_phy1_vco_div 1>;
|
||||
power-domains = <&rpmhpd RPMHPD_MMCX>;
|
||||
required-opps = <&rpmhpd_opp_low_svs>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,121 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,glymur-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on Glymur SoC
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on Glymur SoC.
|
||||
|
||||
See also: include/dt-bindings/clock/qcom,glymur-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,glymur-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board XO_A source
|
||||
- description: Sleep clock source
|
||||
- description: USB 0 Phy DP0 GMUX clock source
|
||||
- description: USB 0 Phy DP1 GMUX clock source
|
||||
- description: USB 0 Phy PCIE PIPEGMUX clock source
|
||||
- description: USB 0 Phy PIPEGMUX clock source
|
||||
- description: USB 0 Phy SYS PCIE PIPEGMUX clock source
|
||||
- description: USB 1 Phy DP0 GMUX 2 clock source
|
||||
- description: USB 1 Phy DP1 GMUX 2 clock source
|
||||
- description: USB 1 Phy PCIE PIPEGMUX clock source
|
||||
- description: USB 1 Phy PIPEGMUX clock source
|
||||
- description: USB 1 Phy SYS PCIE PIPEGMUX clock source
|
||||
- description: USB 2 Phy DP0 GMUX 2 clock source
|
||||
- description: USB 2 Phy DP1 GMUX 2 clock source
|
||||
- description: USB 2 Phy PCIE PIPEGMUX clock source
|
||||
- description: USB 2 Phy PIPEGMUX clock source
|
||||
- description: USB 2 Phy SYS PCIE PIPEGMUX clock source
|
||||
- description: PCIe 3a pipe clock
|
||||
- description: PCIe 3b pipe clock
|
||||
- description: PCIe 4 pipe clock
|
||||
- description: PCIe 5 pipe clock
|
||||
- description: PCIe 6 pipe clock
|
||||
- description: QUSB4 0 PHY RX 0 clock source
|
||||
- description: QUSB4 0 PHY RX 1 clock source
|
||||
- description: QUSB4 1 PHY RX 0 clock source
|
||||
- description: QUSB4 1 PHY RX 1 clock source
|
||||
- description: QUSB4 2 PHY RX 0 clock source
|
||||
- description: QUSB4 2 PHY RX 1 clock source
|
||||
- description: UFS PHY RX Symbol 0 clock source
|
||||
- description: UFS PHY RX Symbol 1 clock source
|
||||
- description: UFS PHY TX Symbol 0 clock source
|
||||
- description: USB3 PHY 0 pipe clock source
|
||||
- description: USB3 PHY 1 pipe clock source
|
||||
- description: USB3 PHY 2 pipe clock source
|
||||
- description: USB3 UNI PHY pipe 0 clock source
|
||||
- description: USB3 UNI PHY pipe 1 clock source
|
||||
- description: USB4 PHY 0 pcie pipe clock source
|
||||
- description: USB4 PHY 0 Max pipe clock source
|
||||
- description: USB4 PHY 1 pcie pipe clock source
|
||||
- description: USB4 PHY 1 Max pipe clock source
|
||||
- description: USB4 PHY 2 pcie pipe clock source
|
||||
- description: USB4 PHY 2 Max pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- '#power-domain-cells'
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,glymur-gcc";
|
||||
reg = <0x100000 0x1f9000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&usb_0_phy_dp0_gmux>,
|
||||
<&usb_0_phy_dp1_gmux>,
|
||||
<&usb_0_phy_pcie_pipegmux>,
|
||||
<&usb_0_phy_pipegmux>,
|
||||
<&usb_0_phy_sys_pcie_pipegmux>,
|
||||
<&usb_1_phy_dp0_gmux_2>,
|
||||
<&usb_1_phy_dp1_gmux_2>,
|
||||
<&usb_1_phy_pcie_pipegmux>,
|
||||
<&usb_1_phy_pipegmux>,
|
||||
<&usb_1_phy_sys_pcie_pipegmux>,
|
||||
<&usb_2_phy_dp0_gmux 2>,
|
||||
<&usb_2_phy_dp1_gmux 2>,
|
||||
<&usb_2_phy_pcie_pipegmux>,
|
||||
<&usb_2_phy_pipegmux>,
|
||||
<&usb_2_phy_sys_pcie_pipegmux>,
|
||||
<&pcie_3a_pipe>, <&pcie_3b_pipe>,
|
||||
<&pcie_4_pipe>, <&pcie_5_pipe>,
|
||||
<&pcie_6_pipe>,
|
||||
<&qusb4_0_phy_rx_0>, <&qusb4_0_phy_rx_1>,
|
||||
<&qusb4_1_phy_rx_0>, <&qusb4_1_phy_rx_1>,
|
||||
<&qusb4_2_phy_rx_0>, <&qusb4_2_phy_rx_1>,
|
||||
<&ufs_phy_rx_symbol_0>, <&ufs_phy_rx_symbol_1>,
|
||||
<&ufs_phy_tx_symbol_0>,
|
||||
<&usb3_phy_0_pipe>, <&usb3_phy_1_pipe>,
|
||||
<&usb3_phy_2_pipe>,
|
||||
<&usb3_uni_phy_pipe_0>, <&usb3_uni_phy_pipe_1>,
|
||||
<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
|
||||
<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
|
||||
<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -17,6 +17,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-rpmh-clk
|
||||
- qcom,milos-rpmh-clk
|
||||
- qcom,qcs615-rpmh-clk
|
||||
- qcom,qdu1000-rpmh-clk
|
||||
|
||||
@@ -8,12 +8,14 @@ title: Qualcomm TCSR Clock Controller on SM8550
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Taniya Das <taniya.das@oss.qualcomm.com>
|
||||
|
||||
description: |
|
||||
Qualcomm TCSR clock control module provides the clocks, resets and
|
||||
power domains on SM8550
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,glymur-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
|
||||
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
|
||||
@@ -22,6 +24,7 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,glymur-tcsr
|
||||
- qcom,milos-tcsr
|
||||
- qcom,sar2130p-tcsr
|
||||
- qcom,sm8550-tcsr
|
||||
|
||||
@@ -23,13 +23,17 @@ description: |
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sc7280-videocc
|
||||
- qcom,sdm845-videocc
|
||||
- qcom,sm6350-videocc
|
||||
- qcom,sm8150-videocc
|
||||
- qcom,sm8250-videocc
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,sc7180-videocc
|
||||
- qcom,sc7280-videocc
|
||||
- qcom,sdm845-videocc
|
||||
- qcom,sm6350-videocc
|
||||
- qcom,sm8150-videocc
|
||||
- qcom,sm8250-videocc
|
||||
- items:
|
||||
- const: qcom,sc8180x-videocc
|
||||
- const: qcom,sm8150-videocc
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
@@ -110,8 +114,9 @@ allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sm8150-videocc
|
||||
contains:
|
||||
enum:
|
||||
- qcom,sm8150-videocc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
|
||||
@@ -30,6 +30,8 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-peric1
|
||||
- samsung,exynos990-cmu-peric0
|
||||
- samsung,exynos990-cmu-hsi0
|
||||
- samsung,exynos990-cmu-peris
|
||||
- samsung,exynos990-cmu-top
|
||||
@@ -56,6 +58,28 @@ required:
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-peric1
|
||||
- samsung,exynos990-cmu-peric0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
|
||||
- description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: ip
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -25,6 +25,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,s2mpg10-clk
|
||||
- samsung,s2mps11-clk
|
||||
- samsung,s2mps13-clk # S2MPS13 and S2MPS15
|
||||
- samsung,s2mps14-clk
|
||||
|
||||
@@ -1,24 +0,0 @@
|
||||
Binding for Silicon Labs 514 programmable I2C clock generator.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1]. Details about the device can be
|
||||
found in the datasheet[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si514 datasheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall be "silabs,si514"
|
||||
- reg: I2C device address.
|
||||
- #clock-cells: From common clock bindings: Shall be 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock bindings. Recommended to be "si514".
|
||||
|
||||
Example:
|
||||
si514: clock-generator@55 {
|
||||
reg = <0x55>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si514";
|
||||
};
|
||||
@@ -1,175 +0,0 @@
|
||||
Binding for Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable
|
||||
i2c clock generator.
|
||||
|
||||
Reference
|
||||
[1] Si5341 Data Sheet
|
||||
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
|
||||
[2] Si5341 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
|
||||
[3] Si5345 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
|
||||
|
||||
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
|
||||
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
|
||||
in turn can be directed to any of the 10 (or 4) outputs through a divider.
|
||||
The internal structure of the clock generators can be found in [2].
|
||||
The Si5345 is similar to the Si5341 with the addition of fractional input
|
||||
dividers and automatic input selection, as described in [3].
|
||||
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
|
||||
|
||||
The driver can be used in "as is" mode, reading the current settings from the
|
||||
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
|
||||
configured when the driver probes, it assumes the driver must fully initialize
|
||||
it.
|
||||
|
||||
The device type, speed grade and revision are determined runtime by probing.
|
||||
|
||||
The driver currently does not support any fancy input configurations. They can
|
||||
still be programmed into the chip and the driver will leave them "as is".
|
||||
|
||||
==I2C device node==
|
||||
|
||||
Required properties:
|
||||
- compatible: shall be one of the following:
|
||||
"silabs,si5340" - Si5340 A/B/C/D
|
||||
"silabs,si5341" - Si5341 A/B/C/D
|
||||
"silabs,si5342" - Si5342 A/B/C/D
|
||||
"silabs,si5344" - Si5344 A/B/C/D
|
||||
"silabs,si5345" - Si5345 A/B/C/D
|
||||
- reg: i2c device address, usually 0x74
|
||||
- #clock-cells: from common clock binding; shall be set to 2.
|
||||
The first value is "0" for outputs, "1" for synthesizers.
|
||||
The second value is the output or synthesizer index.
|
||||
- clocks: from common clock binding; list of parent clock handles,
|
||||
corresponding to inputs. Use a fixed clock for the "xtal" input.
|
||||
At least one must be present.
|
||||
- clock-names: One of: "xtal", "in0", "in1", "in2"
|
||||
|
||||
Optional properties:
|
||||
- vdd-supply: Regulator node for VDD
|
||||
- vdda-supply: Regulator node for VDDA
|
||||
- vdds-supply: Regulator node for VDDS
|
||||
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
|
||||
feedback divider. Must be such that the PLL output is in the valid range. For
|
||||
example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
|
||||
the fraction matters, using 3500 and 12 will deliver the exact same result.
|
||||
If these are not specified, and the PLL is not yet programmed when the driver
|
||||
probes, the PLL will be set to 14GHz.
|
||||
- silabs,reprogram: When present, the driver will always assume the device must
|
||||
be initialized, and always performs the soft-reset routine. Since this will
|
||||
temporarily stop all output clocks, don't do this if the chip is generating
|
||||
the CPU clock for example.
|
||||
- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
|
||||
in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
|
||||
- interrupts: Interrupt for INTRb pin.
|
||||
- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
|
||||
rather than 1.8V thresholds.
|
||||
- vddoX-supply (where X is an output index): Regulator node for VDDO for the
|
||||
specified output. The driver selects the output VDD_SEL setting based on this
|
||||
voltage.
|
||||
- #address-cells: shall be set to 1.
|
||||
- #size-cells: shall be set to 0.
|
||||
|
||||
|
||||
== Child nodes: Outputs ==
|
||||
|
||||
The child nodes list the output clocks.
|
||||
|
||||
Each of the clock outputs can be overwritten individually by using a child node.
|
||||
If a child node for a clock output is not set, the configuration remains
|
||||
unchanged.
|
||||
|
||||
Required child node properties:
|
||||
- reg: number of clock output.
|
||||
|
||||
Optional child node properties:
|
||||
- silabs,format: Output format, one of:
|
||||
1 = differential (defaults to LVDS levels)
|
||||
2 = low-power (defaults to HCSL levels)
|
||||
4 = LVCMOS
|
||||
- silabs,common-mode: Manually override output common mode, see [2] for values
|
||||
- silabs,amplitude: Manually override output amplitude, see [2] for values
|
||||
- silabs,synth-master: boolean. If present, this output is allowed to change the
|
||||
multisynth frequency dynamically.
|
||||
- silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
|
||||
when disabled, otherwise it's driven LOW.
|
||||
|
||||
==Example==
|
||||
|
||||
/* 48MHz reference crystal */
|
||||
ref48: ref48M {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
i2c-master-node {
|
||||
/* Programmable clock (for logic) */
|
||||
si5341: clock-generator@74 {
|
||||
reg = <0x74>;
|
||||
compatible = "silabs,si5341";
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&ref48>;
|
||||
clock-names = "xtal";
|
||||
|
||||
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
|
||||
silabs,pll-m-den = <48>;
|
||||
silabs,reprogram; /* Chips are not programmed, always reset */
|
||||
|
||||
out@0 {
|
||||
reg = <0>;
|
||||
silabs,format = <1>; /* LVDS 3v3 */
|
||||
silabs,common-mode = <3>;
|
||||
silabs,amplitude = <3>;
|
||||
silabs,synth-master;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 6 configuration:
|
||||
* LVDS 1v8
|
||||
*/
|
||||
out@6 {
|
||||
reg = <6>;
|
||||
silabs,format = <1>; /* LVDS 1v8 */
|
||||
silabs,common-mode = <13>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 8 configuration:
|
||||
* HCSL 3v3
|
||||
*/
|
||||
out@8 {
|
||||
reg = <8>;
|
||||
silabs,format = <2>;
|
||||
silabs,common-mode = <11>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
some-video-node {
|
||||
/* Standard clock bindings */
|
||||
clock-names = "pixel";
|
||||
clocks = <&si5341 0 7>; /* Output 7 */
|
||||
|
||||
/* Set output 7 to use syntesizer 3 as its parent */
|
||||
assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
|
||||
assigned-clock-parents = <&si5341 1 3>;
|
||||
/* Set output 7 to 148.5 MHz using a synth frequency of 594 MHz */
|
||||
assigned-clock-rates = <148500000>, <594000000>;
|
||||
};
|
||||
|
||||
some-audio-node {
|
||||
clock-names = "i2s-clk";
|
||||
clocks = <&si5341 0 0>;
|
||||
/*
|
||||
* since output 0 is a synth-master, the synth will be automatically set
|
||||
* to an appropriate frequency when the audio driver requests another
|
||||
* frequency. We give control over synth 2 to this output here.
|
||||
*/
|
||||
assigned-clocks = <&si5341 0 0>;
|
||||
assigned-clock-parents = <&si5341 1 2>;
|
||||
};
|
||||
@@ -0,0 +1,223 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/silabs,si5341.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silicon Labs Si5340/1/2/4/5 programmable i2c clock generator
|
||||
|
||||
maintainers:
|
||||
- Mike Looijmans <mike.looijmans@topic.nl>
|
||||
|
||||
description: >
|
||||
Silicon Labs Si5340, Si5341 Si5342, Si5344 and Si5345 programmable i2c clock
|
||||
generator.
|
||||
|
||||
Reference
|
||||
[1] Si5341 Data Sheet
|
||||
https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
|
||||
[2] Si5341 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
|
||||
[3] Si5345 Reference Manual
|
||||
https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
|
||||
|
||||
The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
|
||||
clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
|
||||
in turn can be directed to any of the 10 (or 4) outputs through a divider.
|
||||
The internal structure of the clock generators can be found in [2].
|
||||
The Si5345 is similar to the Si5341 with the addition of fractional input
|
||||
dividers and automatic input selection, as described in [3].
|
||||
The Si5342 and Si5344 are smaller versions of the Si5345, with 2 or 4 outputs.
|
||||
|
||||
The driver can be used in "as is" mode, reading the current settings from the
|
||||
chip at boot, in case you have a (pre-)programmed device. If the PLL is not
|
||||
configured when the driver probes, it assumes the driver must fully initialize
|
||||
it.
|
||||
|
||||
The device type, speed grade and revision are determined runtime by probing.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- silabs,si5340
|
||||
- silabs,si5341
|
||||
- silabs,si5342
|
||||
- silabs,si5344
|
||||
- silabs,si5345
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
description: >
|
||||
The first value is "0" for outputs, "1" for synthesizers.
|
||||
|
||||
The second value is the output or synthesizer index.
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: xtal
|
||||
- const: in0
|
||||
- const: in1
|
||||
- const: in2
|
||||
|
||||
clock-output-names: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description: Interrupt for INTRb pin
|
||||
|
||||
vdd-supply:
|
||||
description: Regulator node for VDD
|
||||
|
||||
vdda-supply:
|
||||
description: Regulator node for VDDA
|
||||
|
||||
vdds-supply:
|
||||
description: Regulator node for VDDS
|
||||
|
||||
silabs,pll-m-num:
|
||||
description:
|
||||
Numerator for PLL feedback divider. Must be such that the PLL output is in
|
||||
the valid range. For example, to create 14GHz from a 48MHz xtal, use
|
||||
m-num=14000 and m-den=48. Only the fraction matters, using 3500 and 12
|
||||
will deliver the exact same result. If these are not specified, and the
|
||||
PLL is not yet programmed when the driver probes, the PLL will be set to
|
||||
14GHz.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,pll-m-den:
|
||||
description: Denominator for PLL feedback divider
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,reprogram:
|
||||
description: Always perform soft-reset and reinitialize PLL
|
||||
type: boolean
|
||||
|
||||
silabs,xaxb-ext-clk:
|
||||
description: Use XA/XB pins as external reference clock
|
||||
type: boolean
|
||||
|
||||
silabs,iovdd-33:
|
||||
description: I2C lines use 3.3V thresholds
|
||||
type: boolean
|
||||
|
||||
patternProperties:
|
||||
"^vddo[0-9]-supply$": true
|
||||
|
||||
"^out@[0-9]$":
|
||||
description: >
|
||||
Output-specific override nodes
|
||||
|
||||
Each of the clock outputs can be overwritten individually by using a child
|
||||
node. If a child node for a clock output is not set, the configuration
|
||||
remains unchanged.
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
reg:
|
||||
description: Number of clock output
|
||||
maximum: 9
|
||||
|
||||
always-on:
|
||||
description: Set to keep the clock output always running
|
||||
type: boolean
|
||||
|
||||
silabs,format:
|
||||
description: Output format
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [1, 2, 4]
|
||||
|
||||
silabs,common-mode:
|
||||
description: Override output common mode
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,amplitude:
|
||||
description: Override output amplitude
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
silabs,synth-master:
|
||||
description: Allow dynamic multisynth rate control
|
||||
type: boolean
|
||||
|
||||
silabs,disable-high:
|
||||
description: Drive output HIGH when disabled
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-generator@74 {
|
||||
reg = <0x74>;
|
||||
compatible = "silabs,si5341";
|
||||
#clock-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&ref48>;
|
||||
clock-names = "xtal";
|
||||
|
||||
silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
|
||||
silabs,pll-m-den = <48>;
|
||||
silabs,reprogram; /* Chips are not programmed, always reset */
|
||||
|
||||
out@0 {
|
||||
reg = <0>;
|
||||
silabs,format = <1>; /* LVDS 3v3 */
|
||||
silabs,common-mode = <3>;
|
||||
silabs,amplitude = <3>;
|
||||
silabs,synth-master;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 6 configuration:
|
||||
* LVDS 1v8
|
||||
*/
|
||||
out@6 {
|
||||
reg = <6>;
|
||||
silabs,format = <1>; /* LVDS 1v8 */
|
||||
silabs,common-mode = <13>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Output 8 configuration:
|
||||
* HCSL 3v3
|
||||
*/
|
||||
out@8 {
|
||||
reg = <8>;
|
||||
silabs,format = <2>;
|
||||
silabs,common-mode = <11>;
|
||||
silabs,amplitude = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -1,25 +0,0 @@
|
||||
Binding for Silicon Labs 544 programmable I2C clock generator.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1]. Details about the device can be
|
||||
found in the datasheet[2].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si544 datasheet
|
||||
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: One of "silabs,si514a", "silabs,si514b" "silabs,si514c" according
|
||||
to the speed grade of the chip.
|
||||
- reg: I2C device address.
|
||||
- #clock-cells: From common clock bindings: Shall be 0.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock bindings. Recommended to be "si544".
|
||||
|
||||
Example:
|
||||
si544: clock-controller@55 {
|
||||
reg = <0x55>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si544b";
|
||||
};
|
||||
@@ -0,0 +1,54 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/silabs,si544.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Silicon Labs SI514/SI544 clock generator
|
||||
|
||||
maintainers:
|
||||
- Mike Looijmans <mike.looijmans@topic.nl>
|
||||
|
||||
description: >
|
||||
Silicon Labs 514/544 programmable I2C clock generator. Details about the device
|
||||
can be found in the datasheet:
|
||||
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
|
||||
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- silabs,si514
|
||||
- silabs,si544a
|
||||
- silabs,si544b
|
||||
- silabs,si544c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clock-controller@55 {
|
||||
reg = <0x55>;
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si544b";
|
||||
};
|
||||
};
|
||||
@@ -1,41 +0,0 @@
|
||||
Binding for Silicon Labs 570, 571, 598 and 599 programmable
|
||||
I2C clock generators.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1]. Details about the devices can be
|
||||
found in the data sheets[2][3].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] Si570/571 Data Sheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si570.pdf
|
||||
[3] Si598/599 Data Sheet
|
||||
https://www.silabs.com/Support%20Documents/TechnicalDocs/si598-99.pdf
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall be one of "silabs,si570", "silabs,si571",
|
||||
"silabs,si598", "silabs,si599"
|
||||
- reg: I2C device address.
|
||||
- #clock-cells: From common clock bindings: Shall be 0.
|
||||
- factory-fout: Factory set default frequency. This frequency is part specific.
|
||||
The correct frequency for the part used has to be provided in
|
||||
order to generate the correct output frequencies. For more
|
||||
details, please refer to the data sheet.
|
||||
- temperature-stability: Temperature stability of the device in PPM. Should be
|
||||
one of: 7, 20, 50 or 100.
|
||||
|
||||
Optional properties:
|
||||
- clock-output-names: From common clock bindings. Recommended to be "si570".
|
||||
- clock-frequency: Output frequency to generate. This defines the output
|
||||
frequency set during boot. It can be reprogrammed during
|
||||
runtime through the common clock framework.
|
||||
- silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely
|
||||
on hardware loading of RAM from NVM at power on.
|
||||
|
||||
Example:
|
||||
si570: clock-generator@5d {
|
||||
#clock-cells = <0>;
|
||||
compatible = "silabs,si570";
|
||||
temperature-stability = <50>;
|
||||
reg = <0x5d>;
|
||||
factory-fout = <156250000>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user