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mips: ralink: update CPU clock index

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Update CPU clock index to match the clock driver changes.

Fixes: d34db686a3 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Shiji Yang
2026-04-01 21:51:02 +02:00
committed by Thomas Bogendoerfer
parent 35d8945bf9
commit 43985a62ba
1 changed files with 4 additions and 4 deletions
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arch/mips/ralink/clk.c
+4 -4
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@@ -21,16 +21,16 @@ static const char *clk_cpu(int *idx)
{
switch (ralink_soc) {
case RT2880_SOC:
*idx = 0;
*idx = 1;
return "ralink,rt2880-sysc";
case RT3883_SOC:
*idx = 0;
*idx = 1;
return "ralink,rt3883-sysc";
case RT305X_SOC_RT3050:
*idx = 0;
*idx = 1;
return "ralink,rt3050-sysc";
case RT305X_SOC_RT3052:
*idx = 0;
*idx = 1;
return "ralink,rt3052-sysc";
case RT305X_SOC_RT3350:
*idx = 1;