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Merge tag 'pci-v7.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Browse Source 
Pull pci updates from Bjorn Helgaas:
 "Enumeration:

   - Allow TLP Processing Hints to be enabled for RCiEPs (George Abraham
     P)

   - Enable AtomicOps only if we know the Root Port supports them (Gerd
     Bayer)

   - Don't enable AtomicOps for RCiEPs since none of them need Atomic
     Ops and we can't tell whether the Root Complex would support them
     (Gerd Bayer)

   - Leave Precision Time Measurement disabled until a driver enables it
     to avoid PCIe errors (Mika Westerberg)

   - Make pci_set_vga_state() fail if bridge doesn't support VGA
     routing, i.e., PCI_BRIDGE_CTL_VGA is not writable, and return
     errors to vga_get() callers including userspace via
     /dev/vga_arbiter (Simon Richter)

   - Validate max-link-speed from DT in j721e, brcmstb, mediatek-gen3,
     rzg3s drivers (where the actual controller constraints are known),
     and remove validation from the generic OF DT accessor (Hans Zhang)

   - Remove pc110pad driver (no longer useful after 486 CPU support
     removed) and no_pci_devices() (pc110pad was the last user) (Dmitry
     Torokhov, Heiner Kallweit)

  Resource management:

   - Prevent assigning space to unimplemented bridge windows; previously
     we mistakenly assumed prefetchable window existed and assigned
     space and put a BAR there (Ahmed Naseef)

   - Avoid shrinking bridge windows to fit in the initial Root Port
     window; fixes one problem with devices with large BARs connected
     via switches, e.g., Thunderbolt (Ilpo Järvinen)

   - Pass full extent of empty space, not just the aligned space, to
     resource_alignf callback so free space before the requested
     alignment can be used (Ilpo Järvinen)

   - Place small resources before larger ones for better utilization of
     address space (Ilpo Järvinen)

   - Fix alignment calculation for resource size larger than align,
     e.g., bridge windows larger than the 1MB required alignment (Ilpo
     Järvinen)

  Reset:

   - Update slot handling so all ARI functions are treated as being in
     the same slot. They're all reset by Secondary Bus Reset, but
     previously drivers of ARI functions that appeared to be on a
     non-zero device weren't notified and fatal hardware errors could
     result (Keith Busch)

   - Make sysfs reset_subordinate hotplug safe to avoid spurious hotplug
     events (Keith Busch)

   - Hide Secondary Bus Reset ('bus') from sysfs reset_methods if masked
     by CXL because it has no effect (Vidya Sagar)

   - Avoid FLR for AMD NPU device, where it causes the device to hang
     (Lizhi Hou)

  Error handling:

   - Clear only error bits in PCIe Device Status to avoid accidentally
     clearing Emergency Power Reduction Detected (Shuai Xue)

   - Check for AER errors even in devices without drivers (Lukas Wunner)

   - Initialize ratelimit info so DPC and EDR paths log AER error
     information (Kuppuswamy Sathyanarayanan)

  Power control:

   - Add UPD720201/UPD720202 USB 3.0 xHCI Host Controller .compatible so
     generic pwrctrl driver can control it (Neil Armstrong)

  Hotplug:

   - Set LED_HW_PLUGGABLE for NPEM hotplug-capable ports so LED core
     doesn't complain when setting brightness fails because the endpoint
     is gone (Richard Cheng)

  Peer-to-peer DMA:

   - Allow wildcards in list of host bridges that support peer-to-peer
     DMA between hierarchy domains and add all Google SoCs (Jacob
     Moroni)

  Endpoint framework:

   - Advertise dynamic inbound mapping support in pci-epf-test and
     update host pci_endpoint_test to skip doorbell testing if not
     advertised by endpoint (Koichiro Den)

   - Return 0, not remaining timeout, when MHI eDMA ops complete so
     mhi_ep_ring_add_element() doesn't interpret non-zero as failure
     (Daniel Hodges)

   - Remove vntb and ntb duplicate resource teardown that leads to oops
     when .allow_link() fails or .drop_link() is called (Koichiro Den)

   - Disable vntb delayed work before clearing BAR mappings and
     doorbells to avoid oops caused by doing the work after resources
     have been torn down (Koichiro Den)

   - Add a way to describe reserved subregions within BARs, e.g.,
     platform-owned fixed register windows, and use it for the RK3588
     BAR4 DMA ctrl window (Koichiro Den)

   - Add BAR_DISABLED for BARs that will never be available to an EPF
     driver, and change some BAR_RESERVED annotations to BAR_DISABLED
     (Niklas Cassel)

   - Add NTB .get_dma_dev() callback for cases where DMA API requires a
     different device, e.g., vNTB devices (Koichiro Den)

   - Add reserved region types for MSI-X Table and PBA so Endpoint
     controllers can them as describe hardware-owned regions in a
     BAR_RESERVED BAR (Manikanta Maddireddy)

   - Make Tegra194/234 BAR0 programmable and remove 1MB size limit
     (Manikanta Maddireddy)

   - Expose Tegra BAR2 (MSI-X) and BAR4 (DMA) as 64-bit BAR_RESERVED
     (Manikanta Maddireddy)

   - Add Tegra194 and Tegra234 device table entries to pci_endpoint_test
     (Manikanta Maddireddy)

   - Skip the BAR subrange selftest if there are not enough inbound
     window resources to run the test (Christian Bruel)

  New native PCIe controller drivers:

   - Add DT binding and driver for Andes QiLai SoC PCIe host controller
     (Randolph Lin)

   - Add DT binding and driver for ESWIN PCIe Root Complex (Senchuan
     Zhang)

  Baikal T-1 PCIe controller driver:

   - Remove driver since it never quite became usable (Andy Shevchenko)

  Cadence PCIe controller driver:

   - Implement byte/word config reads with dword (32-bit) reads because
     some Cadence controllers don't support sub-dword accesses (Aksh
     Garg)

  CIX Sky1 PCIe controller driver:

   - Add 'power-domains' to DT binding for SCMI power domain (Gary Yang)

  Freescale i.MX6 PCIe controller driver:

   - Add i.MX94 and i.MX943 to fsl,imx6q-pcie-ep DT binding (Richard
     Zhu)

   - Delay instead of polling for L2/L3 Ready after PME_Turn_off when
     suspending i.MX6SX because LTSSM registers are inaccessible
     (Richard Zhu)

   - Separate PERST# assertion (for resetting endpoints) from core reset
     (for resetting the RC itself) to prepare for new DTs with PERST#
     GPIO in per-Root Port nodes (Sherry Sun)

   - Retain Root Port MSI capability on i.MX7D, i.MX8MM, and i.MX8MQ so
     MSI from downstream devices will work (Richard Zhu)

   - Fix i.MX95 reference clock source selection when internal refclk is
     used (Franz Schnyder)

  Freescale Layerscape PCIe controller driver:

   - Allow building as a removable module (Sascha Hauer)

  MediaTek PCIe Gen3 controller driver:

   - Use dev_err_probe() to simplify error paths and make deferred probe
     messages visible in /sys/kernel/debug/devices_deferred (Chen-Yu
     Tsai)

   - Power off device if setup fails (Chen-Yu Tsai)

   - Integrate new pwrctrl API to enable power control for WiFi/BT
     adapters on mainboard or in PCIe or M.2 slots (Chen-Yu Tsai)

  NVIDIA Tegra194 PCIe controller driver:

   - Poll less aggressively and non-atomically for PME_TO_Ack during
     transition to L2 (Vidya Sagar)

   - Disable LTSSM after transition to Detect on surprise link down to
     stop toggling between Polling and Detect (Manikanta Maddireddy)

   - Don't force the device into the D0 state before L2 when suspending
     or shutting down the controller (Vidya Sagar)

   - Disable PERST# IRQ only in Endpoint mode because it's not
     registered in Root Port mode (Manikanta Maddireddy)

   - Handle 'nvidia,refclk-select' as optional (Vidya Sagar)

   - Disable direct speed change in Endpoint mode so link speed change
     is controlled by the host (Vidya Sagar)

   - Set LTR values before link up to avoid bogus LTR messages with 0
     latency (Vidya Sagar)

   - Allow system suspend when the Endpoint link is down (Vidya Sagar)

   - Use DWC IP core version, not Tegra custom values, to avoid DWC core
     version check warnings (Manikanta Maddireddy)

   - Apply ECRC workaround to devices based on DesignWare 5.00a as well
     as 4.90a (Manikanta Maddireddy)

   - Disable PM Substate L1.2 in Endpoint mode to work around Tegra234
     erratum (Vidya Sagar)

   - Delay post-PERST# cleanup until core is powered on to avoid CBB
     timeout (Manikanta Maddireddy)

   - Assert CLKREQ# so switches that forward it to their downstream side
     can bring up those links successfully (Vidya Sagar)

   - Calibrate pipe to UPHY for Endpoint mode to reset stale PLL state
     from any previous bad link state (Vidya Sagar)

   - Remove IRQF_ONESHOT flag from Endpoint interrupt registration so
     DMA driver and Endpoint controller driver can share the interrupt
     line (Vidya Sagar)

   - Enable DMA interrupt to support DMA in both Root Port and Endpoint
     modes (Vidya Sagar)

   - Enable hardware link retraining after link goes down in Endpoint
     mode (Vidya Sagar)

   - Add DT binding and driver support for core clock monitoring (Vidya
     Sagar)

  Qualcomm PCIe controller driver:

   - Advertise 'Hot-Plug Capable' and set 'No Command Completed Support'
     since Qcom Root Ports support hotplug events like DL_Up/Down and
     can accept writes to Slot Control without delays between writes
     (Krishna Chaitanya Chundru)

  Renesas R-Car PCIe controller driver:

   - Mark Endpoint BAR0 and BAR2 as Resizable (Koichiro Den)

   - Reduce EPC BAR alignment requirement to 4K (Koichiro Den)

  Renesas RZ/G3S PCIe controller driver:

   - Add RZ/G3E to DT binding and to driver (John Madieu)

   - Assert (not deassert) resets in probe error path (John Madieu)

   - Assert resets in suspend path in reverse order they were deasserted
     during probe (John Madieu)

   - Rework inbound window algorithm to prevent mapping more than
     intended region and enforce alignment on size, to prepare for
     RZ/G3E support (John Madieu)

  Rockchip DesignWare PCIe controller driver:

   - Add tracepoints for PCIe controller LTSSM transitions and link rate
     changes (Shawn Lin)

   - Trace LTSSM events collected by the dw-rockchip debug FIFO (Shawn
     Lin)

  SOPHGO PCIe controller driver:

   - Disable ASPM L0s and L1 on Sophgo 2042 PCIe Root Ports that
     advertise support for them (Yao Zi)

  Synopsys DesignWare PCIe controller driver:

   - Continue with system suspend even if an Endpoint doesn't respond
     with PME_TO_Ack message (Manivannan Sadhasivam)

   - Set Endpoint MSI-X Table Size in the correct function of a
     multi-function device when configuring MSI-X, not in Function 0
     (Aksh Garg)

   - Set Max Link Width and Max Link Speed for all functions of a
     multi-function device, not just Function 0 (Aksh Garg)

   - Expose PCIe event counters in groups 5-7 in debugfs (Hans Zhang)

  Miscellaneous:

   - Warn only once about invalid ACS kernel parameter format (Richard
     Cheng)

   - Suppress FW_BUG warning when writing sysfs 'numa_node' with the
     current value (Li RongQing)

   - Drop redundant 'depends on PCI' from Kconfig (Julian Braha)"

* tag 'pci-v7.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (165 commits)
  PCI/P2PDMA: Add Google SoCs to the P2P DMA host bridge list
  PCI/P2PDMA: Allow wildcard Device IDs in host bridge list
  PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports
  PCI: cadence: Add flags for disabling ASPM capability for broken Root Ports
  PCI: tegra194: Add core monitor clock support
  dt-bindings: PCI: tegra194: Add monitor clock support
  PCI: tegra194: Enable hardware hot reset mode in Endpoint mode
  PCI: tegra194: Enable DMA interrupt
  PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration
  PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode
  PCI: tegra194: Assert CLKREQ# explicitly by default
  PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on
  PCI: tegra194: Disable L1.2 capability of Tegra234 EP
  PCI: dwc: Apply ECRC workaround to DesignWare 5.00a as well
  PCI: tegra194: Use DWC IP core version
  PCI: tegra194: Free up Endpoint resources during remove()
  PCI: tegra194: Allow system suspend when the Endpoint link is not up
  PCI: tegra194: Set LTR message request before PCIe link up in Endpoint mode
  PCI: tegra194: Disable direct speed change for Endpoint mode
  PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select"
  ...
This commit is contained in:
Linus Torvalds
2026-04-15 14:41:21 -07:00
parent 46576fa329 4224e91fea
commit 40286d6379
117 changed files with 2979 additions and 2032 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/PCI/msi-howto.rst
+5 -2
View File
@@ -113,8 +113,11 @@ vectors, use the following function::
int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
Any allocated resources should be freed before removing the device using
the following function::
If the driver enables the device using pcim_enable_device(), the driver
shouldn't call pci_free_irq_vectors() because pcim_enable_device()
activates automatic management for IRQ vectors. Otherwise, the driver should
free any allocated IRQ vectors before removing the device using the following
function::
void pci_free_irq_vectors(struct pci_dev *dev);
Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
+89
View File
@@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/andestech,qilai-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andes QiLai PCIe host controller
description:
Andes QiLai PCIe host controller is based on the Synopsys DesignWare
PCI core.
maintainers:
- Randolph Lin <randolph@andestech.com>
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
const: andestech,qilai-pcie
reg:
items:
- description: Data Bus Interface (DBI) registers.
- description: APB registers.
- description: PCIe configuration space region.
reg-names:
items:
- const: dbi
- const: apb
- const: config
dma-coherent: true
ranges:
maxItems: 2
interrupts:
maxItems: 1
interrupt-names:
items:
- const: msi
required:
- reg
- reg-names
- interrupts
- interrupt-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie@80000000 {
compatible = "andestech,qilai-pcie";
device_type = "pci";
reg = <0x0 0x80000000 0x0 0x20000000>,
<0x0 0x04000000 0x0 0x00001000>,
<0x0 0x00000000 0x0 0x00010000>;
reg-names = "dbi", "apb", "config";
dma-coherent;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
<0x43000000 0x01 0x00000000 0x01 0x00000000 0x02 0x00000000>;
#interrupt-cells = <1>;
interrupts = <0xf>;
interrupt-names = "msi";
interrupt-parent = <&plic0>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 1 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &plic0 0xf IRQ_TYPE_LEVEL_HIGH>;
};
};
...
Documentation/devicetree/bindings/pci/baikal,bt1-pcie.yaml
-168
View File
@@ -1,168 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 PCIe Root Port Controller
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description:
Embedded into Baikal-T1 SoC Root Complex controller with a single port
activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
to have just a single Root Port function and is capable of establishing the
link up to Gen.3 speed on x4 lanes. It doesn't have embedded clock and reset
control module, so the proper interface initialization is supposed to be
performed by software. There four in- and four outbound iATU regions
which can be used to emit all required TLP types on the PCIe bus.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
properties:
compatible:
const: baikal,bt1-pcie
reg:
description:
DBI, DBI2 and at least 4KB outbound iATU-capable region for the
peripheral devices CFG-space access.
maxItems: 3
reg-names:
items:
- const: dbi
- const: dbi2
- const: config
interrupts:
description:
MSI, AER, PME, Hot-plug, Link Bandwidth Management, Link Equalization
request and eight Read/Write eDMA IRQ lines are available.
maxItems: 14
interrupt-names:
items:
- const: dma0
- const: dma1
- const: dma2
- const: dma3
- const: dma4
- const: dma5
- const: dma6
- const: dma7
- const: msi
- const: aer
- const: pme
- const: hp
- const: bw_mg
- const: l_eq
clocks:
description:
DBI (attached to the APB bus), AXI-bus master and slave interfaces
are fed up by the dedicated application clocks. A common reference
clock signal is supposed to be attached to the corresponding Ref-pad
of the SoC. It will be redistributed amongst the controller core
sub-modules (pipe, core, aux, etc).
maxItems: 4
clock-names:
items:
- const: dbi
- const: mstr
- const: slv
- const: ref
resets:
description:
A comprehensive controller reset logic is supposed to be implemented
by software, so almost all the possible application and core reset
signals are exposed via the system CCU module.
maxItems: 9
reset-names:
items:
- const: mstr
- const: slv
- const: pwr
- const: hot
- const: phy
- const: core
- const: pipe
- const: sticky
- const: non-sticky
baikal,bt1-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the Baikal-T1 System Controller DT node. It's required to
access some additional PM, Reset-related and LTSSM signals.
num-lanes:
maximum: 4
max-link-speed:
maximum: 3
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/gpio/gpio.h>
pcie@1f052000 {
compatible = "baikal,bt1-pcie";
device_type = "pci";
reg = <0x1f052000 0x1000>, <0x1f053000 0x1000>, <0x1bdbf000 0x1000>;
reg-names = "dbi", "dbi2", "config";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x00000000 0x1bdb0000 0 0x00008000>,
<0x82000000 0 0x20000000 0x08000000 0 0x13db0000>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SHARED 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SHARED 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma0", "dma1", "dma2", "dma3",
"dma4", "dma5", "dma6", "dma7",
"msi", "aer", "pme", "hp", "bw_mg",
"l_eq";
clocks = <&ccu_sys 1>, <&ccu_axi 6>, <&ccu_axi 7>, <&clk_pcie>;
clock-names = "dbi", "mstr", "slv", "ref";
resets = <&ccu_axi 6>, <&ccu_axi 7>, <&ccu_sys 7>, <&ccu_sys 10>,
<&ccu_sys 4>, <&ccu_sys 6>, <&ccu_sys 5>, <&ccu_sys 8>,
<&ccu_sys 9>;
reset-names = "mstr", "slv", "pwr", "hot", "phy", "core", "pipe",
"sticky", "non-sticky";
reset-gpios = <&port0 0 GPIO_ACTIVE_LOW>;
num-lanes = <4>;
max-link-speed = <3>;
};
...
Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml
+3
View File
@@ -38,6 +38,9 @@ properties:
ranges:
maxItems: 3
power-domains:
maxItems: 1
required:
- compatible
- ranges
Documentation/devicetree/bindings/pci/eswin,pcie.yaml
+166
View File
@@ -0,0 +1,166 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/eswin,pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ESWIN PCIe Root Complex
maintainers:
- Yu Ning <ningyu@eswincomputing.com>
- Senchuan Zhang <zhangsenchuan@eswincomputing.com>
- Yanghui Ou <ouyanghui@eswincomputing.com>
description:
ESWIN SoCs PCIe Root Complex is based on the Synopsys DesignWare PCIe IP.
properties:
compatible:
const: eswin,eic7700-pcie
reg:
maxItems: 3
reg-names:
items:
- const: dbi
- const: config
- const: elbi
ranges:
maxItems: 3
'#interrupt-cells':
const: 1
interrupt-names:
items:
- const: msi
- const: inta
- const: intb
- const: intc
- const: intd
interrupt-map:
maxItems: 4
interrupt-map-mask:
items:
- const: 0
- const: 0
- const: 0
- const: 7
clocks:
maxItems: 4
clock-names:
items:
- const: mstr
- const: dbi
- const: phy_reg
- const: aux
resets:
maxItems: 2
reset-names:
items:
- const: dbi
- const: pwr
patternProperties:
"^pcie@":
type: object
$ref: /schemas/pci/pci-pci-bridge.yaml#
properties:
reg:
maxItems: 1
num-lanes:
maximum: 4
resets:
maxItems: 1
reset-names:
items:
- const: perst
required:
- reg
- ranges
- num-lanes
- resets
- reset-names
unevaluatedProperties: false
required:
- compatible
- reg
- ranges
- interrupts
- interrupt-names
- interrupt-map-mask
- interrupt-map
- '#interrupt-cells'
- clocks
- clock-names
- resets
- reset-names
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
unevaluatedProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie@54000000 {
compatible = "eswin,eic7700-pcie";
reg = <0x0 0x54000000 0x0 0x4000000>,
<0x0 0x40000000 0x0 0x800000>,
<0x0 0x50000000 0x0 0x100000>;
reg-names = "dbi", "config", "elbi";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x01000000 0x0 0x40800000 0x0 0x40800000 0x0 0x800000>,
<0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0xf000000>,
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x2 0x00000000>;
bus-range = <0x00 0xff>;
clocks = <&clock 144>,
<&clock 145>,
<&clock 146>,
<&clock 147>;
clock-names = "mstr", "dbi", "phy_reg", "aux";
resets = <&reset 97>,
<&reset 98>;
reset-names = "dbi", "pwr";
interrupts = <220>, <179>, <180>, <181>, <182>, <183>, <184>, <185>, <186>;
interrupt-names = "msi", "inta", "intb", "intc", "intd";
interrupt-parent = <&plic>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &plic 179>,
<0x0 0x0 0x0 0x2 &plic 180>,
<0x0 0x0 0x0 0x3 &plic 181>,
<0x0 0x0 0x0 0x4 &plic 182>;
device_type = "pci";
pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
device_type = "pci";
num-lanes = <4>;
resets = <&reset 99>;
reset-names = "perst";
};
};
};
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
+2 -2
View File
@@ -17,11 +17,11 @@ description:
properties:
clocks:
minItems: 3
maxItems: 5
maxItems: 6
clock-names:
minItems: 3
maxItems: 5
maxItems: 6
num-lanes:
const: 1
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
+12 -6
View File
@@ -18,12 +18,18 @@ description: |+
properties:
compatible:
enum:
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8mp-pcie-ep
- fsl,imx8q-pcie-ep
- fsl,imx95-pcie-ep
oneOf:
- enum:
- fsl,imx8mm-pcie-ep
- fsl,imx8mp-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8q-pcie-ep
- fsl,imx95-pcie-ep
- items:
- enum:
- fsl,imx94-pcie-ep
- fsl,imx943-pcie-ep
- const: fsl,imx95-pcie-ep
clocks:
minItems: 3
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+18 -11
View File
@@ -21,16 +21,22 @@ description: |+
properties:
compatible:
enum:
- fsl,imx6q-pcie
- fsl,imx6sx-pcie
- fsl,imx6qp-pcie
- fsl,imx7d-pcie
- fsl,imx8mq-pcie
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
- fsl,imx95-pcie
- fsl,imx8q-pcie
oneOf:
- enum:
- fsl,imx6q-pcie
- fsl,imx6qp-pcie
- fsl,imx6sx-pcie
- fsl,imx7d-pcie
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
- fsl,imx8mq-pcie
- fsl,imx8q-pcie
- fsl,imx95-pcie
- items:
- enum:
- fsl,imx94-pcie
- fsl,imx943-pcie
- const: fsl,imx95-pcie
clocks:
minItems: 3
@@ -40,7 +46,8 @@ properties:
- description: PCIe PHY clock.
- description: Additional required clock entry for imx6sx-pcie,
imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
- description: PCIe reference clock.
- description: PCIe internal reference clock.
- description: PCIe additional external reference clock.
clock-names:
minItems: 3
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
+5 -1
View File
@@ -55,12 +55,16 @@ properties:
- const: intr
clocks:
minItems: 1
items:
- description: module clock
- description: core clock
- description: monitor clock
clock-names:
minItems: 1
items:
- const: core
- const: core_m
resets:
items:
Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
+5 -1
View File
@@ -58,12 +58,16 @@ properties:
- const: msi
clocks:
minItems: 1
items:
- description: module clock
- description: core clock
- description: monitor clock
clock-names:
minItems: 1
items:
- const: core
- const: core_m
resets:
items:
Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
+91 -30
View File
@@ -10,17 +10,21 @@ maintainers:
- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
description:
Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification
4.0 and supports up to 5 GT/s (Gen2).
Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
up to 8 GT/s (Gen3) for RZ/G3E.
properties:
compatible:
const: renesas,r9a08g045-pcie # RZ/G3S
enum:
- renesas,r9a08g045-pcie # RZ/G3S
- renesas,r9a09g047-pcie # RZ/G3E
reg:
maxItems: 1
interrupts:
minItems: 16
items:
- description: System error interrupt
- description: System error on correctable error interrupt
@@ -38,39 +42,55 @@ properties:
- description: PCIe event interrupt
- description: Message interrupt
- description: All interrupts
- description: Link equalization request interrupt
- description: Turn off event interrupt
- description: PMU power off interrupt
- description: D3 event function 0 interrupt
- description: D3 event function 1 interrupt
- description: Configuration PMCSR write clear function 0 interrupt
- description: Configuration PMCSR write clear function 1 interrupt
interrupt-names:
minItems: 16
items:
- description: serr
- description: ser_cor
- description: serr_nonfatal
- description: serr_fatal
- description: axi_err
- description: inta
- description: intb
- description: intc
- description: intd
- description: msi
- description: link_bandwidth
- description: pm_pme
- description: dma
- description: pcie_evt
- description: msg
- description: all
- const: serr
- const: serr_cor
- const: serr_nonfatal
- const: serr_fatal
- const: axi_err
- const: inta
- const: intb
- const: intc
- const: intd
- const: msi
- const: link_bandwidth
- const: pm_pme
- const: dma
- const: pcie_evt
- const: msg
- const: all
- const: link_equalization_request
- const: turn_off_event
- const: pmu_poweroff
- const: d3_event_f0
- const: d3_event_f1
- const: cfg_pmcsr_writeclear_f0
- const: cfg_pmcsr_writeclear_f1
interrupt-controller: true
clocks:
items:
- description: System clock
- description: PM control clock
- description: PM control clock or clock for L1 substate handling
clock-names:
items:
- description: aclk
- description: pm
- const: aclk
- enum: [pm, pmu]
resets:
minItems: 1
items:
- description: AXI2PCIe Bridge reset
- description: Data link layer/transaction layer reset
@@ -81,14 +101,15 @@ properties:
- description: Configuration register reset
reset-names:
minItems: 1
items:
- description: aresetn
- description: rst_b
- description: rst_gp_b
- description: rst_ps_b
- description: rst_rsm_b
- description: rst_cfg_b
- description: rst_load_b
- const: aresetn
- const: rst_b
- const: rst_gp_b
- const: rst_ps_b
- const: rst_rsm_b
- const: rst_cfg_b
- const: rst_load_b
power-domains:
maxItems: 1
@@ -128,7 +149,9 @@ patternProperties:
const: 0x1912
device-id:
const: 0x0033
enum:
- 0x0033
- 0x0039
clocks:
items:
@@ -167,6 +190,44 @@ required:
allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
- if:
properties:
compatible:
contains:
const: renesas,r9a08g045-pcie
then:
properties:
interrupts:
maxItems: 16
interrupt-names:
maxItems: 16
clock-names:
items:
- const: aclk
- const: pm
resets:
minItems: 7
reset-names:
minItems: 7
- if:
properties:
compatible:
contains:
const: renesas,r9a09g047-pcie
then:
properties:
interrupts:
minItems: 23
interrupt-names:
minItems: 23
clock-names:
items:
- const: aclk
- const: pmu
resets:
maxItems: 1
reset-names:
maxItems: 1
unevaluatedProperties: false
Documentation/trace/events-pci-controller.rst
+42
View File
@@ -0,0 +1,42 @@
.. SPDX-License-Identifier: GPL-2.0
======================================
Subsystem Trace Points: PCI Controller
======================================
Overview
========
The PCI controller tracing system provides tracepoints to monitor controller
level information for debugging purpose. The events normally show up here:
/sys/kernel/tracing/events/pci_controller
Cf. include/trace/events/pci_controller.h for the events definitions.
Available Tracepoints
=====================
pcie_ltssm_state_transition
---------------------------
Monitors PCIe LTSSM state transition including state and rate information
::
pcie_ltssm_state_transition "dev: %s state: %s rate: %s\n"
**Parameters**:
* ``dev`` - PCIe controller instance
* ``state`` - PCIe LTSSM state
* ``rate`` - PCIe date rate
**Example Usage**:
.. code-block:: shell
# Enable the tracepoint
echo 1 > /sys/kernel/debug/tracing/events/pci_controller/pcie_ltssm_state_transition/enable
# Monitor events (the following output is generated when a device is linking)
cat /sys/kernel/debug/tracing/trace_pipe
kworker/0:0-9 [000] ..... 5.600221: pcie_ltssm_state_transition: dev: a40000000.pcie state: RCVRY_EQ2 rate: 8.0 GT/s
Documentation/trace/index.rst
+1
View File
@@ -55,6 +55,7 @@ applications.
events-nmi
events-msr
events-pci
events-pci-controller
boottime-trace
histogram
histogram-design
MAINTAINERS
+16
View File
@@ -20259,6 +20259,13 @@ S: Orphan
F: Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
F: drivers/pci/controller/pcie-altera.c
PCI DRIVER FOR ANDES QILAI PCIE
M: Randolph Lin <randolph@andestech.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
F: drivers/pci/controller/dwc/pcie-andes-qilai.c
PCI DRIVER FOR APPLIEDMICRO XGENE
M: Toan Le <toan@os.amperecomputing.com>
L: linux-pci@vger.kernel.org
@@ -20526,9 +20533,11 @@ C: irc://irc.oftc.net/linux-pci
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
F: Documentation/ABI/testing/debugfs-pcie-ptm
F: Documentation/devicetree/bindings/pci/
F: Documentation/trace/events-pci-controller.rst
F: drivers/pci/controller/
F: drivers/pci/pci-bridge-emul.c
F: drivers/pci/pci-bridge-emul.h
F: include/trace/events/pci_controller.h
PCI PEER-TO-PEER DMA (P2PDMA)
M: Bjorn Helgaas <bhelgaas@google.com>
@@ -20624,6 +20633,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Odd Fixes
F: drivers/pci/controller/pci-thunder-*
PCIE DRIVER FOR ESWIN
M: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/eswin,pcie.yaml
F: drivers/pci/controller/dwc/pcie-eswin.c
PCIE DRIVER FOR HISILICON
M: Zhou Wang <wangzhou1@hisilicon.com>
L: linux-pci@vger.kernel.org
arch/alpha/kernel/pci.c
+1
View File
@@ -125,6 +125,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
const struct resource *empty_res,
resource_size_t size, resource_size_t align)
{
struct pci_dev *dev = data;
arch/arm/kernel/bios32.c
+6 -3
View File
@@ -560,7 +560,9 @@ char * __init pcibios_setup(char *str)
* which might be mirrored at 0x0100-0x03ff..
*/
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
const struct resource *empty_res,
resource_size_t size,
resource_size_t align)
{
struct pci_dev *dev = data;
resource_size_t start = res->start;
@@ -569,14 +571,15 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
if (res->flags & IORESOURCE_IO && start & 0x300)
start = (start + 0x3ff) & ~0x3ff;
start = (start + align - 1) & ~(align - 1);
host_bridge = pci_find_host_bridge(dev->bus);
if (host_bridge->align_resource)
return host_bridge->align_resource(dev, res,
start, size, align);
if (res->flags & IORESOURCE_MEM)
return pci_align_resource(dev, res, empty_res, size, align);
return start;
}
arch/m68k/kernel/pcibios.c
+6 -2
View File
@@ -27,14 +27,18 @@
* which might be mirrored at 0x0100-0x03ff..
*/
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
const struct resource *empty_res,
resource_size_t size,
resource_size_t align)
{
struct pci_dev *dev = data;
resource_size_t start = res->start;
if ((res->flags & IORESOURCE_IO) && (start & 0x300))
start = (start + 0x3ff) & ~0x3ff;
start = (start + align - 1) & ~(align - 1);
if (res->flags & IORESOURCE_MEM)
return pci_align_resource(dev, res, empty_res, size, align);
return start;
}
arch/mips/pci/pci-generic.c
+5 -3
View File
@@ -22,7 +22,8 @@
* which might have be mirrored at 0x0100-0x03ff..
*/
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
const struct resource *empty_res,
resource_size_t size, resource_size_t align)
{
struct pci_dev *dev = data;
resource_size_t start = res->start;
@@ -31,14 +32,15 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
if (res->flags & IORESOURCE_IO && start & 0x300)
start = (start + 0x3ff) & ~0x3ff;
start = (start + align - 1) & ~(align - 1);
host_bridge = pci_find_host_bridge(dev->bus);
if (host_bridge->align_resource)
return host_bridge->align_resource(dev, res,
start, size, align);
if (res->flags & IORESOURCE_MEM)
return pci_align_resource(dev, res, empty_res, size, align);
return start;
}
arch/mips/pci/pci-legacy.c
+3
View File
@@ -52,6 +52,7 @@ unsigned long pci_address_to_pio(phys_addr_t address)
*/
resource_size_t
pcibios_align_resource(void *data, const struct resource *res,
const struct resource *empty_res,
resource_size_t size, resource_size_t align)
{
struct pci_dev *dev = data;
@@ -69,6 +70,8 @@ pcibios_align_resource(void *data, const struct resource *res,
if (start & 0x300)
start = (start + 0x3ff) & ~0x3ff;
} else if (res->flags & IORESOURCE_MEM) {
start = pci_align_resource(dev, res, empty_res, size, align);
/* Make sure we start at our min on all hoses */
if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
arch/parisc/kernel/pci.c
+10 -7
View File
@@ -8,6 +8,7 @@
* Copyright (C) 1999-2001 Hewlett-Packard Company
* Copyright (C) 1999-2001 Grant Grundler
*/
#include <linux/align.h>
#include <linux/eisa.h>
#include <linux/init.h>
#include <linux/module.h>
@@ -196,9 +197,12 @@ void __ref pcibios_init_bridge(struct pci_dev *dev)
* than res->start.
*/
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t alignment)
const struct resource *empty_res,
resource_size_t size,
resource_size_t alignment)
{
resource_size_t mask, align, start = res->start;
struct pci_dev *dev = data;
resource_size_t align, start = res->start;
DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
pci_name(((struct pci_dev *) data)),
@@ -207,11 +211,10 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
/* If it's not IO, then it's gotta be MEM */
align = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
/* Align to largest of MIN or input size */
mask = max(alignment, align) - 1;
start += mask;
start &= ~mask;
if (align > alignment)
start = ALIGN(start, align);
else
start = pci_align_resource(dev, res, empty_res, size, alignment);
return start;
}

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