mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'armsoc-fixes-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"This is a larger than normal update for Arm SoC specific code, most of
it in device trees, but also drivers and the omap and at91/sama7
platforms:
- There are four new entries to the MAINTAINERS file: Sven Peter and
Alyssa Rosenzweig for Apple M1, Romain Perier for Mstar/sigmastar,
and Vignesh Raghavendra for TI K3
- Build fixes to address randconfig warnings in sharpsl, dove, omap1,
and qcom platforms as well as the scmi and op-tee subsystems
- Regression fixes for missing CONFIG_FB and other options for
several defconfigs
- Several bug fixes for the newly added Microchip SAMA7 platform,
mostly regarding power management
- Missing SMP barriers to protect accesses to SCMI virtio device
- Regression fixes for TI OMAP, including a boot-time hang on am335x.
- Lots of bug fixes for NXP i.MX, mostly addressing incorrect
settings in devicetree files, and one revert for broken suspend.
- Fixes for ARM Juno/Vexpress devicetree files, addressing a couple
of schema warnings.
- Regression fixes for qualcomm SoC specific drivers and devicetree
files, reverting an mdt_loader change and at least pastially
reverting some of the 5.15 DTS changes, plus some minor bugfixes"
* tag 'armsoc-fixes-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (64 commits)
MAINTAINERS: Add Sven Peter as ARM/APPLE MACHINE maintainer
MAINTAINERS: Add Alyssa Rosenzweig as M1 reviewer
firmware: arm_scmi: Add proper barriers to scmi virtio device
firmware: arm_scmi: Simplify spinlocks in virtio transport
ARM: dts: omap3430-sdp: Fix NAND device node
bus: ti-sysc: Use CLKDM_NOAUTO for dra7 dcan1 for errata i893
ARM: sharpsl_param: work around -Wstringop-overread warning
ARM: defconfig: gemini: Restore framebuffer
ARM: dove: mark 'putc' as inline
ARM: omap1: move omap15xx local bus handling to usb.c
MAINTAINERS: Add Vignesh to TI K3 platform maintainership
arm64: dts: imx8m*-venice-gw7902: fix M2_RST# gpio
ARM: imx6: disable the GIC CPU interface before calling stby-poweroff sequence
arm64: dts: ls1028a: fix eSDHC2 node
arm64: dts: imx8mm-kontron-n801x-som: do not allow to switch off buck2
ARM: dts: at91: sama7g5ek: to not touch slew-rate for SDMMC pins
ARM: dts: at91: sama7g5ek: use proper slew-rate settings for GMACs
ARM: at91: pm: preload base address of controllers in tlb
ARM: at91: pm: group constants and addresses loading
ARM: dts: at91: sama7g5ek: add suspend voltage for ddr3l rail
...
This commit is contained in:
Linus Torvalds committed
commit
3e899c7209
64 files changed
+667
-583
No files matched your search
@@ -1276,6 +1276,7 @@ F: drivers/input/mouse/bcm5974.c
|
||||
|
||||
APPLE DART IOMMU DRIVER
|
||||
M: Sven Peter <sven@svenpeter.dev>
|
||||
R: Alyssa Rosenzweig <alyssa@rosenzweig.io>
|
||||
L: iommu@lists.linux-foundation.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/iommu/apple,dart.yaml
|
||||
@@ -1712,6 +1713,8 @@ F: drivers/*/*alpine*
|
||||
|
||||
ARM/APPLE MACHINE SUPPORT
|
||||
M: Hector Martin <marcan@marcan.st>
|
||||
M: Sven Peter <sven@svenpeter.dev>
|
||||
R: Alyssa Rosenzweig <alyssa@rosenzweig.io>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
W: https://asahilinux.org
|
||||
@@ -2237,6 +2240,7 @@ F: arch/arm/mach-pxa/mioa701.c
|
||||
|
||||
ARM/MStar/Sigmastar Armv7 SoC support
|
||||
M: Daniel Palmer <daniel@thingy.jp>
|
||||
M: Romain Perier <romain.perier@gmail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
W: http://linux-chenxing.org/
|
||||
@@ -2713,6 +2717,7 @@ F: drivers/power/reset/keystone-reset.c
|
||||
|
||||
ARM/TEXAS INSTRUMENTS K3 ARCHITECTURE
|
||||
M: Nishanth Menon <nm@ti.com>
|
||||
M: Vignesh Raghavendra <vigneshr@ti.com>
|
||||
M: Tero Kristo <kristo@kernel.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
|
||||
@@ -71,7 +71,6 @@
|
||||
isc: isc@f0008000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
qspi1: spi@f0024000 {
|
||||
|
||||
@@ -196,11 +196,13 @@
|
||||
|
||||
regulator-state-standby {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1350000>;
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1350000>;
|
||||
regulator-mode = <4>;
|
||||
};
|
||||
};
|
||||
@@ -353,7 +355,10 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txck_default &pinctrl_gmac0_phy_irq>;
|
||||
pinctrl-0 = <&pinctrl_gmac0_default
|
||||
&pinctrl_gmac0_mdio_default
|
||||
&pinctrl_gmac0_txck_default
|
||||
&pinctrl_gmac0_phy_irq>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
|
||||
@@ -368,7 +373,9 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gmac1_default &pinctrl_gmac1_phy_irq>;
|
||||
pinctrl-0 = <&pinctrl_gmac1_default
|
||||
&pinctrl_gmac1_mdio_default
|
||||
&pinctrl_gmac1_phy_irq>;
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
|
||||
@@ -423,14 +430,20 @@
|
||||
<PIN_PA15__G0_TXEN>,
|
||||
<PIN_PA30__G0_RXCK>,
|
||||
<PIN_PA18__G0_RXDV>,
|
||||
<PIN_PA22__G0_MDC>,
|
||||
<PIN_PA23__G0_MDIO>,
|
||||
<PIN_PA25__G0_125CK>;
|
||||
slew-rate = <0>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_gmac0_mdio_default: gmac0_mdio_default {
|
||||
pinmux = <PIN_PA22__G0_MDC>,
|
||||
<PIN_PA23__G0_MDIO>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_gmac0_txck_default: gmac0_txck_default {
|
||||
pinmux = <PIN_PA24__G0_TXCK>;
|
||||
slew-rate = <0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
@@ -447,8 +460,13 @@
|
||||
<PIN_PD25__G1_RX0>,
|
||||
<PIN_PD26__G1_RX1>,
|
||||
<PIN_PD27__G1_RXER>,
|
||||
<PIN_PD24__G1_RXDV>,
|
||||
<PIN_PD28__G1_MDC>,
|
||||
<PIN_PD24__G1_RXDV>;
|
||||
slew-rate = <0>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pinctrl_gmac1_mdio_default: gmac1_mdio_default {
|
||||
pinmux = <PIN_PD28__G1_MDC>,
|
||||
<PIN_PD29__G1_MDIO>;
|
||||
bias-disable;
|
||||
};
|
||||
@@ -540,6 +558,7 @@
|
||||
<PIN_PA8__SDMMC0_DAT5>,
|
||||
<PIN_PA9__SDMMC0_DAT6>,
|
||||
<PIN_PA10__SDMMC0_DAT7>;
|
||||
slew-rate = <0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
@@ -547,6 +566,7 @@
|
||||
pinmux = <PIN_PA0__SDMMC0_CK>,
|
||||
<PIN_PA2__SDMMC0_RSTN>,
|
||||
<PIN_PA11__SDMMC0_DS>;
|
||||
slew-rate = <0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
@@ -558,6 +578,7 @@
|
||||
<PIN_PC0__SDMMC1_DAT1>,
|
||||
<PIN_PC1__SDMMC1_DAT2>,
|
||||
<PIN_PC2__SDMMC1_DAT3>;
|
||||
slew-rate = <0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
@@ -566,6 +587,7 @@
|
||||
<PIN_PB28__SDMMC1_RSTN>,
|
||||
<PIN_PC5__SDMMC1_1V8SEL>,
|
||||
<PIN_PC4__SDMMC1_CD>;
|
||||
slew-rate = <0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
@@ -577,11 +599,13 @@
|
||||
<PIN_PD6__SDMMC2_DAT1>,
|
||||
<PIN_PD7__SDMMC2_DAT2>,
|
||||
<PIN_PD8__SDMMC2_DAT3>;
|
||||
slew-rate = <0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
ck {
|
||||
pinmux = <PIN_PD4__SDMMC2_CK>;
|
||||
slew-rate = <0>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
@@ -634,6 +658,15 @@
|
||||
pinctrl-0 = <&pinctrl_sdmmc2_default>;
|
||||
};
|
||||
|
||||
&shdwc {
|
||||
atmel,shdwc-debouncer = <976>;
|
||||
status = "okay";
|
||||
|
||||
input@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&spdifrx {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spdifrx_default>;
|
||||
|
||||
@@ -56,6 +56,7 @@
|
||||
panel {
|
||||
compatible = "edt,etm0700g0dh6";
|
||||
pinctrl-0 = <&pinctrl_display_gpio>;
|
||||
pinctrl-names = "default";
|
||||
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
@@ -76,8 +77,7 @@
|
||||
regulator-name = "vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 2 0>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
|
||||
/ {
|
||||
@@ -277,6 +278,7 @@
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
chan@1 {
|
||||
@@ -284,6 +286,7 @@
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
chan@2 {
|
||||
@@ -291,6 +294,7 @@
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
||||
chan@3 {
|
||||
@@ -298,6 +302,7 @@
|
||||
led-cur = /bits/ 8 <0x0>;
|
||||
max-cur = /bits/ 8 <0x0>;
|
||||
reg = <3>;
|
||||
color = <LED_COLOR_ID_WHITE>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -176,7 +176,18 @@
|
||||
pinctrl-0 = <&pinctrl_enet>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
|
||||
phy-handle = <&phy>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
qca,clk-out-frequency = <125000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
|
||||
@@ -114,7 +114,7 @@
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
@@ -124,7 +124,7 @@
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -292,7 +292,7 @@
|
||||
compatible = "micron,n25q256a", "jedec,spi-nor";
|
||||
spi-max-frequency = <29000000>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-tx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -101,7 +101,7 @@
|
||||
|
||||
nand@1,0 {
|
||||
compatible = "ti,omap2-nand";
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
|
||||
interrupt-parent = <&gpmc>;
|
||||
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
|
||||
<1 IRQ_TYPE_NONE>; /* termcount */
|
||||
|
||||
@@ -198,7 +198,7 @@
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
pxo_board {
|
||||
pxo_board: pxo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
@@ -1148,22 +1148,21 @@
|
||||
};
|
||||
|
||||
gpu: adreno-3xx@4300000 {
|
||||
compatible = "qcom,adreno-3xx";
|
||||
compatible = "qcom,adreno-320.2", "qcom,adreno";
|
||||
reg = <0x04300000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"mem_clk",
|
||||
"mem_iface_clk";
|
||||
"core",
|
||||
"iface",
|
||||
"mem",
|
||||
"mem_iface";
|
||||
clocks =
|
||||
<&mmcc GFX3D_CLK>,
|
||||
<&mmcc GFX3D_AHB_CLK>,
|
||||
<&mmcc GFX3D_AXI_CLK>,
|
||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||
qcom,chipid = <0x03020002>;
|
||||
|
||||
iommus = <&gfx3d 0
|
||||
&gfx3d 1
|
||||
@@ -1306,7 +1305,7 @@
|
||||
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
|
||||
clock-names = "iface_clk", "ref";
|
||||
clocks = <&mmcc DSI_M_AHB_CLK>,
|
||||
<&cxo_board>;
|
||||
<&pxo_board>;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@@ -75,6 +75,17 @@
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
securam: securam@e0000000 {
|
||||
compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
|
||||
reg = <0xe0000000 0x4000>;
|
||||
clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0xe0000000 0x4000>;
|
||||
no-memory-wc;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
secumod: secumod@e0004000 {
|
||||
compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
|
||||
reg = <0xe0004000 0x4000>;
|
||||
@@ -111,6 +122,17 @@
|
||||
clock-names = "td_slck", "md_slck", "main_xtal";
|
||||
};
|
||||
|
||||
shdwc: shdwc@e001d010 {
|
||||
compatible = "microchip,sama7g5-shdwc", "syscon";
|
||||
reg = <0xe001d010 0x10>;
|
||||
clocks = <&clk32k 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
atmel,wakeup-rtc-timer;
|
||||
atmel,wakeup-rtt-timer;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtt: rtt@e001d020 {
|
||||
compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
|
||||
reg = <0xe001d020 0x30>;
|
||||
@@ -137,6 +159,11 @@
|
||||
clocks = <&clk32k 0>;
|
||||
};
|
||||
|
||||
chipid@e0020000 {
|
||||
compatible = "microchip,sama7g5-chipid";
|
||||
reg = <0xe0020000 0x8>;
|
||||
};
|
||||
|
||||
sdmmc0: mmc@e1204000 {
|
||||
compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
|
||||
reg = <0xe1204000 0x4000>;
|
||||
@@ -515,6 +542,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
uddrc: uddrc@e3800000 {
|
||||
compatible = "microchip,sama7g5-uddrc";
|
||||
reg = <0xe3800000 0x4000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ddr3phy: ddr3phy@e3804000 {
|
||||
compatible = "microchip,sama7g5-ddr3phy";
|
||||
reg = <0xe3804000 0x1000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@e8c11000 {
|
||||
compatible = "arm,cortex-a7-gic";
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
|
||||
* CHANGES TO vexpress-v2m.dtsi!
|
||||
*/
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
v2m_fixed_3v3: fixed-regulator-0 {
|
||||
@@ -101,16 +102,68 @@
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
motherboard-bus {
|
||||
model = "V2M-P1";
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 63>;
|
||||
interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
motherboard-bus@8000000 {
|
||||
arm,hbi = <0x190>;
|
||||
arm,vexpress,site = <0>;
|
||||
arm,v2m-memory-map = "rs1";
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0 0 0x08000000 0x04000000>,
|
||||
<1 0 0x14000000 0x04000000>,
|
||||
<2 0 0x18000000 0x04000000>,
|
||||
<3 0 0x1c000000 0x04000000>,
|
||||
<4 0 0x0c000000 0x04000000>,
|
||||
<5 0 0x10000000 0x04000000>;
|
||||
|
||||
nor_flash: flash@0 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
@@ -215,7 +268,7 @@
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
mmci@50000 {
|
||||
mmc@50000 {
|
||||
compatible = "arm,pl180", "arm,primecell";
|
||||
reg = <0x050000 0x1000>;
|
||||
interrupts = <9>, <10>;
|
||||
@@ -275,7 +328,7 @@
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
wdt@f0000 {
|
||||
watchdog@f0000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0f0000 0x1000>;
|
||||
interrupts = <0>;
|
||||
|
||||
@@ -17,18 +17,73 @@
|
||||
* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
|
||||
* CHANGES TO vexpress-v2m-rs1.dtsi!
|
||||
*/
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
bus@4000000 {
|
||||
motherboard {
|
||||
model = "V2M-P1";
|
||||
bus@40000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x40000000 0x10000000>,
|
||||
<0x10000000 0x10000000 0x00020000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 63>;
|
||||
interrupt-map = <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
motherboard-bus@40000000 {
|
||||
arm,hbi = <0x190>;
|
||||
arm,vexpress,site = <0>;
|
||||
compatible = "arm,vexpress,v2m-p1", "simple-bus";
|
||||
#address-cells = <2>; /* SMB chipselect number and offset */
|
||||
#size-cells = <1>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges;
|
||||
ranges = <0 0 0x40000000 0x04000000>,
|
||||
<1 0 0x44000000 0x04000000>,
|
||||
<2 0 0x48000000 0x04000000>,
|
||||
<3 0 0x4c000000 0x04000000>,
|
||||
<7 0 0x10000000 0x00020000>;
|
||||
|
||||
flash@0,00000000 {
|
||||
compatible = "arm,vexpress-flash", "cfi-flash";
|
||||
|
||||
@@ -237,62 +237,7 @@
|
||||
};
|
||||
|
||||
bus@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
ranges = <0x8000000 0 0x8000000 0x18000000>;
|
||||
};
|
||||
|
||||
site2: hsb@40000000 {
|
||||
|
||||
@@ -609,62 +609,7 @@
|
||||
};
|
||||
|
||||
smb: bus@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
ranges = <0x8000000 0 0x8000000 0x18000000>;
|
||||
};
|
||||
|
||||
site2: hsb@40000000 {
|
||||
|
||||
@@ -207,62 +207,7 @@
|
||||
};
|
||||
|
||||
smb: bus@8000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x04000000>,
|
||||
<1 0 0x14000000 0x04000000>,
|
||||
<2 0 0x18000000 0x04000000>,
|
||||
<3 0 0x1c000000 0x04000000>,
|
||||
<4 0 0x0c000000 0x04000000>,
|
||||
<5 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
ranges = <0 0x8000000 0x18000000>;
|
||||
};
|
||||
|
||||
site2: hsb@40000000 {
|
||||
|
||||
@@ -295,64 +295,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
smb: bus@4000000 {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x40000000 0x04000000>,
|
||||
<1 0 0x44000000 0x04000000>,
|
||||
<2 0 0x48000000 0x04000000>,
|
||||
<3 0 0x4c000000 0x04000000>,
|
||||
<7 0 0x10000000 0x00020000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic 0 0 4>,
|
||||
<0 0 1 &gic 0 1 4>,
|
||||
<0 0 2 &gic 0 2 4>,
|
||||
<0 0 3 &gic 0 3 4>,
|
||||
<0 0 4 &gic 0 4 4>,
|
||||
<0 0 5 &gic 0 5 4>,
|
||||
<0 0 6 &gic 0 6 4>,
|
||||
<0 0 7 &gic 0 7 4>,
|
||||
<0 0 8 &gic 0 8 4>,
|
||||
<0 0 9 &gic 0 9 4>,
|
||||
<0 0 10 &gic 0 10 4>,
|
||||
<0 0 11 &gic 0 11 4>,
|
||||
<0 0 12 &gic 0 12 4>,
|
||||
<0 0 13 &gic 0 13 4>,
|
||||
<0 0 14 &gic 0 14 4>,
|
||||
<0 0 15 &gic 0 15 4>,
|
||||
<0 0 16 &gic 0 16 4>,
|
||||
<0 0 17 &gic 0 17 4>,
|
||||
<0 0 18 &gic 0 18 4>,
|
||||
<0 0 19 &gic 0 19 4>,
|
||||
<0 0 20 &gic 0 20 4>,
|
||||
<0 0 21 &gic 0 21 4>,
|
||||
<0 0 22 &gic 0 22 4>,
|
||||
<0 0 23 &gic 0 23 4>,
|
||||
<0 0 24 &gic 0 24 4>,
|
||||
<0 0 25 &gic 0 25 4>,
|
||||
<0 0 26 &gic 0 26 4>,
|
||||
<0 0 27 &gic 0 27 4>,
|
||||
<0 0 28 &gic 0 28 4>,
|
||||
<0 0 29 &gic 0 29 4>,
|
||||
<0 0 30 &gic 0 30 4>,
|
||||
<0 0 31 &gic 0 31 4>,
|
||||
<0 0 32 &gic 0 32 4>,
|
||||
<0 0 33 &gic 0 33 4>,
|
||||
<0 0 34 &gic 0 34 4>,
|
||||
<0 0 35 &gic 0 35 4>,
|
||||
<0 0 36 &gic 0 36 4>,
|
||||
<0 0 37 &gic 0 37 4>,
|
||||
<0 0 38 &gic 0 38 4>,
|
||||
<0 0 39 &gic 0 39 4>,
|
||||
<0 0 40 &gic 0 40 4>,
|
||||
<0 0 41 &gic 0 41 4>,
|
||||
<0 0 42 &gic 0 42 4>;
|
||||
};
|
||||
|
||||
site2: hsb@e0000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
|
||||
@@ -40,7 +40,9 @@ EXPORT_SYMBOL(sharpsl_param);
|
||||
|
||||
void sharpsl_save_param(void)
|
||||
{
|
||||
memcpy(&sharpsl_param, param_start(PARAM_BASE), sizeof(struct sharpsl_param_info));
|
||||
struct sharpsl_param_info *params = param_start(PARAM_BASE);
|
||||
|
||||
memcpy(&sharpsl_param, params, sizeof(*params));
|
||||
|
||||
if (sharpsl_param.comadj_keyword != COMADJ_MAGIC)
|
||||
sharpsl_param.comadj=-1;
|
||||
|
||||
@@ -76,6 +76,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_PANEL_ILITEK_IL9322=y
|
||||
CONFIG_DRM_TVE200=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_LOGO=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_MON=y
|
||||
|
||||
@@ -292,6 +292,7 @@ CONFIG_DRM_IMX_LDB=y
|
||||
CONFIG_DRM_IMX_HDMI=y
|
||||
CONFIG_DRM_ETNAVIV=y
|
||||
CONFIG_DRM_MXSFB=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_MODE_HELPERS=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_LCD_L4F00242T03=y
|
||||
|
||||
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