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Merge tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Browse Source 
Pull devicetree updates from Rob Herring:
 "DT core:

   - Fix ref counting errors in interrupt parsing code

   - Allow "nonposted-mmio" property per device and on non-Apple h/w

   - Use typed accessors in platform driver code

   - Fix mismatch between DT MAX_PHANDLE_ARGS and
     NR_FWNODE_REFERENCE_ARGS and increase the maximum number args

   - Rework of_resolve_phandles() to use __free() cleanup and fix ref
     count error

   - Use of_prop_cmp() in a few more places

   - Improve make_fit.py script error handling

  DT bindings:

   - Update DT property ordering rules for properties within groups
     (i.e. common suffix)

   - Update DT submitting-patches doc to cover sending .dts patches and
     SoC maintainer rules on being warning free against linux-next

   - Add ti,tps53681, ti,tps53681, Maxim max15301, max15303, and
     max20751 to trivial devices

   - Add Renesas RZ/V2H(P) and Allwinner H616 support to Arm Mali
     Bifrost GPU. Add Samsung exynos7870 support to Arm Mail Midgard.

   - Rework qcom,ebi2 and samsung,exynos4210-sram memory controller
     bindings to split child node properties. Fix the LAN9115 binding to
     use the child node schema so all properties are documented.

   - Convert nxp,lpc3220-mic and Altera ECC manager bindings to schema

   - Fix some issues with LVDS display panels causing validation
     warnings

   - Drop some obsolete parts of Xilinx bindings"

* tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (48 commits)
  scripts/make_fit: Print DT name before libfdt errors
  dt-bindings: edac: altera: socfpga: Convert to YAML
  dt-bindings: pps: gpio: Correct indentation and style in DTS example
  media: dt-bindings: mediatek,vcodec-encoder: Drop assigned-clock properties
  of: address: Allow to specify nonposted-mmio per-device
  of: address: Expand nonposted-mmio to non-Apple Silicon platforms
  docs: dt-bindings: Specify ordering for properties within groups
  dt-bindings: gpu: arm,mali-midgard: add exynos7870-mali compatible
  of: Move of_prop_val_eq() next to the single user
  of/platform: Use typed accessors rather than of_get_property()
  dt-bindings: trivial-devices: Add Maxim max15301, max15303, and max20751
  dt-bindings: fsi: ibm,p9-scom: Add "ibm,fsi2pib" compatible
  dt-bindings: memory-controllers: qcom,ebi2: Enforce child props
  dt-bindings: memory-controllers: samsung,exynos4210-srom: Enforce child props
  dt-bindings: display: mitsubishi,aa104xd12: Adjust allowed and required properties
  dt-bindings: display: mitsubishi,aa104xd12: Allow jeida-18 for data-mapping
  dt-bindings: interrupt-controller: Convert nxp,lpc3220-mic.txt to yaml format
  docs: process: maintainer-soc-clean-dts: linux-next is decisive
  docs: dt: submitting-patches: Document sending DTS patches
  of: Align macro MAX_PHANDLE_ARGS with NR_FWNODE_REFERENCE_ARGS
  ...
This commit is contained in:
Linus Torvalds
2025-03-29 11:23:16 -07:00
parent 092e335082 314655d41e
commit 3b9ea5b5ed
36 changed files with 764 additions and 707 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml
+1
View File
@@ -41,6 +41,7 @@ properties:
- enum:
- ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
- ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
- ti,sn65lvds822 # For the SN65LVDS822 FlatLink LVDS Receiver
- ti,sn65lvds94 # For the SN65DS94 LVDS serdes
- const: lvds-decoder # Generic LVDS decoders compatible fallback
- enum:
Documentation/devicetree/bindings/display/panel/mitsubishi,aa104xd12.yaml
+4 -2
View File
@@ -33,7 +33,9 @@ properties:
description: Reference to the regulator powering the panel VCC pins.
data-mapping:
const: jeida-24
enum:
- jeida-18
- jeida-24
width-mm:
const: 210
@@ -41,6 +43,7 @@ properties:
height-mm:
const: 158
backlight: true
panel-timing: true
port: true
@@ -48,7 +51,6 @@ additionalProperties: false
required:
- compatible
- vcc-supply
- data-mapping
- width-mm
- height-mm
Documentation/devicetree/bindings/dts-coding-style.rst
+7 -1
View File
@@ -133,6 +133,9 @@ The above-described ordering follows this approach:
3. Status is the last information to annotate that device node is or is not
finished (board resources are needed).
The individual properties inside each group shall use natural sort order by
the property name.
Example::
/* SoC DTSI */
@@ -158,7 +161,10 @@ Example::
/* Board DTS */
&device_node {
vdd-supply = <&board_vreg1>;
vdd-0v9-supply = <&board_vreg1>;
vdd-1v8-supply = <&board_vreg4>;
vdd-3v3-supply = <&board_vreg2>;
vdd-12v-supply = <&board_vreg3>;
status = "okay";
}
Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml
+323
View File
@@ -0,0 +1,323 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2025 Altera Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Altera SoCFPGA ECC Manager
maintainers:
- Matthew Gerlach <matthew.gerlach@altera.com>
description:
This binding describes the device tree nodes required for the Altera SoCFPGA
ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
families.
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-ecc-manager
- const: altr,socfpga-a10-ecc-manager
- const: altr,socfpga-a10-ecc-manager
- const: altr,socfpga-ecc-manager
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-controller: true
"#interrupt-cells":
const: 2
ranges: true
altr,sysmgr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to Stratix10 System Manager Block with the ECC manager registers
sdramedac:
type: object
additionalProperties: false
properties:
compatible:
enum:
- altr,sdram-edac-a10
- altr,sdram-edac-s10
interrupts:
minItems: 1
maxItems: 2
altr,sdr-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SDRAM parent
required:
- compatible
- interrupts
- altr,sdr-syscon
patternProperties:
"^ocram-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-ocram-ecc
- const: altr,socfpga-a10-ocram-ecc
- const: altr,socfpga-a10-ocram-ecc
- const: altr,socfpga-ocram-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
iram:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to OCRAM parent
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to OCRAM parent
required:
- compatible
- reg
- interrupts
"^usb[0-9]-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-usb-ecc
- const: altr,socfpga-usb-ecc
- const: altr,socfpga-usb-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to USB parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-eth-mac-ecc
- const: altr,socfpga-eth-mac-ecc
- const: altr,socfpga-eth-mac-ecc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to ethernet parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^sdmmc[a-f]-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
- items:
- const: altr,socfpga-s10-sdmmc-ecc
- const: altr,socfpga-sdmmc-ecc
- const: altr,socfpga-sdmmc-ecc
reg:
maxItems: 1
interrupts:
minItems: 2
maxItems: 4
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SD/MMC parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
"^l2-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
enum:
- altr,socfpga-a10-l2-ecc
- altr,socfpga-l2-ecc
reg:
maxItems: 1
interrupts:
maxItems: 2
required:
- compatible
- reg
- interrupts
"^dma-ecc@[a-f0-9]+$":
type: object
additionalProperties: false
properties:
compatible:
const: altr,socfpga-dma-ecc
reg:
maxItems: 1
interrupts:
maxItems: 2
altr,ecc-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to SD/MMC parent
required:
- compatible
- reg
- interrupts
- altr,ecc-parent
if:
properties:
compatible:
contains:
const: altr,socfpga-ecc-manager
then:
required:
- compatible
- "#address-cells"
- "#size-cells"
- ranges
else:
required:
- compatible
- "#address-cells"
- "#size-cells"
- interrupts
- interrupt-controller
- "#interrupt-cells"
- ranges
- altr,sysmgr-syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager",
"altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
sdramedac {
compatible = "altr,sdram-edac-s10";
altr,sdr-syscon = <&sdr>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
compatible = "altr,socfpga-s10-ocram-ecc",
"altr,socfpga-a10-ocram-ecc";
reg = <0xff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
usb0-ecc@ff8c4000 {
compatible = "altr,socfpga-s10-usb-ecc",
"altr,socfpga-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
compatible = "altr,socfpga-s10-eth-mac-ecc",
"altr,socfpga-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmca-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc",
"altr,socfpga-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
};
};
Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
-383
View File
@@ -1,383 +0,0 @@
Altera SoCFPGA ECC Manager
This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
The ECC Manager counts and corrects single bit errors and counts/handles
double bit errors which are uncorrectable.
Cyclone5 and Arria5 ECC Manager
Required Properties:
- compatible : Should be "altr,socfpga-ecc-manager"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses
Subcomponents:
L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
On Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-ocram-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- iram : phandle to On-Chip RAM definition.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt. Note the rising edge type.
Example:
eccmgr: eccmgr@ffd08140 {
compatible = "altr,socfpga-ecc-manager";
#address-cells = <1>;
#size-cells = <1>;
ranges;
l2-ecc@ffd08140 {
compatible = "altr,socfpga-l2-ecc";
reg = <0xffd08140 0x4>;
interrupts = <0 36 1>, <0 37 1>;
};
ocram-ecc@ffd08144 {
compatible = "altr,socfpga-ocram-ecc";
reg = <0xffd08144 0x4>;
iram = <&ocram>;
interrupts = <0 178 1>, <0 179 1>;
};
};
Arria10 SoCFPGA ECC Manager
The Arria10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register instead of individual IRQs like the Cyclone5
and Arria5. Therefore the device tree is different as well.
Required Properties:
- compatible : Should be "altr,socfpga-a10-ecc-manager"
- altr,sysgr-syscon : phandle to Arria10 System Manager Block
containing the ECC manager registers.
- #address-cells: must be 1
- #size-cells: must be 1
- interrupts : Should be single bit error interrupt, then double bit error
interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- ranges : standard definition, should translate from local addresses
Subcomponents:
L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
- reg : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
Ethernet FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-eth-mac-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
QSPI FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-qspi-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent QSPI node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt, then double bit error
interrupt, in this order for port A, and then single bit error interrupt,
then double bit error interrupt in this order for port B.
Example:
eccmgr: eccmgr@ffd06000 {
compatible = "altr,socfpga-a10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
l2-ecc@ffd06010 {
compatible = "altr,socfpga-a10-l2-ecc";
reg = <0xffd06010 0x4>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
<32 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8c3000 {
compatible = "altr,socfpga-a10-ocram-ecc";
reg = <0xff8c3000 0x90>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
<33 IRQ_TYPE_LEVEL_HIGH> ;
};
emac0-rx-ecc@ff8c0800 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0800 0x400>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
<36 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0c00 {
compatible = "altr,socfpga-eth-mac-ecc";
reg = <0xff8c0c00 0x400>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
<37 IRQ_TYPE_LEVEL_HIGH>;
};
nand-buf-ecc@ff8c2000 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2000 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
<43 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c2400 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2400 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
<45 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c2800 {
compatible = "altr,socfpga-nand-ecc";
reg = <0xff8c2800 0x400>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
<44 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c8000 {
compatible = "altr,socfpga-dma-ecc";
reg = <0xff8c8000 0x400>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
<42 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c8800 {
compatible = "altr,socfpga-usb-ecc";
reg = <0xff8c8800 0x400>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
<34 IRQ_TYPE_LEVEL_HIGH>;
};
qspi-ecc@ff8c8400 {
compatible = "altr,socfpga-qspi-ecc";
reg = <0xff8c8400 0x400>;
altr,ecc-parent = <&qspi>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<46 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c2c00 {
compatible = "altr,socfpga-sdmmc-ecc";
reg = <0xff8c2c00 0x400>;
altr,ecc-parent = <&mmc>;
interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
<47 IRQ_TYPE_LEVEL_HIGH>,
<16 IRQ_TYPE_LEVEL_HIGH>,
<48 IRQ_TYPE_LEVEL_HIGH>;
};
};
Stratix10 SoCFPGA ECC Manager (ARM64)
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register similar to the Arria10. However, Stratix10 ECC
requires access to registers that can only be read from Secure Monitor
with SMC calls. Therefore the device tree is slightly different. Note
that only 1 interrupt is sent in Stratix10 because the double bit errors
are treated as SErrors in ARM64 instead of IRQs in ARM32.
Required Properties:
- compatible : Should be "altr,socfpga-s10-ecc-manager"
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
containing the ECC manager registers.
- interrupts : Should be single bit error interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses
Subcomponents:
SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
- interrupts : Should be single bit error interrupt.
On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-ocram-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent OCRAM node.
- interrupts : Should be single bit error interrupt.
Ethernet FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-eth-mac-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts : Should be single bit error interrupt.
NAND FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-nand-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts : Should be single bit error interrupt.
DMA FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-dma-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts : Should be single bit error interrupt.
USB FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-usb-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts : Should be single bit error interrupt.
SDMMC FIFO ECC
Required Properties:
- compatible : Should be "altr,socfpga-s10-sdmmc-ecc"
- reg : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts : Should be single bit error interrupt for port A
and then single bit error interrupt for port B.
Example:
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager";
altr,sysmgr-syscon = <&sysmgr>;
#address-cells = <1>;
#size-cells = <1>;
interrupts = <0 15 4>;
interrupt-controller;
#interrupt-cells = <2>;
ranges;
sdramedac {
compatible = "altr,sdram-edac-s10";
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
ocram-ecc@ff8cc000 {
compatible = "altr,socfpga-s10-ocram-ecc";
reg = <ff8cc000 0x100>;
altr,ecc-parent = <&ocram>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-rx-ecc@ff8c0000 {
compatible = "altr,socfpga-s10-eth-mac-ecc";
reg = <0xff8c0000 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
emac0-tx-ecc@ff8c0400 {
compatible = "altr,socfpga-s10-eth-mac-ecc";
reg = <0xff8c0400 0x100>;
altr,ecc-parent = <&gmac0>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
};
nand-buf-ecc@ff8c8000 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8000 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
};
nand-rd-ecc@ff8c8400 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8400 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
};
nand-wr-ecc@ff8c8800 {
compatible = "altr,socfpga-s10-nand-ecc";
reg = <0xff8c8800 0x100>;
altr,ecc-parent = <&nand>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
};
dma-ecc@ff8c9000 {
compatible = "altr,socfpga-s10-dma-ecc";
reg = <0xff8c9000 0x100>;
altr,ecc-parent = <&pdma>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
usb0-ecc@ff8c4000 {
compatible = "altr,socfpga-s10-usb-ecc";
reg = <0xff8c4000 0x100>;
altr,ecc-parent = <&usb0>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
sdmmc-ecc@ff8c8c00 {
compatible = "altr,socfpga-s10-sdmmc-ecc";
reg = <0xff8c8c00 0x100>;
altr,ecc-parent = <&mmc>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
<15 IRQ_TYPE_LEVEL_HIGH>;
};
};
Documentation/devicetree/bindings/fsi/ibm,p9-scom.yaml
+1
View File
@@ -16,6 +16,7 @@ description:
properties:
compatible:
enum:
- ibm,fsi2pib
- ibm,p9-scom
- ibm,i2cr-scom
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+3
View File
@@ -17,6 +17,7 @@ properties:
oneOf:
- items:
- enum:
- allwinner,sun50i-h616-mali
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
- mediatek,mt8183b-mali
@@ -24,6 +25,7 @@ properties:
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g057-mali
- rockchip,px30-mali
- rockchip,rk3562-mali
- rockchip,rk3568-mali
@@ -143,6 +145,7 @@ allOf:
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
- renesas,r9a09g057-mali
then:
properties:
interrupts:
Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml
+4 -1
View File
@@ -45,12 +45,15 @@ properties:
- samsung,exynos7-mali
- const: samsung,exynos5433-mali
- const: arm,mali-t760
- items:
- enum:
- samsung,exynos7870-mali
- const: arm,mali-t830
- items:
- enum:
- rockchip,rk3399-mali
- const: arm,mali-t860
# "arm,mali-t830"
# "arm,mali-t880"
reg:
Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
-58
View File
@@ -1,58 +0,0 @@
* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
Required properties:
- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
- reg: should contain IC registers location and length.
- interrupt-controller: identifies the node as an interrupt controller.
- #interrupt-cells: the number of cells to define an interrupt, should be 2.
The first cell is the IRQ number, the second cell is used to specify
one of the supported IRQ types:
IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
Reset value is IRQ_TYPE_LEVEL_LOW.
Optional properties:
- interrupts: empty for MIC interrupt controller, cascaded MIC
hardware interrupts for SIC1 and SIC2
Examples:
/* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
reg = <0x40008000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
};
sic1: interrupt-controller@4000c000 {
compatible = "nxp,lpc3220-sic";
reg = <0x4000c000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
<30 IRQ_TYPE_LEVEL_LOW>;
};
sic2: interrupt-controller@40010000 {
compatible = "nxp,lpc3220-sic";
reg = <0x40010000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
<31 IRQ_TYPE_LEVEL_LOW>;
};
/* ADC */
adc@40048000 {
compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>;
interrupt-parent = <&sic1>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
};
Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.yaml
+68
View File
@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/nxp,lpc3220-mic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
maintainers:
- Vladimir Zapolskiy <vz@mleia.com>
properties:
compatible:
enum:
- nxp,lpc3220-mic
- nxp,lpc3220-sic
reg:
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
items:
- description: Regular interrupt request
- description: Fast interrupt request
required:
- compatible
- reg
- interrupt-controller
- '#interrupt-cells'
allOf:
- if:
properties:
compatible:
contains:
const: nxp,lpc3220-sic
then:
required:
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
mic: interrupt-controller@40008000 {
compatible = "nxp,lpc3220-mic";
reg = <0x40008000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
};
interrupt-controller@4000c000 {
compatible = "nxp,lpc3220-sic";
reg = <0x4000c000 0x4000>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&mic>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
<30 IRQ_TYPE_LEVEL_LOW>;
};
Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
-6
View File
@@ -41,10 +41,6 @@ properties:
minItems: 1
maxItems: 5
assigned-clocks: true
assigned-clock-parents: true
iommus:
minItems: 1
maxItems: 32
@@ -78,8 +74,6 @@ required:
- clocks
- clock-names
- iommus
- assigned-clocks
- assigned-clock-parents
allOf:
- if:
Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
+1 -35
View File
@@ -38,50 +38,16 @@ properties:
patternProperties:
"^.*@[0-3],[a-f0-9]+$":
type: object
$ref: mc-peripheral-props.yaml#
additionalProperties: true
description:
The actual device nodes should be added as subnodes to the SROMc node.
These subnodes, in addition to regular device specification, should
contain the following properties, describing configuration
of the relevant SROM bank.
properties:
reg:
description:
Bank number, base address (relative to start of the bank) and size
of the memory mapped for the device. Note that base address will be
typically 0 as this is the start of the bank.
maxItems: 1
reg-io-width:
enum: [1, 2]
description:
Data width in bytes (1 or 2). If omitted, default of 1 is used.
samsung,srom-page-mode:
description:
If page mode is set, 4 data page mode will be configured,
else normal (1 data) page mode will be set.
type: boolean
samsung,srom-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 6
description: |
Array of 6 integers, specifying bank timings in the following order:
Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
Each value is specified in cycles and has the following meaning
and valid range:
Tacp: Page mode access cycle at Page mode (0 - 15)
Tcah: Address holding time after CSn (0 - 15)
Tcoh: Chip selection hold on OEn (0 - 15)
Tacc: Access cycle (0 - 31, the actual time is N + 1)
Tcos: Chip selection set-up before OEn (0 - 15)
Tacs: Address set-up before CSn (0 - 15)
required:
- reg
- samsung,srom-timing
required:
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
+2
View File
@@ -36,6 +36,8 @@ allOf:
- $ref: st,stm32-fmc2-ebi-props.yaml#
- $ref: ingenic,nemc-peripherals.yaml#
- $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
- $ref: qcom,ebi2-peripheral-props.yaml#
- $ref: samsung,exynos4210-srom-peripheral-props.yaml#
- $ref: ti,gpmc-child.yaml#
- $ref: fsl/fsl,imx-weim-peripherals.yaml
Documentation/devicetree/bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml
+91
View File
@@ -0,0 +1,91 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2)
maintainers:
- Bjorn Andersson <andersson@kernel.org>
properties:
# SLOW chip selects
qcom,xmem-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The time the memory continues to drive the data bus after OE
is de-asserted, in order to avoid contention on the data bus.
They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Minimum value is
actually 1, so a value of 0 will still yield 1 recovery cycle.
minimum: 0
maximum: 15
qcom,xmem-write-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The extra cycles inserted after every write minimum 1. The
data out is driven from the time WE is asserted until CS is
asserted. With a hold of 1 (value = 0), the CS stays active
for 1 extra cycle, etc.
minimum: 0
maximum: 15
qcom,xmem-write-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for write cycles inserted for the first
write to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-read-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for read cycles inserted for the first
read to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-write-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every write access.
minimum: 0
maximum: 15
qcom,xmem-read-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every read access.
minimum: 0
maximum: 15
# FAST chip selects
qcom,xmem-address-hold-enable:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Holds the address for an extra cycle to meet hold time
requirements with ADV assertion, when set to 1.
enum: [ 0, 1 ]
qcom,xmem-adv-to-oe-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of cycles elapsed before an OE assertion, with
respect to the cycle where ADV (address valid) is asserted.
minimum: 0
maximum: 3
qcom,xmem-read-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The length in cycles of the first segment of a read transfer.
For a single read transfer this will be the time from CS
assertion to OE assertion.
minimum: 0
maximum: 15
additionalProperties: true
Documentation/devicetree/bindings/bus/qcom,ebi2.yaml → Documentation/devicetree/bindings/memory-controllers/qcom,ebi2.yaml
+2 -85
View File
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml#
$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm External Bus Interface 2 (EBI2)
@@ -104,91 +104,8 @@ required:
patternProperties:
"^.*@[0-5],[0-9a-f]+$":
type: object
$ref: mc-peripheral-props.yaml#
additionalProperties: true
properties:
reg:
maxItems: 1
# SLOW chip selects
qcom,xmem-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The time the memory continues to drive the data bus after OE
is de-asserted, in order to avoid contention on the data bus.
They are inserted when reading one CS and switching to another
CS or read followed by write on the same CS. Minimum value is
actually 1, so a value of 0 will still yield 1 recovery cycle.
minimum: 0
maximum: 15
qcom,xmem-write-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The extra cycles inserted after every write minimum 1. The
data out is driven from the time WE is asserted until CS is
asserted. With a hold of 1 (value = 0), the CS stays active
for 1 extra cycle, etc.
minimum: 0
maximum: 15
qcom,xmem-write-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for write cycles inserted for the first
write to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-read-delta-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The initial latency for read cycles inserted for the first
read to a page or burst memory.
minimum: 0
maximum: 255
qcom,xmem-write-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every write access.
minimum: 0
maximum: 15
qcom,xmem-read-wait-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of wait cycles for every read access.
minimum: 0
maximum: 15
# FAST chip selects
qcom,xmem-address-hold-enable:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
Holds the address for an extra cycle to meet hold time
requirements with ADV assertion, when set to 1.
enum: [ 0, 1 ]
qcom,xmem-adv-to-oe-recovery-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The number of cycles elapsed before an OE assertion, with
respect to the cycle where ADV (address valid) is asserted.
minimum: 0
maximum: 3
qcom,xmem-read-hold-cycles:
$ref: /schemas/types.yaml#/definitions/uint32
description: >
The length in cycles of the first segment of a read transfer.
For a single read transfer this will be the time from CS
assertion to OE assertion.
minimum: 0
maximum: 15
required:
- reg
additionalProperties: false
Documentation/devicetree/bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml
+35
View File
@@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Peripheral Properties for Samsung Exynos SoC SROM Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
samsung,srom-page-mode:
description:
If page mode is set, 4 data page mode will be configured,
else normal (1 data) page mode will be set.
type: boolean
samsung,srom-timing:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 6
maxItems: 6
description: |
Array of 6 integers, specifying bank timings in the following order:
Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
Each value is specified in cycles and has the following meaning
and valid range:
Tacp: Page mode access cycle at Page mode (0 - 15)
Tcah: Address holding time after CSn (0 - 15)
Tcoh: Chip selection hold on OEn (0 - 15)
Tacc: Access cycle (0 - 31, the actual time is N + 1)
Tcos: Chip selection set-up before OEn (0 - 15)
Tacs: Address set-up before CSn (0 - 15)
additionalProperties: true
Documentation/devicetree/bindings/net/smsc,lan9115.yaml
+2 -4
View File
@@ -11,6 +11,7 @@ maintainers:
allOf:
- $ref: ethernet-controller.yaml#
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
properties:
compatible:
@@ -89,10 +90,7 @@ required:
- reg
- interrupts
# There are lots of bus-specific properties ("qcom,*", "samsung,*", "fsl,*",
# "gpmc,*", ...) to be found, that actually depend on the compatible value of
# the parent node.
additionalProperties: true
unevaluatedProperties: false
examples:
- |
Documentation/devicetree/bindings/pps/pps-gpio.yaml
+10 -10
View File
@@ -36,14 +36,14 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/gpio.h>
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
assert-falling-edge;
echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
echo-active-ms = <100>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
assert-falling-edge;
echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
echo-active-ms = <100>;
};
Documentation/devicetree/bindings/soc/imx/fsl,aips-bus.yaml
+4 -1
View File
@@ -22,6 +22,9 @@ select:
required:
- compatible
allOf:
- $ref: /schemas/simple-bus.yaml#
properties:
compatible:
items:
@@ -35,7 +38,7 @@ required:
- compatible
- reg
additionalProperties: true
unevaluatedProperties: false
examples:
- |
Documentation/devicetree/bindings/submitting-patches.rst
+17 -2
View File
@@ -54,11 +54,22 @@ I. For patch submitters
followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864
("checkpatch: add DT compatible string documentation checks"). ]
7) If a documented compatible string is not yet matched by the
7) DTS is treated in general as driver-independent hardware description, thus
any DTS patches, regardless whether using existing or new bindings, should
be placed at the end of patchset to indicate no dependency of drivers on
the DTS. DTS will be anyway applied through separate tree or branch, so
different order would indicate the serie is non-bisectable.
If a driver subsystem maintainer prefers to apply entire set, instead of
their relevant portion of patchset, please split the DTS patches into
separate patchset with a reference in changelog or cover letter to the
bindings submission on the mailing list.
8) If a documented compatible string is not yet matched by the
driver, the documentation should also include a compatible
string that is matched by the driver.
8) Bindings are actively used by multiple projects other than the Linux
9) Bindings are actively used by multiple projects other than the Linux
Kernel, extra care and consideration may need to be taken when making changes
to existing bindings.
@@ -79,6 +90,10 @@ II. For kernel maintainers
3) For a series going though multiple trees, the binding patch should be
kept with the driver using the binding.
4) The DTS files should however never be applied via driver subsystem tree,
but always via platform SoC trees on dedicated branches (see also
Documentation/process/maintainer-soc.rst).
III. Notes
==========

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