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Merge tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux into soc/dt

Browse Source 
RISC-V SpacemiT DT changes for 6.20

- Disable Ethernet PHY auto sleep mode
- Add pinctrl IO power support
- Add K3 Pico-ITX board
- Add support for K3 SoC
- Add DWC USB support
- Add reset for eMMC(sdhci)/I2C
- Add PCIe support
- Support PMIC for Jupiter board

* tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux:
  riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi
  riscv: dts: spacemit: pinctrl: update register and IO power
  riscv: dts: spacemit: add K3 Pico-ITX board support
  riscv: dts: spacemit: add initial support for K3 SoC
  dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
  dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
  dt-bindings: interrupt-controller: add SpacemiT K3 APLIC
  dt-bindings: timer: add SpacemiT K3 CLINT
  dt-bindings: riscv: add SpacemiT X100 CPU compatible
  riscv: dts: spacemit: k1: Add "b" ISA extension
  riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3
  riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1
  riscv: dts: spacemit: Add USB2 PHY node for K1
  riscv: dts: spacemit: sdhci: add reset support
  riscv: dts: spacemit: add reset property
  riscv: dts: spacemit: PCIe and PHY-related updates
  riscv: dts: spacemit: Add a PCIe regulator
  riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter
  riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter
  riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2026-01-28 18:39:39 +01:00
parent c8f7de01d9 5164e95565
commit 332a1ff488
14 changed files with 1116 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
+1
View File
@@ -28,6 +28,7 @@ properties:
items:
- enum:
- qemu,aplic
- spacemit,k3-aplic
- const: riscv,aplic
reg:
Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml
+1
View File
@@ -48,6 +48,7 @@ properties:
items:
- enum:
- qemu,imsics
- spacemit,k3-imsics
- const: riscv,imsics
reg:
Documentation/devicetree/bindings/riscv/cpus.yaml
+1
View File
@@ -61,6 +61,7 @@ properties:
- sifive,u7
- sifive,u74
- sifive,u74-mc
- spacemit,x100
- spacemit,x60
- thead,c906
- thead,c908
Documentation/devicetree/bindings/riscv/spacemit.yaml
+5
View File
@@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT SoC-based boards
maintainers:
- Guodong Xu <guodong@riscstar.com>
- Yangyu Chen <cyy@cyyself.name>
- Yixun Lan <dlan@gentoo.org>
@@ -26,6 +27,10 @@ properties:
- xunlong,orangepi-r2s
- xunlong,orangepi-rv2
- const: spacemit,k1
- items:
- enum:
- spacemit,k3-pico-itx
- const: spacemit,k3
additionalProperties: true
Documentation/devicetree/bindings/timer/sifive,clint.yaml
+1
View File
@@ -33,6 +33,7 @@ properties:
- eswin,eic7700-clint # ESWIN EIC7700
- sifive,fu540-c000-clint # SiFive FU540
- spacemit,k1-clint # SpacemiT K1
- spacemit,k3-clint # SpacemiT K3
- starfive,jh7100-clint # StarFive JH7100
- starfive,jh7110-clint # StarFive JH7110
- starfive,jh8100-clint # StarFive JH8100
arch/riscv/boot/dts/spacemit/Makefile
+1
View File
@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SPACEMIT) += k1-milkv-jupiter.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-musepi-pro.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-r2s.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k1-orangepi-rv2.dtb
dtb-$(CONFIG_ARCH_SPACEMIT) += k3-pico-itx.dtb
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+90
View File
@@ -33,6 +33,14 @@
};
};
pcie_vcc_3v3: pcie-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "PCIE_VCC3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_dc_in: dc-in-12v {
compatible = "regulator-fixed";
regulator-name = "dc_in_12v";
@@ -51,6 +59,31 @@
regulator-always-on;
vin-supply = <&reg_dc_in>;
};
usb3-vbus-5v {
compatible = "regulator-fixed";
regulator-name = "USB30_VBUS";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio K1_GPIO(97) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
usb3_hub_5v: usb3-hub-5v {
compatible = "regulator-fixed";
regulator-name = "USB30_HUB";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio K1_GPIO(123) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&combo_phy {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_3_cfg>;
status = "okay";
};
&emmc {
@@ -264,8 +297,65 @@
};
};
&pcie1_phy {
pinctrl-names = "default";
pinctrl-0 = <&pcie1_3_cfg>;
status = "okay";
};
&pcie1_port {
phys = <&pcie1_phy>;
};
&pcie1 {
vpcie3v3-supply = <&pcie_vcc_3v3>;
status = "okay";
};
&pcie2_phy {
pinctrl-names = "default";
pinctrl-0 = <&pcie2_4_cfg>;
status = "okay";
};
&pcie2_port {
phys = <&pcie2_phy>;
};
&pcie2 {
vpcie3v3-supply = <&pcie_vcc_3v3>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
status = "okay";
};
&usbphy2 {
status = "okay";
};
&usb_dwc3 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
hub_2_0: hub@1 {
compatible = "usb2109,2817";
reg = <0x1>;
vdd-supply = <&usb3_hub_5v>;
peer-hub = <&hub_3_0>;
reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
};
hub_3_0: hub@2 {
compatible = "usb2109,817";
reg = <0x2>;
vdd-supply = <&usb3_hub_5v>;
peer-hub = <&hub_2_0>;
reset-gpios = <&gpio K1_GPIO(124) GPIO_ACTIVE_LOW>;
};
};
arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts
+135
View File
@@ -20,6 +20,25 @@
chosen {
stdout-path = "serial0";
};
reg_dc_in: dc-in-12v {
compatible = "regulator-fixed";
regulator-name = "dc_in_12v";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
regulator-boot-on;
regulator-always-on;
};
reg_vcc_4v: vcc-4v {
compatible = "regulator-fixed";
regulator-name = "vcc_4v";
regulator-min-microvolt = <4000000>;
regulator-max-microvolt = <4000000>;
regulator-boot-on;
regulator-always-on;
vin-supply = <&reg_dc_in>;
};
};
&eth0 {
@@ -72,6 +91,122 @@
status = "okay";
};
&i2c8 {
pinctrl-0 = <&i2c8_cfg>;
pinctrl-names = "default";
status = "okay";
pmic@41 {
compatible = "spacemit,p1";
reg = <0x41>;
interrupts = <64>;
vin-supply = <&reg_vcc_4v>;
regulators {
buck1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
buck2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
buck3_1v8: buck3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1800000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
buck4 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3300000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
buck5 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
buck6 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3450000>;
regulator-ramp-delay = <5000>;
regulator-always-on;
};
aldo1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
};
aldo2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
aldo3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
aldo4 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
dldo1 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
};
dldo2 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
dldo3 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
dldo4 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-always-on;
};
dldo5 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
dldo6 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
regulator-always-on;
};
dldo7 {
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <3400000>;
};
};
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
arch/riscv/boot/dts/spacemit/k1-orangepi-r2s.dts
+2
View File
@@ -52,6 +52,7 @@
rgmii0: phy@1 {
reg = <0x1>;
motorcomm,auto-sleep-disabled;
};
};
};
@@ -75,6 +76,7 @@
rgmii1: phy@1 {
reg = <0x1>;
motorcomm,auto-sleep-disabled;
};
};
};
arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+2
View File
@@ -54,6 +54,7 @@
rgmii0: phy@1 {
reg = <0x1>;
motorcomm,auto-sleep-disabled;
};
};
};
@@ -77,6 +78,7 @@
rgmii1: phy@1 {
reg = <0x1>;
motorcomm,auto-sleep-disabled;
};
};
};
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+33
View File
@@ -530,6 +530,39 @@
};
};
pcie0_3_cfg: pcie0-3-cfg {
pcie0-3-pins {
pinmux = <K1_PADCONF(54, 3)>, /* PERST# */
<K1_PADCONF(55, 3)>, /* WAKE# */
<K1_PADCONF(53, 3)>; /* CLKREQ# */
bias-pull-up = <0>;
drive-strength = <21>;
};
};
pcie1_3_cfg: pcie1-3-cfg {
pcie1-3-pins {
pinmux = <K1_PADCONF(59, 4)>, /* PERST# */
<K1_PADCONF(60, 4)>, /* WAKE# */
<K1_PADCONF(61, 4)>; /* CLKREQ# */
bias-pull-up = <0>;
drive-strength = <21>;
};
};
pcie2_4_cfg: pcie2-4-cfg {
pcie2-4-pins {
pinmux = <K1_PADCONF(62, 4)>, /* PERST# */
<K1_PADCONF(112, 3)>, /* WAKE# */
<K1_PADCONF(117, 4)>; /* CLKREQ# */
bias-pull-up = <0>;
drive-strength = <21>;
};
};
pwm14_1_cfg: pwm14-1-cfg {
pwm14-1-pins {
pinmux = <K1_PADCONF(44, 4)>;
arch/riscv/boot/dts/spacemit/k1.dtsi
+237 -17
View File
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/spacemit,k1-syscon.h>
#include <dt-bindings/phy/phy.h>
/dts-v1/;
/ {
@@ -53,9 +54,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -83,9 +84,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <1>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -113,9 +114,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <2>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -143,9 +144,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <3>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -173,9 +174,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <4>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -203,9 +204,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <5>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -233,9 +234,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <6>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -263,9 +264,9 @@
compatible = "spacemit,x60", "riscv";
device_type = "cpu";
reg = <7>;
riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom",
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicond", "zicsr",
"zifencei", "zihintpause", "zihpm", "zfh", "zba",
"zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt",
@@ -367,6 +368,7 @@
<&syscon_apbc CLK_TWSI0_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI0>;
interrupts = <36>;
status = "disabled";
};
@@ -380,6 +382,7 @@
<&syscon_apbc CLK_TWSI1_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI1>;
interrupts = <37>;
status = "disabled";
};
@@ -393,6 +396,7 @@
<&syscon_apbc CLK_TWSI2_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI2>;
interrupts = <38>;
status = "disabled";
};
@@ -406,6 +410,7 @@
<&syscon_apbc CLK_TWSI4_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI4>;
interrupts = <40>;
status = "disabled";
};
@@ -419,10 +424,65 @@
<&syscon_apbc CLK_TWSI5_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI5>;
interrupts = <41>;
status = "disabled";
};
usbphy2: phy@c0a30000 {
compatible = "spacemit,k1-usb2-phy";
reg = <0x0 0xc0a30000 0x0 0x200>;
clocks = <&syscon_apmu CLK_USB30>;
#phy-cells = <0>;
status = "disabled";
};
combo_phy: phy@c0b10000 {
compatible = "spacemit,k1-combo-phy";
reg = <0x0 0xc0b10000 0x0 0x1000>;
clocks = <&vctcxo_24m>,
<&syscon_apmu CLK_PCIE0_DBI>,
<&syscon_apmu CLK_PCIE0_MASTER>,
<&syscon_apmu CLK_PCIE0_SLAVE>;
clock-names = "refclk",
"dbi",
"mstr",
"slv";
resets = <&syscon_apmu RESET_PCIE0_GLOBAL>,
<&syscon_apmu RESET_PCIE0_DBI>,
<&syscon_apmu RESET_PCIE0_MASTER>,
<&syscon_apmu RESET_PCIE0_SLAVE>;
reset-names = "phy",
"dbi",
"mstr",
"slv";
#phy-cells = <1>;
spacemit,apmu = <&syscon_apmu>;
status = "disabled";
};
pcie1_phy: phy@c0c10000 {
compatible = "spacemit,k1-pcie-phy";
reg = <0x0 0xc0c10000 0x0 0x1000>;
clocks = <&vctcxo_24m>;
clock-names = "refclk";
resets = <&syscon_apmu RESET_PCIE1_GLOBAL>;
reset-names = "phy";
#phy-cells = <0>;
status = "disabled";
};
pcie2_phy: phy@c0d10000 {
compatible = "spacemit,k1-pcie-phy";
reg = <0x0 0xc0d10000 0x0 0x1000>;
clocks = <&vctcxo_24m>;
clock-names = "refclk";
resets = <&syscon_apmu RESET_PCIE2_GLOBAL>;
reset-names = "phy";
#phy-cells = <0>;
status = "disabled";
};
syscon_apbc: system-controller@d4015000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
@@ -443,6 +503,7 @@
<&syscon_apbc CLK_TWSI6_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI6>;
interrupts = <70>;
status = "disabled";
};
@@ -546,6 +607,7 @@
<&syscon_apbc CLK_TWSI7_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI7>;
interrupts = <18>;
status = "disabled";
};
@@ -559,16 +621,18 @@
<&syscon_apbc CLK_TWSI8_BUS>;
clock-names = "func", "bus";
clock-frequency = <400000>;
resets = <&syscon_apbc RESET_TWSI8>;
interrupts = <19>;
status = "disabled";
};
pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k1-pinctrl";
reg = <0x0 0xd401e000 0x0 0x400>;
reg = <0x0 0xd401e000 0x0 0x1000>;
clocks = <&syscon_apbc CLK_AIB>,
<&syscon_apbc CLK_AIB_BUS>;
clock-names = "func", "bus";
spacemit,apbc = <&syscon_apbc>;
};
pwm8: pwm@d4020000 {
@@ -969,6 +1033,135 @@
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
pcie0: pcie@ca000000 {
device_type = "pci";
compatible = "spacemit,k1-pcie";
reg = <0x0 0xca000000 0x0 0x00001000>,
<0x0 0xca300000 0x0 0x0001ff24>,
<0x0 0x8f000000 0x0 0x00002000>,
<0x0 0xc0b20000 0x0 0x00001000>;
reg-names = "dbi",
"atu",
"config",
"link";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x8f002000 0x0 0x00100000>,
<0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x0f000000>;
interrupts = <141>;
interrupt-names = "msi";
clocks = <&syscon_apmu CLK_PCIE0_DBI>,
<&syscon_apmu CLK_PCIE0_MASTER>,
<&syscon_apmu CLK_PCIE0_SLAVE>;
clock-names = "dbi",
"mstr",
"slv";
resets = <&syscon_apmu RESET_PCIE0_DBI>,
<&syscon_apmu RESET_PCIE0_MASTER>,
<&syscon_apmu RESET_PCIE0_SLAVE>;
reset-names = "dbi",
"mstr",
"slv";
spacemit,apmu = <&syscon_apmu 0x03cc>;
status = "disabled";
pcie0_port: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie1: pcie@ca400000 {
device_type = "pci";
compatible = "spacemit,k1-pcie";
reg = <0x0 0xca400000 0x0 0x00001000>,
<0x0 0xca700000 0x0 0x0001ff24>,
<0x0 0x9f000000 0x0 0x00002000>,
<0x0 0xc0c20000 0x0 0x00001000>;
reg-names = "dbi",
"atu",
"config",
"link";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x9f002000 0x0 0x00100000>,
<0x02000000 0x0 0x90000000 0x0 0x90000000 0x0 0x0f000000>;
interrupts = <142>;
interrupt-names = "msi";
clocks = <&syscon_apmu CLK_PCIE1_DBI>,
<&syscon_apmu CLK_PCIE1_MASTER>,
<&syscon_apmu CLK_PCIE1_SLAVE>;
clock-names = "dbi",
"mstr",
"slv";
resets = <&syscon_apmu RESET_PCIE1_DBI>,
<&syscon_apmu RESET_PCIE1_MASTER>,
<&syscon_apmu RESET_PCIE1_SLAVE>;
reset-names = "dbi",
"mstr",
"slv";
spacemit,apmu = <&syscon_apmu 0x3d4>;
status = "disabled";
pcie1_port: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pcie2: pcie@ca800000 {
device_type = "pci";
compatible = "spacemit,k1-pcie";
reg = <0x0 0xca800000 0x0 0x00001000>,
<0x0 0xcab00000 0x0 0x0001ff24>,
<0x0 0xb7000000 0x0 0x00002000>,
<0x0 0xc0d20000 0x0 0x00001000>;
reg-names = "dbi",
"atu",
"config",
"link";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0xb7002000 0x0 0x00100000>,
<0x42000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000>,
<0x02000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x07000000>;
interrupts = <143>;
interrupt-names = "msi";
clocks = <&syscon_apmu CLK_PCIE2_DBI>,
<&syscon_apmu CLK_PCIE2_MASTER>,
<&syscon_apmu CLK_PCIE2_SLAVE>;
clock-names = "dbi",
"mstr",
"slv";
resets = <&syscon_apmu RESET_PCIE2_DBI>,
<&syscon_apmu RESET_PCIE2_MASTER>,
<&syscon_apmu RESET_PCIE2_SLAVE>;
reset-names = "dbi",
"mstr",
"slv";
spacemit,apmu = <&syscon_apmu 0x3dc>;
status = "disabled";
pcie2_port: pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
storage-bus {
@@ -978,12 +1171,39 @@
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>;
usb_dwc3: usb@c0a00000 {
compatible = "spacemit,k1-dwc3";
reg = <0x0 0xc0a00000 0x0 0x10000>;
clocks = <&syscon_apmu CLK_USB30>;
clock-names = "usbdrd30";
interrupts = <125>;
phys = <&usbphy2>, <&combo_phy PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi";
resets = <&syscon_apmu RESET_USB30_AHB>,
<&syscon_apmu RESET_USB30_VCC>,
<&syscon_apmu RESET_USB30_PHY>;
reset-names = "ahb", "vcc", "phy";
reset-delay = <2>;
snps,hsphy_interface = "utmi";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,dis_rxdet_inp3_quirk;
status = "disabled";
};
emmc: mmc@d4281000 {
compatible = "spacemit,k1-sdhci";
reg = <0x0 0xd4281000 0x0 0x200>;
clocks = <&syscon_apmu CLK_SDH_AXI>,
<&syscon_apmu CLK_SDH2>;
clock-names = "core", "io";
resets = <&syscon_apmu RESET_SDH_AXI>,
<&syscon_apmu RESET_SDH2>;
reset-names = "axi", "sdh";
interrupts = <101>;
status = "disabled";
};
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+29
View File
@@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd
* Copyright (c) 2026 Guodong Xu <guodong@riscstar.com>
*/
#include "k3.dtsi"
/ {
model = "SpacemiT K3 Pico-ITX";
compatible = "spacemit,k3-pico-itx", "spacemit,k3";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0";
};
memory@100000000 {
device_type = "memory";
reg = <0x1 0x00000000 0x4 0x00000000>;
};
};
&uart0 {
status = "okay";
};
arch/riscv/boot/dts/spacemit/k3.dtsi
+578
View File
File diff suppressed because it is too large Load Diff