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Merge tag 'pef2256-framer' into devel
Immutable tag for the PEF2256 framer
This commit is contained in:
Linus Walleij
@@ -0,0 +1,213 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/lantiq,pef2256.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Lantiq PEF2256
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maintainers:
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- Herve Codina <herve.codina@bootlin.com>
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description:
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The Lantiq PEF2256, also known as Infineon PEF2256 or FALC56, is a framer and
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line interface component designed to fulfill all required interfacing between
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an analog E1/T1/J1 line and the digital PCM system highway/H.100 bus.
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properties:
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compatible:
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items:
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- const: lantiq,pef2256
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Master Clock
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- description: System Clock Receive
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- description: System Clock Transmit
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clock-names:
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items:
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- const: mclk
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- const: sclkr
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- const: sclkx
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interrupts:
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maxItems: 1
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reset-gpios:
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description:
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GPIO used to reset the device.
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maxItems: 1
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pinctrl:
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$ref: /schemas/pinctrl/pinctrl.yaml#
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additionalProperties: false
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patternProperties:
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'-pins$':
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type: object
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$ref: /schemas/pinctrl/pinmux-node.yaml#
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additionalProperties: false
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properties:
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pins:
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enum: [ RPA, RPB, RPC, RPD, XPA, XPB, XPC, XPD ]
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function:
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enum: [ SYPR, RFM, RFMB, RSIGM, RSIG, DLR, FREEZE, RFSP, LOS,
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SYPX, XFMS, XSIG, TCLK, XMFB, XSIGM, DLX, XCLK, XLT,
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GPI, GPOH, GPOL ]
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required:
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- pins
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- function
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lantiq,data-rate-bps:
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enum: [2048000, 4096000, 8192000, 16384000]
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default: 2048000
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description:
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Data rate (bit per seconds) on the system highway.
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lantiq,clock-falling-edge:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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Data is sent on falling edge of the clock (and received on the rising
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edge). If 'clock-falling-edge' is not present, data is sent on the
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rising edge (and received on the falling edge).
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lantiq,channel-phase:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3, 4, 5, 6, 7]
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default: 0
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description: |
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The pef2256 delivers a full frame (32 8-bit time-slots in E1 and 24 8-bit
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time-slots 8 8-bit signaling in E1/J1) every 125us. This lead to a data
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rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000
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bit/s, the data (all 32 8-bit) present in the frame are interleave with
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unused time-slots. The lantiq,channel-phase property allows to set the
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correct alignment of the interleave mechanism.
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For instance, suppose lantiq,data-rate-bps = 8192000 (ie 4*2048000), and
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lantiq,channel-phase = 2, the interleave schema with unused time-slots
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(nu) and used time-slots (XX) for TSi is
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nu nu XX nu nu nu XX nu nu nu XX nu
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<-- TSi --> <- TSi+1 -> <- TSi+2 ->
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With lantiq,data-rate-bps = 8192000, and lantiq,channel-phase = 1, the
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interleave schema is
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nu XX nu nu nu XX nu nu nu XX nu nu
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<-- TSi --> <- TSi+1 -> <- TSi+2 ->
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With lantiq,data-rate-bps = 4096000 (ie 2*2048000), and
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lantiq,channel-phase = 1, the interleave schema is
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nu XX nu XX nu XX
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<-- TSi --> <- TSi+1 -> <- TSi+2 ->
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patternProperties:
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'^codec(-([0-9]|[1-2][0-9]|3[0-1]))?$':
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type: object
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$ref: /schemas/sound/dai-common.yaml
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unevaluatedProperties: false
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description:
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Codec provided by the pef2256. This codec allows to use some of the PCM
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system highway time-slots as audio channels to transport audio data over
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the E1/T1/J1 lines.
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The time-slots used by the codec must be set and so, the properties
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'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
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'dai-tdm-slot-rx-mask' must be present in the sound card node for
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sub-nodes that involve the codec. The codec uses 8-bit time-slots.
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'dai-tdm-tdm-slot-with' must be set to 8.
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The tx and rx masks define the pef2256 time-slots assigned to the codec.
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properties:
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compatible:
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const: lantiq,pef2256-codec
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'#sound-dai-cells':
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const: 0
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required:
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- compatible
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- '#sound-dai-cells'
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- interrupts
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pef2256: framer@2000000 {
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compatible = "lantiq,pef2256";
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reg = <0x2000000 0x100>;
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interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&intc>;
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clocks = <&clk_mclk>, <&clk_sclkr>, <&clk_sclkx>;
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clock-names = "mclk", "sclkr", "sclkx";
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reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
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lantiq,data-rate-bps = <4096000>;
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pinctrl {
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pef2256_rpa_sypr: rpa-pins {
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pins = "RPA";
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function = "SYPR";
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};
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pef2256_xpa_sypx: xpa-pins {
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pins = "XPA";
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function = "SYPX";
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};
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};
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pef2256_codec0: codec-0 {
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compatible = "lantiq,pef2256-codec";
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#sound-dai-cells = <0>;
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sound-name-prefix = "PEF2256_0";
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};
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pef2256_codec1: codec-1 {
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compatible = "lantiq,pef2256-codec";
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#sound-dai-cells = <0>;
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sound-name-prefix = "PEF2256_1";
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};
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};
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sound {
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compatible = "simple-audio-card";
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#address-cells = <1>;
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#size-cells = <0>;
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simple-audio-card,dai-link@0 { /* CPU DAI1 - pef2256 codec 1 */
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reg = <0>;
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cpu {
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sound-dai = <&cpu_dai1>;
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};
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codec {
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sound-dai = <&pef2256_codec0>;
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dai-tdm-slot-num = <4>;
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dai-tdm-slot-width = <8>;
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/* TS 1, 2, 3, 4 */
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dai-tdm-slot-tx-mask = <0 1 1 1 1>;
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dai-tdm-slot-rx-mask = <0 1 1 1 1>;
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};
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};
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simple-audio-card,dai-link@1 { /* CPU DAI2 - pef2256 codec 2 */
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reg = <1>;
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cpu {
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sound-dai = <&cpu_dai2>;
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};
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codec {
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sound-dai = <&pef2256_codec1>;
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dai-tdm-slot-num = <4>;
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dai-tdm-slot-width = <8>;
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/* TS 5, 6, 7, 8 */
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dai-tdm-slot-tx-mask = <0 0 0 0 0 1 1 1 1>;
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dai-tdm-slot-rx-mask = <0 0 0 0 0 1 1 1 1>;
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};
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};
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};
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@@ -12028,6 +12028,14 @@ S: Maintained
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F: arch/mips/lantiq
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F: drivers/soc/lantiq
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LANTIQ PEF2256 DRIVER
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M: Herve Codina <herve.codina@bootlin.com>
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S: Maintained
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F: Documentation/devicetree/bindings/net/lantiq,pef2256.yaml
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F: drivers/net/wan/framer/pef2256/
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F: drivers/pinctrl/pinctrl-pef2256.c
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F: include/linux/framer/pef2256.h
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LASI 53c700 driver for PARISC
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M: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
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L: linux-scsi@vger.kernel.org
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@@ -95,6 +95,8 @@ config HDLC_X25
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comment "X.25/LAPB support is disabled"
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depends on HDLC && (LAPB!=m || HDLC!=m) && LAPB!=y
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source "drivers/net/wan/framer/Kconfig"
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config PCI200SYN
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tristate "Goramo PCI200SYN support"
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depends on HDLC && PCI
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@@ -14,6 +14,8 @@ obj-$(CONFIG_HDLC_FR) += hdlc_fr.o
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obj-$(CONFIG_HDLC_PPP) += hdlc_ppp.o
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obj-$(CONFIG_HDLC_X25) += hdlc_x25.o
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obj-y += framer/
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obj-$(CONFIG_FARSYNC) += farsync.o
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obj-$(CONFIG_LAPBETHER) += lapbether.o
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@@ -0,0 +1,42 @@
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# FRAMER
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#
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menuconfig FRAMER
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tristate "Framer Subsystem"
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help
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A framer is a component in charge of an E1/T1 line interface.
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Connected usually to a TDM bus, it converts TDM frames to/from E1/T1
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frames. It also provides information related to the E1/T1 line.
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Used with HDLC, the network can be reached through the E1/T1 line.
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This framework is designed to provide a generic interface for framer
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devices present in the kernel. This layer will have the generic
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API by which framer drivers can create framer using the framer
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framework and framer users can obtain reference to the framer.
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All the users of this framework should select this config.
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if FRAMER
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config GENERIC_FRAMER
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bool
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config FRAMER_PEF2256
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tristate "Lantiq PEF2256"
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depends on OF
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depends on HAS_IOMEM
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select GENERIC_FRAMER
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select MFD_CORE
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select REGMAP_MMIO
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help
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Enable support for the Lantiq PEF2256 (FALC56) framer.
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The PEF2256 is a framer and line interface between analog E1/T1/J1
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line and a digital PCM bus.
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If unsure, say N.
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To compile this driver as a module, choose M here: the
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module will be called framer-pef2256.
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endif # FRAMER
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@@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the framer drivers.
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#
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obj-$(CONFIG_GENERIC_FRAMER) += framer-core.o
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obj-$(CONFIG_FRAMER_PEF2256) += pef2256/
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the pef2256 driver.
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#
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obj-$(CONFIG_FRAMER_PEF2256) += framer-pef2256.o
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framer-pef2256-objs := pef2256.o
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@@ -0,0 +1,250 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
|
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* PEF2256 registers definition
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*
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* Copyright 2023 CS GROUP France
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*
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* Author: Herve Codina <herve.codina@bootlin.com>
|
||||
*/
|
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#ifndef __PEF2256_REGS_H__
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#define __PEF2256_REGS_H__
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#include "linux/bitfield.h"
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|
||||
/* Command Register */
|
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#define PEF2256_CMDR 0x02
|
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#define PEF2256_CMDR_RRES BIT(6)
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#define PEF2256_CMDR_XRES BIT(4)
|
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#define PEF2256_CMDR_SRES BIT(0)
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/* Interrupt Mask Register 0..5 */
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||||
#define PEF2256_IMR0 0x14
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||||
#define PEF2256_IMR1 0x15
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||||
#define PEF2256_IMR2 0x16
|
||||
#define PEF2256_IMR3 0x17
|
||||
#define PEF2256_IMR4 0x18
|
||||
#define PEF2256_IMR5 0x19
|
||||
|
||||
/* Framer Mode Register 0 */
|
||||
#define PEF2256_FMR0 0x1C
|
||||
#define PEF2256_FMR0_XC_MASK GENMASK(7, 6)
|
||||
#define PEF2256_FMR0_XC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x0)
|
||||
#define PEF2256_FMR0_XC_CMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x1)
|
||||
#define PEF2256_FMR0_XC_AMI FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x2)
|
||||
#define PEF2256_FMR0_XC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_XC_MASK, 0x3)
|
||||
#define PEF2256_FMR0_RC_MASK GENMASK(5, 4)
|
||||
#define PEF2256_FMR0_RC_NRZ FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x0)
|
||||
#define PEF2256_FMR0_RC_CMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x1)
|
||||
#define PEF2256_FMR0_RC_AMI FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x2)
|
||||
#define PEF2256_FMR0_RC_HDB3 FIELD_PREP_CONST(PEF2256_FMR0_RC_MASK, 0x3)
|
||||
|
||||
/* Framer Mode Register 1 */
|
||||
#define PEF2256_FMR1 0x1D
|
||||
#define PEF2256_FMR1_XFS BIT(3)
|
||||
#define PEF2256_FMR1_ECM BIT(2)
|
||||
/* SSD is defined on 2 bits. The other bit is on SIC1 register */
|
||||
#define PEF2256_FMR1_SSD_MASK GENMASK(1, 1)
|
||||
#define PEF2256_FMR1_SSD_2048 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
|
||||
#define PEF2256_FMR1_SSD_4096 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
|
||||
#define PEF2256_FMR1_SSD_8192 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x0)
|
||||
#define PEF2256_FMR1_SSD_16384 FIELD_PREP_CONST(PEF2256_FMR1_SSD_MASK, 0x1)
|
||||
|
||||
/* Framer Mode Register 2 */
|
||||
#define PEF2256_FMR2 0x1E
|
||||
#define PEF2256_FMR2_RFS_MASK GENMASK(7, 6)
|
||||
#define PEF2256_FMR2_RFS_DOUBLEFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x0)
|
||||
#define PEF2256_FMR2_RFS_CRC4_MULTIFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x2)
|
||||
#define PEF2256_FMR2_RFS_AUTO_MULTIFRAME FIELD_PREP_CONST(PEF2256_FMR2_RFS_MASK, 0x3)
|
||||
#define PEF2256_FMR2_AXRA BIT(1)
|
||||
|
||||
/* Transmit Service Word */
|
||||
#define PEF2256_XSW 0x20
|
||||
#define PEF2256_XSW_XSIS BIT(7)
|
||||
#define PEF2256_XSW_XTM BIT(6)
|
||||
#define PEF2256_XSW_XY_MASK GENMASK(5, 0)
|
||||
#define PEF2256_XSW_XY(_v) FIELD_PREP(PEF2256_XSW_XY_MASK, _v)
|
||||
|
||||
/* Transmit Spare Bits */
|
||||
#define PEF2256_XSP 0x21
|
||||
#define PEF2256_XSP_XSIF BIT(2)
|
||||
|
||||
/* Transmit Control 0..1 */
|
||||
#define PEF2256_XC0 0x22
|
||||
#define PEF2256_XC1 0x23
|
||||
|
||||
/* Receive Control 0 */
|
||||
#define PEF2256_RC0 0x24
|
||||
#define PEF2256_RC0_SWD BIT(7)
|
||||
#define PEF2256_RC0_ASY4 BIT(6)
|
||||
|
||||
/* Receive Control 1 */
|
||||
#define PEF2256_RC1 0x25
|
||||
|
||||
/* Transmit Pulse Mask 0..1 */
|
||||
#define PEF2256_XPM0 0x26
|
||||
#define PEF2256_XPM1 0x27
|
||||
|
||||
/* Transmit Pulse Mask 2 */
|
||||
#define PEF2256_XPM2 0x28
|
||||
#define PEF2256_XPM2_XLT BIT(6)
|
||||
|
||||
/* Transparent Service Word Mask */
|
||||
#define PEF2256_TSWM 0x29
|
||||
|
||||
/* Line Interface Mode 0 */
|
||||
#define PEF2256_LIM0 0x36
|
||||
#define PEF2256_2X_LIM0_BIT3 BIT(3) /* v2.x, described as a forced '1' bit */
|
||||
#define PEF2256_LIM0_MAS BIT(0)
|
||||
|
||||
/* Line Interface Mode 1 */
|
||||
#define PEF2256_LIM1 0x37
|
||||
#define PEF2256_12_LIM1_RIL_MASK GENMASK(6, 4)
|
||||
#define PEF2256_12_LIM1_RIL_910 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x0)
|
||||
#define PEF2256_12_LIM1_RIL_740 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x1)
|
||||
#define PEF2256_12_LIM1_RIL_590 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x2)
|
||||
#define PEF2256_12_LIM1_RIL_420 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x3)
|
||||
#define PEF2256_12_LIM1_RIL_320 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x4)
|
||||
#define PEF2256_12_LIM1_RIL_210 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x5)
|
||||
#define PEF2256_12_LIM1_RIL_160 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x6)
|
||||
#define PEF2256_12_LIM1_RIL_100 FIELD_PREP_CONST(PEF2256_12_LIM1_RIL_MASK, 0x7)
|
||||
#define PEF2256_2X_LIM1_RIL_MASK GENMASK(6, 4)
|
||||
#define PEF2256_2X_LIM1_RIL_2250 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x0)
|
||||
#define PEF2256_2X_LIM1_RIL_1100 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x1)
|
||||
#define PEF2256_2X_LIM1_RIL_600 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x2)
|
||||
#define PEF2256_2X_LIM1_RIL_350 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x3)
|
||||
#define PEF2256_2X_LIM1_RIL_210 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x4)
|
||||
#define PEF2256_2X_LIM1_RIL_140 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x5)
|
||||
#define PEF2256_2X_LIM1_RIL_100 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x6)
|
||||
#define PEF2256_2X_LIM1_RIL_50 FIELD_PREP_CONST(PEF2256_2X_LIM1_RIL_MASK, 0x7)
|
||||
|
||||
/* Pulse Count Detection */
|
||||
#define PEF2256_PCD 0x38
|
||||
|
||||
/* Pulse Count Recovery */
|
||||
#define PEF2256_PCR 0x39
|
||||
|
||||
/* Line Interface Mode 2 */
|
||||
#define PEF2256_LIM2 0x3A
|
||||
#define PEF2256_LIM2_SLT_MASK GENMASK(5, 4)
|
||||
#define PEF2256_LIM2_SLT_THR55 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x0)
|
||||
#define PEF2256_LIM2_SLT_THR67 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x1)
|
||||
#define PEF2256_LIM2_SLT_THR50 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x2)
|
||||
#define PEF2256_LIM2_SLT_THR45 FIELD_PREP_CONST(PEF2256_LIM2_SLT_MASK, 0x3)
|
||||
#define PEF2256_LIM2_ELT BIT(2)
|
||||
|
||||
/* System Interface Control 1 */
|
||||
#define PEF2256_SIC1 0x3E
|
||||
#define PEF2256_SIC1_SSC_MASK (BIT(7) | BIT(3))
|
||||
#define PEF2256_SIC1_SSC_2048 (0)
|
||||
#define PEF2256_SIC1_SSC_4096 BIT(3)
|
||||
#define PEF2256_SIC1_SSC_8192 BIT(7)
|
||||
#define PEF2256_SIC1_SSC_16384 (BIT(7) | BIT(3))
|
||||
/* SSD is defined on 2 bits. The other bit is on FMR1 register */
|
||||
#define PEF2256_SIC1_SSD_MASK GENMASK(6, 6)
|
||||
#define PEF2256_SIC1_SSD_2048 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)
|
||||
#define PEF2256_SIC1_SSD_4096 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x0)
|
||||
#define PEF2256_SIC1_SSD_8192 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)
|
||||
#define PEF2256_SIC1_SSD_16384 FIELD_PREP_CONST(PEF2256_SIC1_SSD_MASK, 0x1)
|
||||
#define PEF2256_SIC1_RBS_MASK GENMASK(5, 4)
|
||||
#define PEF2256_SIC1_RBS_2FRAMES FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x0)
|
||||
#define PEF2256_SIC1_RBS_1FRAME FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x1)
|
||||
#define PEF2256_SIC1_RBS_96BITS FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x2)
|
||||
#define PEF2256_SIC1_RBS_BYPASS FIELD_PREP_CONST(PEF2256_SIC1_RBS_MASK, 0x3)
|
||||
#define PEF2256_SIC1_XBS_MASK GENMASK(1, 0)
|
||||
#define PEF2256_SIC1_XBS_BYPASS FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x0)
|
||||
#define PEF2256_SIC1_XBS_1FRAME FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x1)
|
||||
#define PEF2256_SIC1_XBS_2FRAMES FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x2)
|
||||
#define PEF2256_SIC1_XBS_96BITS FIELD_PREP_CONST(PEF2256_SIC1_XBS_MASK, 0x3)
|
||||
|
||||
/* System Interface Control 2 */
|
||||
#define PEF2256_SIC2 0x3F
|
||||
#define PEF2256_SIC2_SICS_MASK GENMASK(3, 1)
|
||||
#define PEF2256_SIC2_SICS(_v) FIELD_PREP(PEF2256_SIC2_SICS_MASK, _v)
|
||||
|
||||
/* System Interface Control 3 */
|
||||
#define PEF2256_SIC3 0x40
|
||||
#define PEF2256_SIC3_RTRI BIT(5)
|
||||
#define PEF2256_SIC3_RESX BIT(3)
|
||||
#define PEF2256_SIC3_RESR BIT(2)
|
||||
|
||||
/* Clock Mode Register 1 */
|
||||
#define PEF2256_CMR1 0x44
|
||||
#define PEF2256_CMR1_RS_MASK GENMASK(5, 4)
|
||||
#define PEF2256_CMR1_RS_DPLL FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x0)
|
||||
#define PEF2256_CMR1_RS_DPLL_LOS_HIGH FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x1)
|
||||
#define PEF2256_CMR1_RS_DCOR_2048 FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x2)
|
||||
#define PEF2256_CMR1_RS_DCOR_8192 FIELD_PREP_CONST(PEF2256_CMR1_RS_MASK, 0x3)
|
||||
#define PEF2256_CMR1_DCS BIT(3)
|
||||
|
||||
/* Clock Mode Register 2 */
|
||||
#define PEF2256_CMR2 0x45
|
||||
#define PEF2256_CMR2_DCOXC BIT(5)
|
||||
|
||||
/* Global Configuration Register */
|
||||
#define PEF2256_GCR 0x46
|
||||
#define PEF2256_GCR_SCI BIT(6)
|
||||
#define PEF2256_GCR_ECMC BIT(4)
|
||||
|
||||
/* Port Configuration 5 */
|
||||
#define PEF2256_PC5 0x84
|
||||
#define PEF2256_PC5_CRP BIT(0)
|
||||
|
||||
/* Global Port Configuration 1 */
|
||||
#define PEF2256_GPC1 0x85
|
||||
#define PEF2256_GPC1_CSFP_MASK GENMASK(7, 5)
|
||||
#define PEF2256_GPC1_CSFP_SEC_IN_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x0)
|
||||
#define PEF2256_GPC1_CSFP_SEC_OUT_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x1)
|
||||
#define PEF2256_GPC1_CSFP_FSC_OUT_HIGH FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x2)
|
||||
#define PEF2256_GPC1_CSFP_FSC_OUT_LOW FIELD_PREP_CONST(PEF2256_GPC1_CSFP_MASK, 0x3)
|
||||
|
||||
/* Port Configuration 6 */
|
||||
#define PEF2256_PC6 0x86
|
||||
|
||||
/* Global Counter Mode n=1..8 */
|
||||
#define PEF2256_GCM(_n) (0x92 + (_n) - 1)
|
||||
#define PEF2256_GCM1 0x92
|
||||
#define PEF2256_GCM2 0x93
|
||||
#define PEF2256_GCM3 0x94
|
||||
#define PEF2256_GCM4 0x95
|
||||
#define PEF2256_GCM5 0x96
|
||||
#define PEF2256_GCM6 0x97
|
||||
#define PEF2256_GCM7 0x98
|
||||
#define PEF2256_GCM8 0x99
|
||||
|
||||
/* Version Status Register */
|
||||
#define PEF2256_VSTR 0x4A
|
||||
#define PEF2256_VSTR_VERSION_12 0x00
|
||||
#define PEF2256_VSTR_VERSION_21 0x10
|
||||
#define PEF2256_VSTR_VERSION_2x 0x05
|
||||
|
||||
/* Framer Receive Status 0 */
|
||||
#define PEF2256_FRS0 0x4C
|
||||
#define PEF2256_FRS0_LOS BIT(7)
|
||||
#define PEF2256_FRS0_AIS BIT(6)
|
||||
|
||||
/* Interrupt Status Register 0..5 */
|
||||
#define PEF2256_ISR(_n) (0x68 + (_n))
|
||||
#define PEF2256_ISR0 0x68
|
||||
#define PEF2256_ISR1 0x69
|
||||
#define PEF2256_ISR2 0x6A
|
||||
#define PEF2256_ISR3 0x6B
|
||||
#define PEF2256_ISR4 0x6C
|
||||
#define PEF2256_ISR5 0x6D
|
||||
|
||||
/* Global Interrupt Status */
|
||||
#define PEF2256_GIS 0x6E
|
||||
#define PEF2256_GIS_ISR(_n) BIT(_n)
|
||||
|
||||
/* Wafer Identification Register */
|
||||
#define PEF2256_WID 0xEC
|
||||
#define PEF2256_12_WID_MASK GENMASK(1, 0)
|
||||
#define PEF2256_12_WID_VERSION_12 FIELD_PREP_CONST(PEF2256_12_WID_MASK, 0x3)
|
||||
#define PEF2256_2X_WID_MASK GENMASK(7, 6)
|
||||
#define PEF2256_2X_WID_VERSION_21 FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x0)
|
||||
#define PEF2256_2X_WID_VERSION_22 FIELD_PREP_CONST(PEF2256_2X_WID_MASK, 0x1)
|
||||
|
||||
/* IMR2/ISR2 Interrupts common bits */
|
||||
#define PEF2256_INT2_AIS BIT(3)
|
||||
#define PEF2256_INT2_LOS BIT(2)
|
||||
|
||||
#endif /* __PEF2256_REGS_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -366,6 +366,21 @@ config PINCTRL_PALMAS
|
||||
open drain configuration for the Palmas series devices like
|
||||
TPS65913, TPS80036 etc.
|
||||
|
||||
config PINCTRL_PEF2256
|
||||
tristate "Lantiq PEF2256 (FALC56) pin controller driver"
|
||||
depends on OF && FRAMER_PEF2256
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
select GENERIC_PINCONF
|
||||
help
|
||||
This option enables the pin controller support for the Lantiq PEF2256
|
||||
framer, also known as FALC56.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
To compile this driver as a module, choose M here: the
|
||||
module will be called pinctrl-pef2256.
|
||||
|
||||
config PINCTRL_PIC32
|
||||
bool "Microchip PIC32 pin controller driver"
|
||||
depends on OF
|
||||
|
||||
@@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_MICROCHIP_SGPIO) += pinctrl-microchip-sgpio.o
|
||||
obj-$(CONFIG_PINCTRL_MLXBF3) += pinctrl-mlxbf3.o
|
||||
obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
|
||||
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
|
||||
obj-$(CONFIG_PINCTRL_PEF2256) += pinctrl-pef2256.o
|
||||
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
|
||||
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
|
||||
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
|
||||
|
||||
@@ -0,0 +1,358 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* PEF2256 also known as FALC56 driver
|
||||
*
|
||||
* Copyright 2023 CS GROUP France
|
||||
*
|
||||
* Author: Herve Codina <herve.codina@bootlin.com>
|
||||
*/
|
||||
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/framer/pef2256.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include <linux/pinctrl/pinconf-generic.h>
|
||||
#include <linux/pinctrl/pinmux.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
/* Port Configuration 1..4 */
|
||||
#define PEF2256_PC1 0x80
|
||||
#define PEF2256_PC2 0x81
|
||||
#define PEF2256_PC3 0x82
|
||||
#define PEF2256_PC4 0x83
|
||||
#define PEF2256_12_PC_RPC_MASK GENMASK(6, 4)
|
||||
#define PEF2256_12_PC_RPC_SYPR FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x0)
|
||||
#define PEF2256_12_PC_RPC_RFM FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x1)
|
||||
#define PEF2256_12_PC_RPC_RFMB FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x2)
|
||||
#define PEF2256_12_PC_RPC_RSIGM FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x3)
|
||||
#define PEF2256_12_PC_RPC_RSIG FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x4)
|
||||
#define PEF2256_12_PC_RPC_DLR FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x5)
|
||||
#define PEF2256_12_PC_RPC_FREEZE FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x6)
|
||||
#define PEF2256_12_PC_RPC_RFSP FIELD_PREP_CONST(PEF2256_12_PC_RPC_MASK, 0x7)
|
||||
#define PEF2256_12_PC_XPC_MASK GENMASK(4, 0)
|
||||
#define PEF2256_12_PC_XPC_SYPX FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x0)
|
||||
#define PEF2256_12_PC_XPC_XFMS FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x1)
|
||||
#define PEF2256_12_PC_XPC_XSIG FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x2)
|
||||
#define PEF2256_12_PC_XPC_TCLK FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x3)
|
||||
#define PEF2256_12_PC_XPC_XMFB FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x4)
|
||||
#define PEF2256_12_PC_XPC_XSIGM FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x5)
|
||||
#define PEF2256_12_PC_XPC_DLX FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x6)
|
||||
#define PEF2256_12_PC_XPC_XCLK FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x7)
|
||||
#define PEF2256_12_PC_XPC_XLT FIELD_PREP_CONST(PEF2256_12_PC_XPC_MASK, 0x8)
|
||||
#define PEF2256_2X_PC_RPC_MASK GENMASK(7, 4)
|
||||
#define PEF2256_2X_PC_RPC_SYPR FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x0)
|
||||
#define PEF2256_2X_PC_RPC_RFM FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x1)
|
||||
#define PEF2256_2X_PC_RPC_RFMB FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x2)
|
||||
#define PEF2256_2X_PC_RPC_RSIGM FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x3)
|
||||
#define PEF2256_2X_PC_RPC_RSIG FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x4)
|
||||
#define PEF2256_2X_PC_RPC_DLR FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x5)
|
||||
#define PEF2256_2X_PC_RPC_FREEZE FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x6)
|
||||
#define PEF2256_2X_PC_RPC_RFSP FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x7)
|
||||
#define PEF2256_2X_PC_RPC_GPI FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0x9)
|
||||
#define PEF2256_2X_PC_RPC_GPOH FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0xa)
|
||||
#define PEF2256_2X_PC_RPC_GPOL FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0xb)
|
||||
#define PEF2256_2X_PC_RPC_LOS FIELD_PREP_CONST(PEF2256_2X_PC_RPC_MASK, 0xc)
|
||||
#define PEF2256_2X_PC_XPC_MASK GENMASK(3, 0)
|
||||
#define PEF2256_2X_PC_XPC_SYPX FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x0)
|
||||
#define PEF2256_2X_PC_XPC_XFMS FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x1)
|
||||
#define PEF2256_2X_PC_XPC_XSIG FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x2)
|
||||
#define PEF2256_2X_PC_XPC_TCLK FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x3)
|
||||
#define PEF2256_2X_PC_XPC_XMFB FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x4)
|
||||
#define PEF2256_2X_PC_XPC_XSIGM FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x5)
|
||||
#define PEF2256_2X_PC_XPC_DLX FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x6)
|
||||
#define PEF2256_2X_PC_XPC_XCLK FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x7)
|
||||
#define PEF2256_2X_PC_XPC_XLT FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x8)
|
||||
#define PEF2256_2X_PC_XPC_GPI FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0x9)
|
||||
#define PEF2256_2X_PC_XPC_GPOH FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0xa)
|
||||
#define PEF2256_2X_PC_XPC_GPOL FIELD_PREP_CONST(PEF2256_2X_PC_XPC_MASK, 0xb)
|
||||
|
||||
struct pef2256_pinreg_desc {
|
||||
int offset;
|
||||
u8 mask;
|
||||
};
|
||||
|
||||
struct pef2256_function_desc {
|
||||
const char *name;
|
||||
const char * const*groups;
|
||||
unsigned int ngroups;
|
||||
u8 func_val;
|
||||
};
|
||||
|
||||
struct pef2256_pinctrl {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
enum pef2256_version version;
|
||||
struct pinctrl_desc pctrl_desc;
|
||||
const struct pef2256_function_desc *functions;
|
||||
unsigned int nfunctions;
|
||||
};
|
||||
|
||||
static int pef2256_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
/* We map 1 group <-> 1 pin */
|
||||
return pef2256->pctrl_desc.npins;
|
||||
}
|
||||
|
||||
static const char *pef2256_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
/* We map 1 group <-> 1 pin */
|
||||
return pef2256->pctrl_desc.pins[selector].name;
|
||||
}
|
||||
|
||||
static int pef2256_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
|
||||
const unsigned int **pins,
|
||||
unsigned int *num_pins)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
/* We map 1 group <-> 1 pin */
|
||||
*pins = &pef2256->pctrl_desc.pins[selector].number;
|
||||
*num_pins = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct pinctrl_ops pef2256_pctlops = {
|
||||
.get_groups_count = pef2256_get_groups_count,
|
||||
.get_group_name = pef2256_get_group_name,
|
||||
.get_group_pins = pef2256_get_group_pins,
|
||||
.dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
|
||||
.dt_free_map = pinconf_generic_dt_free_map,
|
||||
};
|
||||
|
||||
static int pef2256_get_functions_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pef2256->nfunctions;
|
||||
}
|
||||
|
||||
static const char *pef2256_get_function_name(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pef2256->functions[selector].name;
|
||||
}
|
||||
|
||||
static int pef2256_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
|
||||
const char * const **groups,
|
||||
unsigned * const num_groups)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = pef2256->functions[selector].groups;
|
||||
*num_groups = pef2256->functions[selector].ngroups;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pef2256_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
|
||||
unsigned int group_selector)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256 = pinctrl_dev_get_drvdata(pctldev);
|
||||
const struct pef2256_pinreg_desc *pinreg_desc;
|
||||
u8 func_val;
|
||||
|
||||
/* We map 1 group <-> 1 pin */
|
||||
pinreg_desc = pef2256->pctrl_desc.pins[group_selector].drv_data;
|
||||
func_val = pef2256->functions[func_selector].func_val;
|
||||
|
||||
return regmap_update_bits(pef2256->regmap, pinreg_desc->offset,
|
||||
pinreg_desc->mask, func_val);
|
||||
}
|
||||
|
||||
static const struct pinmux_ops pef2256_pmxops = {
|
||||
.get_functions_count = pef2256_get_functions_count,
|
||||
.get_function_name = pef2256_get_function_name,
|
||||
.get_function_groups = pef2256_get_function_groups,
|
||||
.set_mux = pef2256_set_mux,
|
||||
};
|
||||
|
||||
#define PEF2256_PINCTRL_PIN(_number, _name, _offset, _mask) { \
|
||||
.number = _number, \
|
||||
.name = _name, \
|
||||
.drv_data = &(struct pef2256_pinreg_desc) { \
|
||||
.offset = _offset, \
|
||||
.mask = _mask, \
|
||||
}, \
|
||||
}
|
||||
|
||||
static const struct pinctrl_pin_desc pef2256_v12_pins[] = {
|
||||
PEF2256_PINCTRL_PIN(0, "RPA", PEF2256_PC1, PEF2256_12_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(1, "RPB", PEF2256_PC2, PEF2256_12_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(2, "RPC", PEF2256_PC3, PEF2256_12_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(3, "RPD", PEF2256_PC4, PEF2256_12_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(4, "XPA", PEF2256_PC1, PEF2256_12_PC_XPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(5, "XPB", PEF2256_PC2, PEF2256_12_PC_XPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(6, "XPC", PEF2256_PC3, PEF2256_12_PC_XPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(7, "XPD", PEF2256_PC4, PEF2256_12_PC_XPC_MASK),
|
||||
};
|
||||
|
||||
static const struct pinctrl_pin_desc pef2256_v2x_pins[] = {
|
||||
PEF2256_PINCTRL_PIN(0, "RPA", PEF2256_PC1, PEF2256_2X_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(1, "RPB", PEF2256_PC2, PEF2256_2X_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(2, "RPC", PEF2256_PC3, PEF2256_2X_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(3, "RPD", PEF2256_PC4, PEF2256_2X_PC_RPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(4, "XPA", PEF2256_PC1, PEF2256_2X_PC_XPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(5, "XPB", PEF2256_PC2, PEF2256_2X_PC_XPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(6, "XPC", PEF2256_PC3, PEF2256_2X_PC_XPC_MASK),
|
||||
PEF2256_PINCTRL_PIN(7, "XPD", PEF2256_PC4, PEF2256_2X_PC_XPC_MASK),
|
||||
};
|
||||
|
||||
static const char *const pef2256_rp_groups[] = { "RPA", "RPB", "RPC", "RPD" };
|
||||
static const char *const pef2256_xp_groups[] = { "XPA", "XPB", "XPC", "XPD" };
|
||||
static const char *const pef2256_all_groups[] = { "RPA", "RPB", "RPC", "RPD",
|
||||
"XPA", "XPB", "XPC", "XPD" };
|
||||
|
||||
#define PEF2256_FUNCTION(_name, _func_val, _groups) { \
|
||||
.name = _name, \
|
||||
.groups = _groups, \
|
||||
.ngroups = ARRAY_SIZE(_groups), \
|
||||
.func_val = _func_val, \
|
||||
}
|
||||
|
||||
static const struct pef2256_function_desc pef2256_v2x_functions[] = {
|
||||
PEF2256_FUNCTION("SYPR", PEF2256_2X_PC_RPC_SYPR, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RFM", PEF2256_2X_PC_RPC_RFM, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RFMB", PEF2256_2X_PC_RPC_RFMB, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RSIGM", PEF2256_2X_PC_RPC_RSIGM, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RSIG", PEF2256_2X_PC_RPC_RSIG, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("DLR", PEF2256_2X_PC_RPC_DLR, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("FREEZE", PEF2256_2X_PC_RPC_FREEZE, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RFSP", PEF2256_2X_PC_RPC_RFSP, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("LOS", PEF2256_2X_PC_RPC_LOS, pef2256_rp_groups),
|
||||
|
||||
PEF2256_FUNCTION("SYPX", PEF2256_2X_PC_XPC_SYPX, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XFMS", PEF2256_2X_PC_XPC_XFMS, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XSIG", PEF2256_2X_PC_XPC_XSIG, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("TCLK", PEF2256_2X_PC_XPC_TCLK, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XMFB", PEF2256_2X_PC_XPC_XMFB, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XSIGM", PEF2256_2X_PC_XPC_XSIGM, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("DLX", PEF2256_2X_PC_XPC_DLX, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XCLK", PEF2256_2X_PC_XPC_XCLK, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XLT", PEF2256_2X_PC_XPC_XLT, pef2256_xp_groups),
|
||||
|
||||
PEF2256_FUNCTION("GPI", PEF2256_2X_PC_RPC_GPI | PEF2256_2X_PC_XPC_GPI,
|
||||
pef2256_all_groups),
|
||||
PEF2256_FUNCTION("GPOH", PEF2256_2X_PC_RPC_GPOH | PEF2256_2X_PC_XPC_GPOH,
|
||||
pef2256_all_groups),
|
||||
PEF2256_FUNCTION("GPOL", PEF2256_2X_PC_RPC_GPOL | PEF2256_2X_PC_XPC_GPOL,
|
||||
pef2256_all_groups),
|
||||
};
|
||||
|
||||
static const struct pef2256_function_desc pef2256_v12_functions[] = {
|
||||
PEF2256_FUNCTION("SYPR", PEF2256_12_PC_RPC_SYPR, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RFM", PEF2256_12_PC_RPC_RFM, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RFMB", PEF2256_12_PC_RPC_RFMB, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RSIGM", PEF2256_12_PC_RPC_RSIGM, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RSIG", PEF2256_12_PC_RPC_RSIG, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("DLR", PEF2256_12_PC_RPC_DLR, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("FREEZE", PEF2256_12_PC_RPC_FREEZE, pef2256_rp_groups),
|
||||
PEF2256_FUNCTION("RFSP", PEF2256_12_PC_RPC_RFSP, pef2256_rp_groups),
|
||||
|
||||
PEF2256_FUNCTION("SYPX", PEF2256_12_PC_XPC_SYPX, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XFMS", PEF2256_12_PC_XPC_XFMS, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XSIG", PEF2256_12_PC_XPC_XSIG, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("TCLK", PEF2256_12_PC_XPC_TCLK, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XMFB", PEF2256_12_PC_XPC_XMFB, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XSIGM", PEF2256_12_PC_XPC_XSIGM, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("DLX", PEF2256_12_PC_XPC_DLX, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XCLK", PEF2256_12_PC_XPC_XCLK, pef2256_xp_groups),
|
||||
PEF2256_FUNCTION("XLT", PEF2256_12_PC_XPC_XLT, pef2256_xp_groups),
|
||||
};
|
||||
|
||||
static int pef2256_register_pinctrl(struct pef2256_pinctrl *pef2256)
|
||||
{
|
||||
struct pinctrl_dev *pctrl;
|
||||
|
||||
pef2256->pctrl_desc.name = dev_name(pef2256->dev);
|
||||
pef2256->pctrl_desc.owner = THIS_MODULE;
|
||||
pef2256->pctrl_desc.pctlops = &pef2256_pctlops;
|
||||
pef2256->pctrl_desc.pmxops = &pef2256_pmxops;
|
||||
if (pef2256->version == PEF2256_VERSION_1_2) {
|
||||
pef2256->pctrl_desc.pins = pef2256_v12_pins;
|
||||
pef2256->pctrl_desc.npins = ARRAY_SIZE(pef2256_v12_pins);
|
||||
pef2256->functions = pef2256_v12_functions;
|
||||
pef2256->nfunctions = ARRAY_SIZE(pef2256_v12_functions);
|
||||
} else {
|
||||
pef2256->pctrl_desc.pins = pef2256_v2x_pins;
|
||||
pef2256->pctrl_desc.npins = ARRAY_SIZE(pef2256_v2x_pins);
|
||||
pef2256->functions = pef2256_v2x_functions;
|
||||
pef2256->nfunctions = ARRAY_SIZE(pef2256_v2x_functions);
|
||||
}
|
||||
|
||||
pctrl = devm_pinctrl_register(pef2256->dev, &pef2256->pctrl_desc, pef2256);
|
||||
if (IS_ERR(pctrl))
|
||||
return dev_err_probe(pef2256->dev, PTR_ERR(pctrl),
|
||||
"pinctrl driver registration failed\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void pef2256_reset_pinmux(struct pef2256_pinctrl *pef2256)
|
||||
{
|
||||
u8 val;
|
||||
/*
|
||||
* Reset values cannot be used.
|
||||
* They define the SYPR/SYPX pin mux for all the RPx and XPx pins and
|
||||
* Only one pin can be muxed to SYPR and one pin can be muxed to SYPX.
|
||||
* Choose here an other reset value.
|
||||
*/
|
||||
if (pef2256->version == PEF2256_VERSION_1_2)
|
||||
val = PEF2256_12_PC_XPC_XCLK | PEF2256_12_PC_RPC_RFSP;
|
||||
else
|
||||
val = PEF2256_2X_PC_XPC_GPI | PEF2256_2X_PC_RPC_GPI;
|
||||
|
||||
regmap_write(pef2256->regmap, PEF2256_PC1, val);
|
||||
regmap_write(pef2256->regmap, PEF2256_PC2, val);
|
||||
regmap_write(pef2256->regmap, PEF2256_PC3, val);
|
||||
regmap_write(pef2256->regmap, PEF2256_PC4, val);
|
||||
}
|
||||
|
||||
static int pef2256_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct pef2256_pinctrl *pef2256_pinctrl;
|
||||
struct pef2256 *pef2256;
|
||||
int ret;
|
||||
|
||||
pef2256_pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pef2256_pinctrl), GFP_KERNEL);
|
||||
if (!pef2256_pinctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent));
|
||||
|
||||
pef2256 = dev_get_drvdata(pdev->dev.parent);
|
||||
|
||||
pef2256_pinctrl->dev = &pdev->dev;
|
||||
pef2256_pinctrl->regmap = pef2256_get_regmap(pef2256);
|
||||
pef2256_pinctrl->version = pef2256_get_version(pef2256);
|
||||
|
||||
platform_set_drvdata(pdev, pef2256_pinctrl);
|
||||
|
||||
pef2256_reset_pinmux(pef2256_pinctrl);
|
||||
ret = pef2256_register_pinctrl(pef2256_pinctrl);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver pef2256_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "lantiq-pef2256-pinctrl",
|
||||
},
|
||||
.probe = pef2256_pinctrl_probe,
|
||||
};
|
||||
module_platform_driver(pef2256_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
|
||||
MODULE_DESCRIPTION("PEF2256 pin controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@@ -0,0 +1,194 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Generic framer profider header file
|
||||
*
|
||||
* Copyright 2023 CS GROUP France
|
||||
*
|
||||
* Author: Herve Codina <herve.codina@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_PROVIDER_FRAMER_H
|
||||
#define __DRIVERS_PROVIDER_FRAMER_H
|
||||
|
||||
#include <linux/export.h>
|
||||
#include <linux/framer/framer.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define FRAMER_FLAG_POLL_STATUS BIT(0)
|
||||
|
||||
/**
|
||||
* struct framer_ops - set of function pointers for performing framer operations
|
||||
* @init: operation to be performed for initializing the framer
|
||||
* @exit: operation to be performed while exiting
|
||||
* @power_on: powering on the framer
|
||||
* @power_off: powering off the framer
|
||||
* @flags: OR-ed flags (FRAMER_FLAG_*) to ask for core functionality
|
||||
* - @FRAMER_FLAG_POLL_STATUS:
|
||||
* Ask the core to perform a polling to get the framer status and
|
||||
* notify consumers on change.
|
||||
* The framer should call @framer_notify_status_change() when it
|
||||
* detects a status change. This is usually done using interrupts.
|
||||
* If the framer cannot detect this change, it can ask the core for
|
||||
* a status polling. The core will call @get_status() periodically
|
||||
* and, on change detected, it will notify the consumer.
|
||||
* the @get_status()
|
||||
* @owner: the module owner containing the ops
|
||||
*/
|
||||
struct framer_ops {
|
||||
int (*init)(struct framer *framer);
|
||||
void (*exit)(struct framer *framer);
|
||||
int (*power_on)(struct framer *framer);
|
||||
int (*power_off)(struct framer *framer);
|
||||
|
||||
/**
|
||||
* @get_status:
|
||||
*
|
||||
* Optional.
|
||||
*
|
||||
* Used to get the framer status. framer_init() must have
|
||||
* been called on the framer.
|
||||
*
|
||||
* Returns: 0 if successful, an negative error code otherwise
|
||||
*/
|
||||
int (*get_status)(struct framer *framer, struct framer_status *status);
|
||||
|
||||
/**
|
||||
* @set_config:
|
||||
*
|
||||
* Optional.
|
||||
*
|
||||
* Used to set the framer configuration. framer_init() must have
|
||||
* been called on the framer.
|
||||
*
|
||||
* Returns: 0 if successful, an negative error code otherwise
|
||||
*/
|
||||
int (*set_config)(struct framer *framer, const struct framer_config *config);
|
||||
|
||||
/**
|
||||
* @get_config:
|
||||
*
|
||||
* Optional.
|
||||
*
|
||||
* Used to get the framer configuration. framer_init() must have
|
||||
* been called on the framer.
|
||||
*
|
||||
* Returns: 0 if successful, an negative error code otherwise
|
||||
*/
|
||||
int (*get_config)(struct framer *framer, struct framer_config *config);
|
||||
|
||||
u32 flags;
|
||||
struct module *owner;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct framer_provider - represents the framer provider
|
||||
* @dev: framer provider device
|
||||
* @children: can be used to override the default (dev->of_node) child node
|
||||
* @owner: the module owner having of_xlate
|
||||
* @list: to maintain a linked list of framer providers
|
||||
* @of_xlate: function pointer to obtain framer instance from framer pointer
|
||||
*/
|
||||
struct framer_provider {
|
||||
struct device *dev;
|
||||
struct module *owner;
|
||||
struct list_head list;
|
||||
struct framer * (*of_xlate)(struct device *dev,
|
||||
struct of_phandle_args *args);
|
||||
};
|
||||
|
||||
static inline void framer_set_drvdata(struct framer *framer, void *data)
|
||||
{
|
||||
dev_set_drvdata(&framer->dev, data);
|
||||
}
|
||||
|
||||
static inline void *framer_get_drvdata(struct framer *framer)
|
||||
{
|
||||
return dev_get_drvdata(&framer->dev);
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_GENERIC_FRAMER)
|
||||
|
||||
/* Create and destroy a framer */
|
||||
struct framer *framer_create(struct device *dev, struct device_node *node,
|
||||
const struct framer_ops *ops);
|
||||
void framer_destroy(struct framer *framer);
|
||||
|
||||
/* devm version */
|
||||
struct framer *devm_framer_create(struct device *dev, struct device_node *node,
|
||||
const struct framer_ops *ops);
|
||||
|
||||
struct framer *framer_provider_simple_of_xlate(struct device *dev,
|
||||
struct of_phandle_args *args);
|
||||
|
||||
struct framer_provider *
|
||||
__framer_provider_of_register(struct device *dev, struct module *owner,
|
||||
struct framer *(*of_xlate)(struct device *dev,
|
||||
struct of_phandle_args *args));
|
||||
|
||||
void framer_provider_of_unregister(struct framer_provider *framer_provider);
|
||||
|
||||
struct framer_provider *
|
||||
__devm_framer_provider_of_register(struct device *dev, struct module *owner,
|
||||
struct framer *(*of_xlate)(struct device *dev,
|
||||
struct of_phandle_args *args));
|
||||
|
||||
void framer_notify_status_change(struct framer *framer);
|
||||
|
||||
#else /* IS_ENABLED(CONFIG_GENERIC_FRAMER) */
|
||||
|
||||
static inline struct framer *framer_create(struct device *dev, struct device_node *node,
|
||||
const struct framer_ops *ops)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
static inline void framer_destroy(struct framer *framer)
|
||||
{
|
||||
}
|
||||
|
||||
/* devm version */
|
||||
static inline struct framer *devm_framer_create(struct device *dev, struct device_node *node,
|
||||
const struct framer_ops *ops)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
static inline struct framer *framer_provider_simple_of_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
static inline struct framer_provider *
|
||||
__framer_provider_of_register(struct device *dev, struct module *owner,
|
||||
struct framer *(*of_xlate)(struct device *dev,
|
||||
struct of_phandle_args *args))
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
void framer_provider_of_unregister(struct framer_provider *framer_provider)
|
||||
{
|
||||
}
|
||||
|
||||
static inline struct framer_provider *
|
||||
__devm_framer_provider_of_register(struct device *dev, struct module *owner,
|
||||
struct framer *(*of_xlate)(struct device *dev,
|
||||
struct of_phandle_args *args))
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
void framer_notify_status_change(struct framer *framer)
|
||||
{
|
||||
}
|
||||
|
||||
#endif /* IS_ENABLED(CONFIG_GENERIC_FRAMER) */
|
||||
|
||||
#define framer_provider_of_register(dev, xlate) \
|
||||
__framer_provider_of_register((dev), THIS_MODULE, (xlate))
|
||||
|
||||
#define devm_framer_provider_of_register(dev, xlate) \
|
||||
__devm_framer_provider_of_register((dev), THIS_MODULE, (xlate))
|
||||
|
||||
#endif /* __DRIVERS_PROVIDER_FRAMER_H */
|
||||
@@ -0,0 +1,205 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* Generic framer header file
|
||||
*
|
||||
* Copyright 2023 CS GROUP France
|
||||
*
|
||||
* Author: Herve Codina <herve.codina@bootlin.com>
|
||||
*/
|
||||
|
||||
#ifndef __DRIVERS_FRAMER_H
|
||||
#define __DRIVERS_FRAMER_H
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/workqueue.h>
|
||||
|
||||
/**
|
||||
* enum framer_iface - Framer interface
|
||||
* @FRAMER_IFACE_E1: E1 interface
|
||||
* @FRAMER_IFACE_T1: T1 interface
|
||||
*/
|
||||
enum framer_iface {
|
||||
FRAMER_IFACE_E1,
|
||||
FRAMER_IFACE_T1,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum framer_clock_type - Framer clock type
|
||||
* @FRAMER_CLOCK_EXT: External clock
|
||||
* @FRAMER_CLOCK_INT: Internal clock
|
||||
*/
|
||||
enum framer_clock_type {
|
||||
FRAMER_CLOCK_EXT,
|
||||
FRAMER_CLOCK_INT,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct framer_config - Framer configuration
|
||||
* @iface: Framer line interface
|
||||
* @clock_type: Framer clock type
|
||||
* @line_clock_rate: Framer line clock rate
|
||||
*/
|
||||
struct framer_config {
|
||||
enum framer_iface iface;
|
||||
enum framer_clock_type clock_type;
|
||||
unsigned long line_clock_rate;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct framer_status - Framer status
|
||||
* @link_is_on: Framer link state. true, the link is on, false, the link is off.
|
||||
*/
|
||||
struct framer_status {
|
||||
bool link_is_on;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum framer_event - Event available for notification
|
||||
* @FRAMER_EVENT_STATUS: Event notified on framer_status changes
|
||||
*/
|
||||
enum framer_event {
|
||||
FRAMER_EVENT_STATUS,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct framer - represents the framer device
|
||||
* @dev: framer device
|
||||
* @id: id of the framer device
|
||||
* @ops: function pointers for performing framer operations
|
||||
* @mutex: mutex to protect framer_ops
|
||||
* @init_count: used to protect when the framer is used by multiple consumers
|
||||
* @power_count: used to protect when the framer is used by multiple consumers
|
||||
* @pwr: power regulator associated with the framer
|
||||
* @notify_status_work: work structure used for status notifications
|
||||
* @notifier_list: notifier list used for notifications
|
||||
* @polling_work: delayed work structure used for the polling task
|
||||
* @prev_status: previous read status used by the polling task to detect changes
|
||||
*/
|
||||
struct framer {
|
||||
struct device dev;
|
||||
int id;
|
||||
const struct framer_ops *ops;
|
||||
struct mutex mutex; /* Protect framer */
|
||||
int init_count;
|
||||
int power_count;
|
||||
struct regulator *pwr;
|
||||
struct work_struct notify_status_work;
|
||||
struct blocking_notifier_head notifier_list;
|
||||
struct delayed_work polling_work;
|
||||
struct framer_status prev_status;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_GENERIC_FRAMER)
|
||||
int framer_pm_runtime_get(struct framer *framer);
|
||||
int framer_pm_runtime_get_sync(struct framer *framer);
|
||||
int framer_pm_runtime_put(struct framer *framer);
|
||||
int framer_pm_runtime_put_sync(struct framer *framer);
|
||||
int framer_init(struct framer *framer);
|
||||
int framer_exit(struct framer *framer);
|
||||
int framer_power_on(struct framer *framer);
|
||||
int framer_power_off(struct framer *framer);
|
||||
int framer_get_status(struct framer *framer, struct framer_status *status);
|
||||
int framer_get_config(struct framer *framer, struct framer_config *config);
|
||||
int framer_set_config(struct framer *framer, const struct framer_config *config);
|
||||
int framer_notifier_register(struct framer *framer, struct notifier_block *nb);
|
||||
int framer_notifier_unregister(struct framer *framer, struct notifier_block *nb);
|
||||
|
||||
struct framer *framer_get(struct device *dev, const char *con_id);
|
||||
void framer_put(struct device *dev, struct framer *framer);
|
||||
|
||||
struct framer *devm_framer_get(struct device *dev, const char *con_id);
|
||||
struct framer *devm_framer_optional_get(struct device *dev, const char *con_id);
|
||||
#else
|
||||
static inline int framer_pm_runtime_get(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_pm_runtime_get_sync(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_pm_runtime_put(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_pm_runtime_put_sync(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_init(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_exit(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_power_on(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_power_off(struct framer *framer)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_get_status(struct framer *framer, struct framer_status *status)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_get_config(struct framer *framer, struct framer_config *config)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_set_config(struct framer *framer, const struct framer_config *config)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_notifier_register(struct framer *framer,
|
||||
struct notifier_block *nb)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int framer_notifier_unregister(struct framer *framer,
|
||||
struct notifier_block *nb)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
struct framer *framer_get(struct device *dev, const char *con_id)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
void framer_put(struct device *dev, struct framer *framer)
|
||||
{
|
||||
}
|
||||
|
||||
static inline struct framer *devm_framer_get(struct device *dev, const char *con_id)
|
||||
{
|
||||
return ERR_PTR(-ENOSYS);
|
||||
}
|
||||
|
||||
static inline struct framer *devm_framer_optional_get(struct device *dev, const char *con_id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __DRIVERS_FRAMER_H */
|
||||
@@ -0,0 +1,31 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/*
|
||||
* PEF2256 consumer API
|
||||
*
|
||||
* Copyright 2023 CS GROUP France
|
||||
*
|
||||
* Author: Herve Codina <herve.codina@bootlin.com>
|
||||
*/
|
||||
#ifndef __PEF2256_H__
|
||||
#define __PEF2256_H__
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct pef2256;
|
||||
struct regmap;
|
||||
|
||||
/* Retrieve the PEF2256 regmap */
|
||||
struct regmap *pef2256_get_regmap(struct pef2256 *pef2256);
|
||||
|
||||
/* PEF2256 hardware versions */
|
||||
enum pef2256_version {
|
||||
PEF2256_VERSION_UNKNOWN,
|
||||
PEF2256_VERSION_1_2,
|
||||
PEF2256_VERSION_2_1,
|
||||
PEF2256_VERSION_2_2,
|
||||
};
|
||||
|
||||
/* Get the PEF2256 hardware version */
|
||||
enum pef2256_version pef2256_get_version(struct pef2256 *pef2256);
|
||||
|
||||
#endif /* __PEF2256_H__ */
|
||||
Reference in New Issue
Block a user