mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branch 'pm-powercap'
Merge power capping updates for 7.1-rc1: - Clean up and rearrange the intel_rapl power capping driver to make the respective interface drivers (TPMI, MSR, and MMOI) hold their own settings and primitives and consolidate PL4 and PMU support flags into rapl_defaults (Kuppuswamy Sathyanarayanan) - Correct kernel-doc function parameter names in the power capping core code (Randy Dunlap) * pm-powercap: powercap: intel_rapl: Consolidate PL4 and PMU support flags into rapl_defaults powercap: intel_rapl: Move MSR primitives to MSR driver thermal: intel: int340x: processor: Move MMIO primitives to MMIO driver powercap: intel_rapl: Move TPMI primitives to TPMI driver powercap: intel_rapl: Move primitive info to header for interface drivers powercap: intel_rapl: Remove unused macro definitions powercap: intel_rapl: Move MSR default settings into MSR interface driver powercap: intel_rapl: Remove unused AVERAGE_POWER primitive powercap: correct kernel-doc function parameter names thermal: intel: int340x: processor: Move RAPL defaults to MMIO driver powercap: intel_rapl: Move TPMI default settings into TPMI interface driver powercap: intel_rapl: Allow interface drivers to configure rapl_defaults powercap: intel_rapl: Use unit conversion macros from units.h powercap: intel_rapl: Use GENMASK() and BIT() macros powercap: intel_rapl: Use shifts for power-of-2 operations powercap: intel_rapl: Simplify rapl_compute_time_window_atom() powercap: intel_rapl: Remove unused TIME_WINDOW macros powercap: intel_rapl: Cleanup coding style powercap: intel_rapl: Add a symbol namespace for intel_rapl exports
This commit is contained in:
Rafael J. Wysocki
File diff suppressed because it is too large
Load Diff
@@ -21,15 +21,73 @@
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#include <linux/intel_rapl.h>
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#include <linux/processor.h>
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#include <linux/platform_device.h>
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#include <linux/units.h>
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#include <linux/bits.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/iosf_mbi.h>
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#include <asm/msr.h>
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/* Local defines */
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#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
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#define MSR_VR_CURRENT_CONFIG 0x00000601
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#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
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#define POWER_UNIT_OFFSET 0x00
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#define POWER_UNIT_MASK GENMASK(3, 0)
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#define ENERGY_UNIT_OFFSET 0x08
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#define ENERGY_UNIT_MASK GENMASK(12, 8)
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#define TIME_UNIT_OFFSET 0x10
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#define TIME_UNIT_MASK GENMASK(19, 16)
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/* bitmasks for RAPL MSRs, used by primitive access functions */
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#define ENERGY_STATUS_MASK GENMASK(31, 0)
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#define POWER_LIMIT1_MASK GENMASK(14, 0)
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#define POWER_LIMIT1_ENABLE BIT(15)
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#define POWER_LIMIT1_CLAMP BIT(16)
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#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
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#define POWER_LIMIT2_ENABLE BIT_ULL(47)
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#define POWER_LIMIT2_CLAMP BIT_ULL(48)
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#define POWER_HIGH_LOCK BIT_ULL(63)
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#define POWER_LOW_LOCK BIT(31)
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#define POWER_LIMIT4_MASK GENMASK(12, 0)
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#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
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#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
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#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
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#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
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#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
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#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
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#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
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#define PP_POLICY_MASK GENMASK(4, 0)
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/*
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* SPR has different layout for Psys Domain PowerLimit registers.
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* There are 17 bits of PL1 and PL2 instead of 15 bits.
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* The Enable bits and TimeWindow bits are also shifted as a result.
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*/
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#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)
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#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
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#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)
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#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
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#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)
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#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)
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/* Sideband MBI registers */
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#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02
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#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF
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/* private data for RAPL MSR Interface */
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static struct rapl_if_priv *rapl_msr_priv;
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@@ -158,36 +216,278 @@ static int rapl_msr_write_raw(int cpu, struct reg_action *ra)
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return ra->err;
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}
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/* List of verified CPUs. */
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static const struct x86_cpu_id pl4_support_ids[] = {
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X86_MATCH_VFM(INTEL_ICELAKE_L, NULL),
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X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_ALDERLAKE, NULL),
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X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL),
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X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL),
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X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL),
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X86_MATCH_VFM(INTEL_METEORLAKE, NULL),
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X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_ARROWLAKE_U, NULL),
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X86_MATCH_VFM(INTEL_ARROWLAKE_H, NULL),
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X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_NOVALAKE, NULL),
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X86_MATCH_VFM(INTEL_NOVALAKE_L, NULL),
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{}
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static int rapl_check_unit_atom(struct rapl_domain *rd)
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{
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struct reg_action ra;
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u32 value;
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ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
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ra.mask = ~0;
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if (rapl_msr_read_raw(rd->rp->lead_cpu, &ra, false)) {
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pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
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ra.reg.val, rd->rp->name, rd->name);
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return -ENODEV;
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}
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value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
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rd->energy_unit = ENERGY_UNIT_SCALE * (1ULL << value);
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value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
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rd->power_unit = (1ULL << value) * MILLIWATT_PER_WATT;
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value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
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rd->time_unit = USEC_PER_SEC >> value;
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pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n",
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rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
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return 0;
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}
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static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
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{
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static u32 power_ctrl_orig_val;
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const struct rapl_defaults *defaults = rd->rp->priv->defaults;
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u32 mdata;
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if (!defaults->floor_freq_reg_addr) {
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pr_err("Invalid floor frequency config register\n");
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return;
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}
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if (!power_ctrl_orig_val)
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iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
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defaults->floor_freq_reg_addr,
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&power_ctrl_orig_val);
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mdata = power_ctrl_orig_val;
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if (enable) {
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mdata &= ~GENMASK(14, 8);
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mdata |= BIT(8);
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}
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iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
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defaults->floor_freq_reg_addr, mdata);
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}
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static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
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bool to_raw)
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{
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if (to_raw)
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return div64_u64(value, rd->time_unit);
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/*
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* Atom time unit encoding is straight forward val * time_unit,
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* where time_unit is default to 1 sec. Never 0.
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*/
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return value ? value * rd->time_unit : rd->time_unit;
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}
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/* RAPL primitives for MSR I/F */
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static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
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/* name, mask, shift, msr index, unit divisor */
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[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
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RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
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[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
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RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
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[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
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POWER_INFO_THERMAL_SPEC_MASK, 0,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
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POWER_INFO_MAX_TIME_WIN_MASK, 48,
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RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
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[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
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PERF_STATUS_THROTTLE_TIME_MASK, 0,
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RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
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[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
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RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
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[PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK,
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32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE,
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17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
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0),
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[PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE,
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49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
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0),
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[PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK,
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19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK,
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51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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};
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/* List of MSR-based RAPL PMU support CPUs */
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static const struct x86_cpu_id pmu_support_ids[] = {
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X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL),
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X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL),
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static const struct rapl_defaults rapl_defaults_core = {
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.floor_freq_reg_addr = 0,
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.check_unit = rapl_default_check_unit,
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.set_floor_freq = rapl_default_set_floor_freq,
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.compute_time_window = rapl_default_compute_time_window,
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};
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static const struct rapl_defaults rapl_defaults_hsw_server = {
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.check_unit = rapl_default_check_unit,
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.set_floor_freq = rapl_default_set_floor_freq,
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.compute_time_window = rapl_default_compute_time_window,
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.dram_domain_energy_unit = 15300,
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};
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static const struct rapl_defaults rapl_defaults_spr_server = {
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.check_unit = rapl_default_check_unit,
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.set_floor_freq = rapl_default_set_floor_freq,
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.compute_time_window = rapl_default_compute_time_window,
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.psys_domain_energy_unit = NANOJOULE_PER_JOULE,
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.spr_psys_bits = true,
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};
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static const struct rapl_defaults rapl_defaults_byt = {
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.floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
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.check_unit = rapl_check_unit_atom,
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.set_floor_freq = set_floor_freq_atom,
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.compute_time_window = rapl_compute_time_window_atom,
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};
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static const struct rapl_defaults rapl_defaults_tng = {
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.floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
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.check_unit = rapl_check_unit_atom,
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.set_floor_freq = set_floor_freq_atom,
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.compute_time_window = rapl_compute_time_window_atom,
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};
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static const struct rapl_defaults rapl_defaults_ann = {
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.floor_freq_reg_addr = 0,
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.check_unit = rapl_check_unit_atom,
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.set_floor_freq = NULL,
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.compute_time_window = rapl_compute_time_window_atom,
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};
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static const struct rapl_defaults rapl_defaults_cht = {
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.floor_freq_reg_addr = 0,
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.check_unit = rapl_check_unit_atom,
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.set_floor_freq = NULL,
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.compute_time_window = rapl_compute_time_window_atom,
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};
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static const struct rapl_defaults rapl_defaults_amd = {
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.check_unit = rapl_default_check_unit,
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};
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static const struct rapl_defaults rapl_defaults_core_pl4 = {
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.floor_freq_reg_addr = 0,
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.check_unit = rapl_default_check_unit,
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.set_floor_freq = rapl_default_set_floor_freq,
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.compute_time_window = rapl_default_compute_time_window,
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.msr_pl4_support = 1,
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};
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static const struct rapl_defaults rapl_defaults_core_pl4_pmu = {
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.floor_freq_reg_addr = 0,
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.check_unit = rapl_default_check_unit,
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.set_floor_freq = rapl_default_set_floor_freq,
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.compute_time_window = rapl_default_compute_time_window,
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.msr_pl4_support = 1,
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.msr_pmu_support = 1,
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};
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static const struct x86_cpu_id rapl_ids[] = {
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X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server),
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X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server),
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X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core),
|
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X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server),
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X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
|
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X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
|
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X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
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X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
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X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
|
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X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
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X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core_pl4),
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X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
|
||||
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
|
||||
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core_pl4_pmu),
|
||||
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core_pl4_pmu),
|
||||
X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core_pl4),
|
||||
X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
|
||||
|
||||
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
|
||||
X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht),
|
||||
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng),
|
||||
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann),
|
||||
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core),
|
||||
X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core),
|
||||
|
||||
X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server),
|
||||
X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server),
|
||||
|
||||
X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd),
|
||||
X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd),
|
||||
X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd),
|
||||
X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd),
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
|
||||
|
||||
static int rapl_msr_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
|
||||
int ret;
|
||||
|
||||
switch (boot_cpu_data.x86_vendor) {
|
||||
@@ -204,17 +504,19 @@ static int rapl_msr_probe(struct platform_device *pdev)
|
||||
}
|
||||
rapl_msr_priv->read_raw = rapl_msr_read_raw;
|
||||
rapl_msr_priv->write_raw = rapl_msr_write_raw;
|
||||
rapl_msr_priv->defaults = (const struct rapl_defaults *)pdev->dev.platform_data;
|
||||
rapl_msr_priv->rpi = rpi_msr;
|
||||
|
||||
if (id) {
|
||||
if (rapl_msr_priv->defaults->msr_pl4_support) {
|
||||
rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4);
|
||||
rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4].msr =
|
||||
MSR_VR_CURRENT_CONFIG;
|
||||
pr_info("PL4 support detected.\n");
|
||||
pr_info("PL4 support detected (updated).\n");
|
||||
}
|
||||
|
||||
if (x86_match_cpu(pmu_support_ids)) {
|
||||
if (rapl_msr_priv->defaults->msr_pmu_support) {
|
||||
rapl_msr_pmu = true;
|
||||
pr_info("MSR-based RAPL PMU support enabled\n");
|
||||
pr_info("MSR-based RAPL PMU support enabled (updated)\n");
|
||||
}
|
||||
|
||||
rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
|
||||
@@ -258,8 +560,43 @@ static struct platform_driver intel_rapl_msr_driver = {
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(intel_rapl_msr_driver);
|
||||
static struct platform_device *rapl_msr_platdev;
|
||||
|
||||
static int intel_rapl_msr_init(void)
|
||||
{
|
||||
const struct rapl_defaults *def;
|
||||
const struct x86_cpu_id *id;
|
||||
int ret;
|
||||
|
||||
ret = platform_driver_register(&intel_rapl_msr_driver);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Create the MSR RAPL platform device for supported platforms */
|
||||
id = x86_match_cpu(rapl_ids);
|
||||
if (!id)
|
||||
return 0;
|
||||
|
||||
def = (const struct rapl_defaults *)id->driver_data;
|
||||
|
||||
rapl_msr_platdev = platform_device_register_data(NULL, "intel_rapl_msr", 0, def,
|
||||
sizeof(*def));
|
||||
if (IS_ERR(rapl_msr_platdev))
|
||||
pr_debug("intel_rapl_msr device register failed, ret:%ld\n",
|
||||
PTR_ERR(rapl_msr_platdev));
|
||||
|
||||
return 0;
|
||||
}
|
||||
module_init(intel_rapl_msr_init);
|
||||
|
||||
static void intel_rapl_msr_exit(void)
|
||||
{
|
||||
platform_device_unregister(rapl_msr_platdev);
|
||||
platform_driver_unregister(&intel_rapl_msr_driver);
|
||||
}
|
||||
module_exit(intel_rapl_msr_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit) control via MSR interface");
|
||||
MODULE_AUTHOR("Zhang Rui <rui.zhang@intel.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_IMPORT_NS("INTEL_RAPL");
|
||||
|
||||
@@ -9,12 +9,14 @@
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/auxiliary_bus.h>
|
||||
#include <linux/bits.h>
|
||||
#include <linux/intel_rapl.h>
|
||||
#include <linux/intel_tpmi.h>
|
||||
#include <linux/intel_vsec.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/units.h>
|
||||
|
||||
#define TPMI_RAPL_MAJOR_VERSION 0
|
||||
#define TPMI_RAPL_MINOR_VERSION 1
|
||||
@@ -60,6 +62,58 @@ static DEFINE_MUTEX(tpmi_rapl_lock);
|
||||
|
||||
static struct powercap_control_type *tpmi_control_type;
|
||||
|
||||
/* bitmasks for RAPL TPMI, used by primitive access functions */
|
||||
#define TPMI_POWER_LIMIT_MASK GENMASK_ULL(17, 0)
|
||||
#define TPMI_POWER_LIMIT_ENABLE BIT_ULL(62)
|
||||
#define TPMI_POWER_HIGH_LOCK BIT_ULL(63)
|
||||
#define TPMI_TIME_WINDOW_MASK GENMASK_ULL(24, 18)
|
||||
#define TPMI_INFO_SPEC_MASK GENMASK_ULL(17, 0)
|
||||
#define TPMI_INFO_MIN_MASK GENMASK_ULL(35, 18)
|
||||
#define TPMI_INFO_MAX_MASK GENMASK_ULL(53, 36)
|
||||
#define TPMI_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(60, 54)
|
||||
#define TPMI_ENERGY_STATUS_MASK GENMASK(31, 0)
|
||||
#define TPMI_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
|
||||
|
||||
/* RAPL primitives for TPMI I/F */
|
||||
static struct rapl_primitive_info rpi_tpmi[NR_RAPL_PRIMITIVES] = {
|
||||
/* name, mask, shift, msr index, unit divisor */
|
||||
[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, TPMI_POWER_LIMIT_MASK, 0,
|
||||
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
|
||||
[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, TPMI_POWER_LIMIT_MASK, 0,
|
||||
RAPL_DOMAIN_REG_PL2, POWER_UNIT, 0),
|
||||
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, TPMI_POWER_LIMIT_MASK, 0,
|
||||
RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
|
||||
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, TPMI_ENERGY_STATUS_MASK, 0,
|
||||
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
|
||||
[PL1_LOCK] = PRIMITIVE_INFO_INIT(PL1_LOCK, TPMI_POWER_HIGH_LOCK, 63,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[PL2_LOCK] = PRIMITIVE_INFO_INIT(PL2_LOCK, TPMI_POWER_HIGH_LOCK, 63,
|
||||
RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
|
||||
[PL4_LOCK] = PRIMITIVE_INFO_INIT(PL4_LOCK, TPMI_POWER_HIGH_LOCK, 63,
|
||||
RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
|
||||
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
|
||||
RAPL_DOMAIN_REG_PL2, ARBITRARY_UNIT, 0),
|
||||
[PL4_ENABLE] = PRIMITIVE_INFO_INIT(PL4_ENABLE, TPMI_POWER_LIMIT_ENABLE, 62,
|
||||
RAPL_DOMAIN_REG_PL4, ARBITRARY_UNIT, 0),
|
||||
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TPMI_TIME_WINDOW_MASK, 18,
|
||||
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
|
||||
[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TPMI_TIME_WINDOW_MASK, 18,
|
||||
RAPL_DOMAIN_REG_PL2, TIME_UNIT, 0),
|
||||
[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, TPMI_INFO_SPEC_MASK, 0,
|
||||
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
|
||||
[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, TPMI_INFO_MAX_MASK, 36,
|
||||
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
|
||||
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, TPMI_INFO_MIN_MASK, 18,
|
||||
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
|
||||
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, TPMI_INFO_MAX_TIME_WIN_MASK,
|
||||
54, RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
|
||||
[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
|
||||
TPMI_PERF_STATUS_THROTTLE_TIME_MASK,
|
||||
0, RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
|
||||
};
|
||||
|
||||
static int tpmi_rapl_read_raw(int id, struct reg_action *ra, bool atomic)
|
||||
{
|
||||
if (!ra->reg.mmio)
|
||||
@@ -250,6 +304,50 @@ static int parse_one_domain(struct tpmi_rapl_package *trp, u32 offset)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* TPMI Unit register has different layout */
|
||||
#define TPMI_ENERGY_UNIT_SCALE 1000
|
||||
#define TPMI_POWER_UNIT_OFFSET 0x00
|
||||
#define TPMI_POWER_UNIT_MASK GENMASK(3, 0)
|
||||
#define TPMI_ENERGY_UNIT_OFFSET 0x06
|
||||
#define TPMI_ENERGY_UNIT_MASK GENMASK_ULL(10, 6)
|
||||
#define TPMI_TIME_UNIT_OFFSET 0x0C
|
||||
#define TPMI_TIME_UNIT_MASK GENMASK_ULL(15, 12)
|
||||
|
||||
static int rapl_check_unit_tpmi(struct rapl_domain *rd)
|
||||
{
|
||||
struct reg_action ra;
|
||||
u32 value;
|
||||
|
||||
ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT];
|
||||
ra.mask = ~0;
|
||||
if (tpmi_rapl_read_raw(rd->rp->id, &ra, false)) {
|
||||
pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n",
|
||||
ra.reg.val, rd->rp->name, rd->name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
value = (ra.value & TPMI_ENERGY_UNIT_MASK) >> TPMI_ENERGY_UNIT_OFFSET;
|
||||
rd->energy_unit = (TPMI_ENERGY_UNIT_SCALE * MICROJOULE_PER_JOULE) >> value;
|
||||
|
||||
value = (ra.value & TPMI_POWER_UNIT_MASK) >> TPMI_POWER_UNIT_OFFSET;
|
||||
rd->power_unit = MICROWATT_PER_WATT >> value;
|
||||
|
||||
value = (ra.value & TPMI_TIME_UNIT_MASK) >> TPMI_TIME_UNIT_OFFSET;
|
||||
rd->time_unit = USEC_PER_SEC >> value;
|
||||
|
||||
pr_debug("Core CPU %s:%s energy=%dpJ, time=%dus, power=%duW\n",
|
||||
rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct rapl_defaults defaults_tpmi = {
|
||||
.check_unit = rapl_check_unit_tpmi,
|
||||
/* Reuse existing logic, ignore the PL_CLAMP failures and enable all Power Limits */
|
||||
.set_floor_freq = rapl_default_set_floor_freq,
|
||||
.compute_time_window = rapl_default_compute_time_window,
|
||||
};
|
||||
|
||||
static int intel_rapl_tpmi_probe(struct auxiliary_device *auxdev,
|
||||
const struct auxiliary_device_id *id)
|
||||
{
|
||||
@@ -297,6 +395,8 @@ static int intel_rapl_tpmi_probe(struct auxiliary_device *auxdev,
|
||||
trp->priv.read_raw = tpmi_rapl_read_raw;
|
||||
trp->priv.write_raw = tpmi_rapl_write_raw;
|
||||
trp->priv.control_type = tpmi_control_type;
|
||||
trp->priv.defaults = &defaults_tpmi;
|
||||
trp->priv.rpi = rpi_tpmi;
|
||||
|
||||
/* RAPL TPMI I/F is per physical package */
|
||||
trp->rp = rapl_find_package_domain(info->package_id, &trp->priv, false);
|
||||
@@ -348,6 +448,7 @@ static struct auxiliary_driver intel_rapl_tpmi_driver = {
|
||||
|
||||
module_auxiliary_driver(intel_rapl_tpmi_driver)
|
||||
|
||||
MODULE_IMPORT_NS("INTEL_RAPL");
|
||||
MODULE_IMPORT_NS("INTEL_TPMI");
|
||||
|
||||
MODULE_DESCRIPTION("Intel RAPL TPMI Driver");
|
||||
|
||||
@@ -11,6 +11,77 @@
|
||||
|
||||
static struct rapl_if_priv rapl_mmio_priv;
|
||||
|
||||
/* bitmasks for RAPL MSRs, used by primitive access functions */
|
||||
#define MMIO_ENERGY_STATUS_MASK GENMASK(31, 0)
|
||||
|
||||
#define MMIO_POWER_LIMIT1_MASK GENMASK(14, 0)
|
||||
#define MMIO_POWER_LIMIT1_ENABLE BIT(15)
|
||||
#define MMIO_POWER_LIMIT1_CLAMP BIT(16)
|
||||
|
||||
#define MMIO_POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
|
||||
#define MMIO_POWER_LIMIT2_ENABLE BIT_ULL(47)
|
||||
#define MMIO_POWER_LIMIT2_CLAMP BIT_ULL(48)
|
||||
|
||||
#define MMIO_POWER_LOW_LOCK BIT(31)
|
||||
#define MMIO_POWER_HIGH_LOCK BIT_ULL(63)
|
||||
|
||||
#define MMIO_POWER_LIMIT4_MASK GENMASK(12, 0)
|
||||
|
||||
#define MMIO_TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
|
||||
#define MMIO_TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
|
||||
|
||||
#define MMIO_POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
|
||||
#define MMIO_POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
|
||||
#define MMIO_POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
|
||||
#define MMIO_POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
|
||||
|
||||
#define MMIO_PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
|
||||
#define MMIO_PP_POLICY_MASK GENMASK(4, 0)
|
||||
|
||||
/* RAPL primitives for MMIO I/F */
|
||||
static struct rapl_primitive_info rpi_mmio[NR_RAPL_PRIMITIVES] = {
|
||||
/* name, mask, shift, msr index, unit divisor */
|
||||
[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, MMIO_POWER_LIMIT1_MASK, 0,
|
||||
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
|
||||
[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, MMIO_POWER_LIMIT2_MASK, 32,
|
||||
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
|
||||
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, MMIO_POWER_LIMIT4_MASK, 0,
|
||||
RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
|
||||
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, MMIO_ENERGY_STATUS_MASK, 0,
|
||||
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
|
||||
[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_LOW_LOCK, 31,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, MMIO_POWER_HIGH_LOCK, 63,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, MMIO_POWER_LIMIT1_ENABLE, 15,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, MMIO_POWER_LIMIT1_CLAMP, 16,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, MMIO_POWER_LIMIT2_ENABLE, 47,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, MMIO_POWER_LIMIT2_CLAMP, 48,
|
||||
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
|
||||
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, MMIO_TIME_WINDOW1_MASK, 17,
|
||||
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
|
||||
[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, MMIO_TIME_WINDOW2_MASK, 49,
|
||||
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
|
||||
[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
|
||||
MMIO_POWER_INFO_THERMAL_SPEC_MASK, 0,
|
||||
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
|
||||
[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, MMIO_POWER_INFO_MAX_MASK, 32,
|
||||
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
|
||||
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, MMIO_POWER_INFO_MIN_MASK, 16,
|
||||
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
|
||||
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
|
||||
MMIO_POWER_INFO_MAX_TIME_WIN_MASK, 48,
|
||||
RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
|
||||
[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
|
||||
MMIO_PERF_STATUS_THROTTLE_TIME_MASK, 0,
|
||||
RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
|
||||
[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, MMIO_PP_POLICY_MASK, 0,
|
||||
RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
|
||||
};
|
||||
|
||||
static const struct rapl_mmio_regs rapl_mmio_default = {
|
||||
.reg_unit = 0x5938,
|
||||
.regs[RAPL_DOMAIN_PACKAGE] = { 0x59a0, 0x593c, 0x58f0, 0, 0x5930, 0x59b0},
|
||||
@@ -19,6 +90,13 @@ static const struct rapl_mmio_regs rapl_mmio_default = {
|
||||
.limits[RAPL_DOMAIN_DRAM] = BIT(POWER_LIMIT2),
|
||||
};
|
||||
|
||||
static const struct rapl_defaults rapl_defaults_mmio = {
|
||||
.floor_freq_reg_addr = 0,
|
||||
.check_unit = rapl_default_check_unit,
|
||||
.set_floor_freq = rapl_default_set_floor_freq,
|
||||
.compute_time_window = rapl_default_compute_time_window,
|
||||
};
|
||||
|
||||
static int rapl_mmio_read_raw(int cpu, struct reg_action *ra, bool atomic)
|
||||
{
|
||||
if (!ra->reg.mmio)
|
||||
@@ -67,6 +145,8 @@ int proc_thermal_rapl_add(struct pci_dev *pdev, struct proc_thermal_device *proc
|
||||
|
||||
rapl_mmio_priv.read_raw = rapl_mmio_read_raw;
|
||||
rapl_mmio_priv.write_raw = rapl_mmio_write_raw;
|
||||
rapl_mmio_priv.defaults = &rapl_defaults_mmio;
|
||||
rapl_mmio_priv.rpi = rpi_mmio;
|
||||
|
||||
rapl_mmio_priv.control_type = powercap_register_control_type(NULL, "intel-rapl-mmio", NULL);
|
||||
if (IS_ERR(rapl_mmio_priv.control_type)) {
|
||||
@@ -111,4 +191,5 @@ void proc_thermal_rapl_remove(void)
|
||||
EXPORT_SYMBOL_GPL(proc_thermal_rapl_remove);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_IMPORT_NS("INTEL_RAPL");
|
||||
MODULE_DESCRIPTION("RAPL interface using MMIO");
|
||||
|
||||
@@ -77,7 +77,6 @@ enum rapl_primitives {
|
||||
PSYS_TIME_WINDOW1,
|
||||
PSYS_TIME_WINDOW2,
|
||||
/* below are not raw primitive data */
|
||||
AVERAGE_POWER,
|
||||
NR_RAPL_PRIMITIVES,
|
||||
};
|
||||
|
||||
@@ -128,6 +127,46 @@ struct reg_action {
|
||||
int err;
|
||||
};
|
||||
|
||||
struct rapl_defaults {
|
||||
u8 floor_freq_reg_addr;
|
||||
int (*check_unit)(struct rapl_domain *rd);
|
||||
void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
|
||||
u64 (*compute_time_window)(struct rapl_domain *rd, u64 val, bool to_raw);
|
||||
unsigned int dram_domain_energy_unit;
|
||||
unsigned int psys_domain_energy_unit;
|
||||
bool spr_psys_bits;
|
||||
bool msr_pl4_support;
|
||||
bool msr_pmu_support;
|
||||
};
|
||||
|
||||
#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
|
||||
.name = #p, \
|
||||
.mask = m, \
|
||||
.shift = s, \
|
||||
.id = i, \
|
||||
.unit = u, \
|
||||
.flag = f \
|
||||
}
|
||||
|
||||
enum unit_type {
|
||||
ARBITRARY_UNIT, /* no translation */
|
||||
POWER_UNIT,
|
||||
ENERGY_UNIT,
|
||||
TIME_UNIT,
|
||||
};
|
||||
|
||||
/* per domain data. used to describe individual knobs such that access function
|
||||
* can be consolidated into one instead of many inline functions.
|
||||
*/
|
||||
struct rapl_primitive_info {
|
||||
const char *name;
|
||||
u64 mask;
|
||||
int shift;
|
||||
enum rapl_domain_reg_id id;
|
||||
enum unit_type unit;
|
||||
u32 flag;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct rapl_if_priv: private data for different RAPL interfaces
|
||||
* @control_type: Each RAPL interface must have its own powercap
|
||||
@@ -142,8 +181,8 @@ struct reg_action {
|
||||
* registers.
|
||||
* @write_raw: Callback for writing RAPL interface specific
|
||||
* registers.
|
||||
* @defaults: internal pointer to interface default settings
|
||||
* @rpi: internal pointer to interface primitive info
|
||||
* @defaults: pointer to default settings
|
||||
* @rpi: pointer to interface primitive info
|
||||
*/
|
||||
struct rapl_if_priv {
|
||||
enum rapl_if_type type;
|
||||
@@ -154,8 +193,8 @@ struct rapl_if_priv {
|
||||
int limits[RAPL_DOMAIN_MAX];
|
||||
int (*read_raw)(int id, struct reg_action *ra, bool pmu_ctx);
|
||||
int (*write_raw)(int id, struct reg_action *ra);
|
||||
void *defaults;
|
||||
void *rpi;
|
||||
const struct rapl_defaults *defaults;
|
||||
struct rapl_primitive_info *rpi;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PERF_EVENTS
|
||||
@@ -211,6 +250,9 @@ void rapl_remove_package_cpuslocked(struct rapl_package *rp);
|
||||
struct rapl_package *rapl_find_package_domain(int id, struct rapl_if_priv *priv, bool id_is_cpu);
|
||||
struct rapl_package *rapl_add_package(int id, struct rapl_if_priv *priv, bool id_is_cpu);
|
||||
void rapl_remove_package(struct rapl_package *rp);
|
||||
int rapl_default_check_unit(struct rapl_domain *rd);
|
||||
void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode);
|
||||
u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_raw);
|
||||
|
||||
#ifdef CONFIG_PERF_EVENTS
|
||||
int rapl_package_add_pmu(struct rapl_package *rp);
|
||||
|
||||
@@ -238,7 +238,7 @@ static inline void *powercap_get_zone_data(struct powercap_zone *power_zone)
|
||||
* Advantage of this parameter is that client can embed
|
||||
* this data in its data structures and allocate in a
|
||||
* single call, preventing multiple allocations.
|
||||
* @control_type_name: The Name of this control_type, which will be shown
|
||||
* @name: The Name of this control_type, which will be shown
|
||||
* in the sysfs Interface.
|
||||
* @ops: Callbacks for control type. This parameter is optional.
|
||||
*
|
||||
@@ -277,7 +277,7 @@ int powercap_unregister_control_type(struct powercap_control_type *instance);
|
||||
* @name: A name for this zone.
|
||||
* @parent: A pointer to the parent power zone instance if any or NULL
|
||||
* @ops: Pointer to zone operation callback structure.
|
||||
* @no_constraints: Number of constraints for this zone
|
||||
* @nr_constraints: Number of constraints for this zone
|
||||
* @const_ops: Pointer to constraint callback structure
|
||||
*
|
||||
* Register a power zone under a given control type. A power zone must register
|
||||
|
||||
@@ -57,6 +57,9 @@
|
||||
#define MICROWATT_PER_MILLIWATT 1000UL
|
||||
#define MICROWATT_PER_WATT 1000000UL
|
||||
|
||||
#define MICROJOULE_PER_JOULE 1000000UL
|
||||
#define NANOJOULE_PER_JOULE 1000000000UL
|
||||
|
||||
#define BYTES_PER_KBIT (KILO / BITS_PER_BYTE)
|
||||
#define BYTES_PER_MBIT (MEGA / BITS_PER_BYTE)
|
||||
#define BYTES_PER_GBIT (GIGA / BITS_PER_BYTE)
|
||||
|
||||
Reference in New Issue
Block a user