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Merge tag 'imx-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/drivers
i.MX drivers update for 5.19: - A series from Lucas and Paul to update GPCv2 driver for i.MX8MP power domains, and add HSIO and HDMI block control support. * tag 'imx-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: fix semicolon.cocci warnings soc: imx: add i.MX8MP HDMI blk-ctrl soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl soc: imx: add i.MX8MP HSIO blk-ctrl dt-bindings: power: imx8mp: add defines for HDMI blk-ctrl domains dt-bindings: soc: Add i.MX8MP media block control DT bindings soc: imx: imx8m-blk-ctrl: set power device name soc: imx: gpcv2: add support for i.MX8MP power domains soc: imx: gpcv2: add PGC control register indirection Link: https://lore.kernel.org/r/20220508033843.2773685-2-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -0,0 +1,104 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8MP Media Block Control
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maintainers:
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- Paul Elder <paul.elder@ideasonboard.com>
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description:
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The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
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providing access to the NoC and ensuring proper power sequencing of the
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peripherals within the MEDIAMIX domain.
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properties:
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compatible:
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items:
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- const: fsl,imx8mp-media-blk-ctrl
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- const: syscon
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reg:
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maxItems: 1
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'#power-domain-cells':
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const: 1
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power-domains:
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maxItems: 10
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power-domain-names:
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items:
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- const: bus
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- const: mipi-dsi1
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- const: mipi-csi1
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- const: lcdif1
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- const: isi
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- const: mipi-csi2
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- const: lcdif2
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- const: isp
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- const: dwe
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- const: mipi-dsi2
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clocks:
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items:
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- description: The APB clock
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- description: The AXI clock
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- description: The pixel clock for the first CSI2 receiver (aclk)
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- description: The pixel clock for the second CSI2 receiver (aclk)
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- description: The pixel clock for the first LCDIF (pix_clk)
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- description: The pixel clock for the second LCDIF (pix_clk)
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- description: The core clock for the ISP (clk)
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- description: The MIPI-PHY reference clock used by DSI
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clock-names:
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items:
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- const: apb
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- const: axi
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- const: cam1
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- const: cam2
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- const: disp1
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- const: disp2
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- const: isp
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- const: phy
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required:
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- compatible
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- reg
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- '#power-domain-cells'
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- power-domains
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- power-domain-names
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/power/imx8mp-power.h>
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media_blk_ctl: blk-ctl@32ec0000 {
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compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
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reg = <0x32ec0000 0x138>;
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power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
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<&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
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<&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
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<&mipi_phy2_pd>;
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power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
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"mipi-csi2", "lcdif2", "isp1", "dwe", "mipi-dsi2";
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
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clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
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"isp", "phy";
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#power-domain-cells = <1>;
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};
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...
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@@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
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obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
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obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
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obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
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obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o
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+418
-12
File diff suppressed because it is too large
Load Diff
@@ -15,11 +15,12 @@
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#include <dt-bindings/power/imx8mm-power.h>
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#include <dt-bindings/power/imx8mn-power.h>
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#include <dt-bindings/power/imx8mp-power.h>
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#include <dt-bindings/power/imx8mq-power.h>
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#define BLK_SFT_RSTN 0x0
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#define BLK_CLK_EN 0x4
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#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */
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#define BLK_MIPI_RESET_DIV 0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
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struct imx8m_blk_ctrl_domain;
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@@ -41,7 +42,7 @@ struct imx8m_blk_ctrl_domain_data {
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u32 clk_mask;
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/*
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* i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register
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* i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
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* which is used to control the reset for the MIPI Phy.
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* Since it's only present in certain circumstances,
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* an if-statement should be used before setting and clearing this
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@@ -241,6 +242,7 @@ static int imx8m_blk_ctrl_probe(struct platform_device *pdev)
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ret = PTR_ERR(domain->power_dev);
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goto cleanup_pds;
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}
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dev_set_name(domain->power_dev, "%s", data->name);
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domain->genpd.name = data->name;
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domain->genpd.power_on = imx8m_blk_ctrl_power_on;
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@@ -590,6 +592,121 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
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.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
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};
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static int imx8mp_media_power_notifier(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
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power_nb);
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if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
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return NOTIFY_OK;
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/* Enable bus clock and deassert bus reset */
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regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
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regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
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/*
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* On power up we have no software backchannel to the GPC to
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* wait for the ADB handshake to happen, so we just delay for a
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* bit. On power down the GPC driver waits for the handshake.
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*/
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if (action == GENPD_NOTIFY_ON)
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udelay(5);
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return NOTIFY_OK;
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}
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/*
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* From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
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* section 13.2.2, 13.2.3
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* isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
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*/
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static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
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[IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
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.name = "mediablk-mipi-dsi-1",
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.clk_names = (const char *[]){ "apb", "phy", },
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.num_clks = 2,
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.gpc_name = "mipi-dsi1",
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.rst_mask = BIT(0) | BIT(1),
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.clk_mask = BIT(0) | BIT(1),
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.mipi_phy_rst_mask = BIT(17),
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},
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[IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
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.name = "mediablk-mipi-csi2-1",
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.clk_names = (const char *[]){ "apb", "cam1" },
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.num_clks = 2,
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.gpc_name = "mipi-csi1",
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.rst_mask = BIT(2) | BIT(3),
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.clk_mask = BIT(2) | BIT(3),
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.mipi_phy_rst_mask = BIT(16),
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},
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[IMX8MP_MEDIABLK_PD_LCDIF_1] = {
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.name = "mediablk-lcdif-1",
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.clk_names = (const char *[]){ "disp1", "apb", "axi", },
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.num_clks = 3,
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.gpc_name = "lcdif1",
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.rst_mask = BIT(4) | BIT(5) | BIT(23),
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.clk_mask = BIT(4) | BIT(5) | BIT(23),
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},
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[IMX8MP_MEDIABLK_PD_ISI] = {
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.name = "mediablk-isi",
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.clk_names = (const char *[]){ "axi", "apb" },
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.num_clks = 2,
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.gpc_name = "isi",
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.rst_mask = BIT(6) | BIT(7),
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.clk_mask = BIT(6) | BIT(7),
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},
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[IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
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.name = "mediablk-mipi-csi2-2",
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.clk_names = (const char *[]){ "apb", "cam2" },
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.num_clks = 2,
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.gpc_name = "mipi-csi2",
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.rst_mask = BIT(9) | BIT(10),
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.clk_mask = BIT(9) | BIT(10),
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.mipi_phy_rst_mask = BIT(30),
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},
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[IMX8MP_MEDIABLK_PD_LCDIF_2] = {
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.name = "mediablk-lcdif-2",
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.clk_names = (const char *[]){ "disp1", "apb", "axi", },
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.num_clks = 3,
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.gpc_name = "lcdif2",
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.rst_mask = BIT(11) | BIT(12) | BIT(24),
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.clk_mask = BIT(11) | BIT(12) | BIT(24),
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},
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[IMX8MP_MEDIABLK_PD_ISP] = {
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.name = "mediablk-isp",
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.clk_names = (const char *[]){ "isp", "axi", "apb" },
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.num_clks = 3,
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.gpc_name = "isp",
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.rst_mask = BIT(16) | BIT(17) | BIT(18),
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.clk_mask = BIT(16) | BIT(17) | BIT(18),
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},
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[IMX8MP_MEDIABLK_PD_DWE] = {
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.name = "mediablk-dwe",
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.clk_names = (const char *[]){ "axi", "apb" },
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.num_clks = 2,
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.gpc_name = "dwe",
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.rst_mask = BIT(19) | BIT(20) | BIT(21),
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.clk_mask = BIT(19) | BIT(20) | BIT(21),
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},
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[IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
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.name = "mediablk-mipi-dsi-2",
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.clk_names = (const char *[]){ "phy", },
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.num_clks = 1,
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.gpc_name = "mipi-dsi2",
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.rst_mask = BIT(22),
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.clk_mask = BIT(22),
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.mipi_phy_rst_mask = BIT(29),
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},
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};
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static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
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.max_reg = 0x138,
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.power_notifier_fn = imx8mp_media_power_notifier,
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.domains = imx8mp_media_blk_ctl_domain_data,
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.num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
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};
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static int imx8mq_vpu_power_notifier(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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@@ -662,6 +779,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
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}, {
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.compatible = "fsl,imx8mn-disp-blk-ctrl",
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.data = &imx8mn_disp_blk_ctl_dev_data
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}, {
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.compatible = "fsl,imx8mp-media-blk-ctrl",
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.data = &imx8mp_media_blk_ctl_dev_data
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}, {
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.compatible = "fsl,imx8mq-vpu-blk-ctrl",
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.data = &imx8mq_vpu_blk_ctl_dev_data
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File diff suppressed because it is too large
Load Diff
@@ -32,4 +32,22 @@
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#define IMX8MP_HSIOBLK_PD_PCIE 3
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#define IMX8MP_HSIOBLK_PD_PCIE_PHY 4
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#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1 0
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#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1 1
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#define IMX8MP_MEDIABLK_PD_LCDIF_1 2
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#define IMX8MP_MEDIABLK_PD_ISI 3
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#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
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#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
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#define IMX8MP_MEDIABLK_PD_ISP 6
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#define IMX8MP_MEDIABLK_PD_DWE 7
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#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
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#define IMX8MP_HDMIBLK_PD_IRQSTEER 0
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#define IMX8MP_HDMIBLK_PD_LCDIF 1
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#define IMX8MP_HDMIBLK_PD_PAI 2
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#define IMX8MP_HDMIBLK_PD_PVI 3
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#define IMX8MP_HDMIBLK_PD_TRNG 4
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#define IMX8MP_HDMIBLK_PD_HDMI_TX 5
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#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
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#endif
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