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Merge branch 'ib-mfd-regulator-watchdog-6.11' into ibs-for-mfd-merged

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This commit is contained in:
Lee Jones
2024-07-04 17:07:26 +01:00
parent 04f3893327 fcf1f960a6
commit 2a2ca717ce
14 changed files with 2094 additions and 0 deletions
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Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/rohm,bd96801-pmic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BD96801 Scalable Power Management Integrated Circuit
maintainers:
- Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
description:
BD96801 is an automotive grade single-chip power management IC.
It integrates 4 buck converters and 3 LDOs with safety features like
over-/under voltage and over current detection and a watchdog.
properties:
compatible:
const: rohm,bd96801
reg:
maxItems: 1
interrupts:
description:
The PMIC provides intb and errb IRQ lines. The errb IRQ line is used
for fatal IRQs which will cause the PMIC to shut down power outputs.
In many systems this will shut down the SoC contolling the PMIC and
connecting/handling the errb can be omitted. However, there are cases
where the SoC is not powered by the PMIC or has a short time backup
energy to handle shutdown of critical hardware. In that case it may be
useful to connect the errb and handle errb events.
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
items:
- enum: [intb, errb]
- const: errb
rohm,hw-timeout-ms:
description:
Watchdog timeout value(s). First walue is timeout limit. Second value is
optional value for 'too early' watchdog ping if window timeout mode is
to be used.
minItems: 1
maxItems: 2
rohm,wdg-action:
description:
Whether the watchdog failure must turn off the regulator power outputs or
just toggle the INTB line.
enum:
- prstb
- intb-only
timeout-sec:
maxItems: 2
regulators:
$ref: /schemas/regulator/rohm,bd96801-regulator.yaml
description:
List of child nodes that specify the regulators.
required:
- compatible
- reg
- interrupts
- interrupt-names
- regulators
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic: pmic@60 {
reg = <0x60>;
compatible = "rohm,bd96801";
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>, <6 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "intb", "errb";
regulators {
buck1 {
regulator-name = "buck1";
regulator-ramp-delay = <1250>;
/* 0.5V min INITIAL - 150 mV tune */
regulator-min-microvolt = <350000>;
/* 3.3V + 150mV tune */
regulator-max-microvolt = <3450000>;
/* These can be set only when PMIC is in STBY */
rohm,initial-voltage-microvolt = <500000>;
regulator-ov-error-microvolt = <230000>;
regulator-uv-error-microvolt = <230000>;
regulator-temp-protection-kelvin = <1>;
regulator-temp-warn-kelvin = <0>;
};
buck2 {
regulator-name = "buck2";
regulator-min-microvolt = <350000>;
regulator-max-microvolt = <3450000>;
rohm,initial-voltage-microvolt = <3000000>;
regulator-ov-error-microvolt = <18000>;
regulator-uv-error-microvolt = <18000>;
regulator-temp-protection-kelvin = <1>;
regulator-temp-warn-kelvin = <1>;
};
buck3 {
regulator-name = "buck3";
regulator-min-microvolt = <350000>;
regulator-max-microvolt = <3450000>;
rohm,initial-voltage-microvolt = <600000>;
regulator-ov-warn-microvolt = <18000>;
regulator-uv-warn-microvolt = <18000>;
regulator-temp-protection-kelvin = <1>;
regulator-temp-error-kelvin = <0>;
};
buck4 {
regulator-name = "buck4";
regulator-min-microvolt = <350000>;
regulator-max-microvolt = <3450000>;
rohm,initial-voltage-microvolt = <600000>;
regulator-ov-warn-microvolt = <18000>;
regulator-uv-warn-microvolt = <18000>;
regulator-temp-protection-kelvin = <1>;
regulator-temp-error-kelvin = <0>;
};
ldo5 {
regulator-name = "ldo5";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
rohm,initial-voltage-microvolt = <500000>;
regulator-ov-error-microvolt = <36000>;
regulator-uv-error-microvolt = <34000>;
regulator-temp-protection-kelvin = <1>;
regulator-temp-warn-kelvin = <0>;
};
ldo6 {
regulator-name = "ldo6";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
rohm,initial-voltage-microvolt = <300000>;
regulator-ov-error-microvolt = <36000>;
regulator-uv-error-microvolt = <34000>;
regulator-temp-protection-kelvin = <1>;
regulator-temp-warn-kelvin = <0>;
};
ldo7 {
regulator-name = "ldo7";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <3300000>;
rohm,initial-voltage-microvolt = <500000>;
regulator-ov-error-microvolt = <36000>;
regulator-uv-error-microvolt = <34000>;
regulator-temp-protection-kelvin = <1>;
regulator-temp-warn-kelvin = <0>;
};
};
};
};
Documentation/devicetree/bindings/regulator/rohm,bd96801-regulator.yaml
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/rohm,bd96801-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BD96801 Power Management Integrated Circuit regulators
maintainers:
- Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
description:
This module is part of the ROHM BD96801 MFD device. For more details
see Documentation/devicetree/bindings/mfd/rohm,bd96801-pmic.yaml.
The regulator controller is represented as a sub-node of the PMIC node
on the device tree.
Regulator nodes should be named to buck_<number> and ldo_<number>.
The valid names for BD96801 regulator nodes are
buck1, buck2, buck3, buck4, ldo5, ldo6, ldo7
patternProperties:
"^ldo[5-7]$":
type: object
description:
Properties for single LDO regulator.
$ref: regulator.yaml#
properties:
rohm,initial-voltage-microvolt:
description:
Initial voltage for regulator. Voltage can be tuned +/-150 mV from
this value. NOTE, This can be modified via I2C only when PMIC is in
STBY state.
minimum: 300000
maximum: 3300000
unevaluatedProperties: false
"^buck[1-4]$":
type: object
description:
Properties for single BUCK regulator.
$ref: regulator.yaml#
properties:
rohm,initial-voltage-microvolt:
description:
Initial voltage for regulator. Voltage can be tuned +/-150 mV from
this value. NOTE, This can be modified via I2C only when PMIC is in
STBY state.
minimum: 500000
maximum: 3300000
rohm,keep-on-stby:
description:
Keep the regulator powered when PMIC transitions to STBY state.
type: boolean
unevaluatedProperties: false
additionalProperties: false
MAINTAINERS
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@@ -19472,17 +19472,21 @@ F: drivers/gpio/gpio-bd71828.c
F: drivers/mfd/rohm-bd71828.c
F: drivers/mfd/rohm-bd718x7.c
F: drivers/mfd/rohm-bd9576.c
F: drivers/mfd/rohm-bd96801.c
F: drivers/regulator/bd71815-regulator.c
F: drivers/regulator/bd71828-regulator.c
F: drivers/regulator/bd718x7-regulator.c
F: drivers/regulator/bd9576-regulator.c
F: drivers/regulator/bd96801-regulator.c
F: drivers/regulator/rohm-regulator.c
F: drivers/rtc/rtc-bd70528.c
F: drivers/watchdog/bd9576_wdt.c
F: drivers/watchdog/bd96801_wdt.c
F: include/linux/mfd/rohm-bd71815.h
F: include/linux/mfd/rohm-bd71828.h
F: include/linux/mfd/rohm-bd718x7.h
F: include/linux/mfd/rohm-bd957x.h
F: include/linux/mfd/rohm-bd96801.h
F: include/linux/mfd/rohm-generic.h
F: include/linux/mfd/rohm-shared.h
drivers/mfd/Kconfig
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@@ -2101,6 +2101,19 @@ config MFD_ROHM_BD957XMUF
BD9573MUF Power Management ICs. BD9576 and BD9573 are primarily
designed to be used to power R-Car series processors.
config MFD_ROHM_BD96801
tristate "ROHM BD96801 Power Management IC"
depends on I2C=y
depends on OF
select REGMAP_I2C
select REGMAP_IRQ
select MFD_CORE
help
Select this option to get support for the ROHM BD96801 Power
Management IC. The ROHM BD96801 is a highly scalable Power Management
IC for industrial and automotive use. The BD96801 can be used as a
master PMIC in a chained PMIC solution with suitable companion PMICs.
config MFD_STM32_LPTIMER
tristate "Support for STM32 Low-Power Timer"
depends on (ARCH_STM32 && OF) || COMPILE_TEST
drivers/mfd/Makefile
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@@ -269,6 +269,7 @@ obj-$(CONFIG_RAVE_SP_CORE) += rave-sp.o
obj-$(CONFIG_MFD_ROHM_BD71828) += rohm-bd71828.o
obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o
obj-$(CONFIG_MFD_ROHM_BD957XMUF) += rohm-bd9576.o
obj-$(CONFIG_MFD_ROHM_BD96801) += rohm-bd96801.o
obj-$(CONFIG_MFD_STMFX) += stmfx.o
obj-$(CONFIG_MFD_KHADAS_MCU) += khadas-mcu.o
obj-$(CONFIG_MFD_ACER_A500_EC) += acer-ec-a500.o
drivers/mfd/rohm-bd96801.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2024 ROHM Semiconductors
*
* ROHM BD96801 PMIC driver
*
* This version of the "BD86801 scalable PMIC"'s driver supports only very
* basic set of the PMIC features. Most notably, there is no support for
* the ERRB interrupt and the configurations which should be done when the
* PMIC is in STBY mode.
*
* Supporting the ERRB interrupt would require dropping the regmap-IRQ
* usage or working around (or accepting a presense of) a naming conflict
* in debugFS IRQs.
*
* Being able to reliably do the configurations like changing the
* regulator safety limits (like limits for the over/under -voltages, over
* current, thermal protection) would require the configuring driver to be
* synchronized with entity causing the PMIC state transitions. Eg, one
* should be able to ensure the PMIC is in STBY state when the
* configurations are applied to the hardware. How and when the PMIC state
* transitions are to be done is likely to be very system specific, as will
* be the need to configure these safety limits. Hence it's not simple to
* come up with a generic solution.
*
* Users who require the ERRB handling and STBY state configurations can
* have a look at the original RFC:
* https://lore.kernel.org/all/cover.1712920132.git.mazziesaccount@gmail.com/
* which implements a workaround to debugFS naming conflict and some of
* the safety limit configurations - but leaves the state change handling
* and synchronization to be implemented.
*
* It would be great to hear (and receive a patch!) if you implement the
* STBY configuration support or a proper fix to the debugFS naming
* conflict in your downstream driver ;)
*/
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/types.h>
#include <linux/mfd/rohm-bd96801.h>
#include <linux/mfd/rohm-generic.h>
static const struct resource regulator_intb_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "bd96801-buck1-overcurr-h"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "bd96801-buck1-overcurr-l"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "bd96801-buck1-overcurr-n"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "bd96801-buck1-overvolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "bd96801-buck1-undervolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "bd96801-buck1-thermal"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "bd96801-buck2-overcurr-h"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "bd96801-buck2-overcurr-l"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "bd96801-buck2-overcurr-n"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "bd96801-buck2-overvolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "bd96801-buck2-undervolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "bd96801-buck2-thermal"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "bd96801-buck3-overcurr-h"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "bd96801-buck3-overcurr-l"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "bd96801-buck3-overcurr-n"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "bd96801-buck3-overvolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "bd96801-buck3-undervolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "bd96801-buck3-thermal"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "bd96801-buck4-overcurr-h"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "bd96801-buck4-overcurr-l"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "bd96801-buck4-overcurr-n"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "bd96801-buck4-overvolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "bd96801-buck4-undervolt"),
DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "bd96801-buck4-thermal"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "bd96801-ldo5-overcurr"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "bd96801-ldo5-overvolt"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "bd96801-ldo5-undervolt"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "bd96801-ldo6-overcurr"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "bd96801-ldo6-overvolt"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "bd96801-ldo6-undervolt"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "bd96801-ldo7-overcurr"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "bd96801-ldo7-overvolt"),
DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"),
};
static const struct resource wdg_intb_irqs[] = {
DEFINE_RES_IRQ_NAMED(BD96801_WDT_ERR_STAT, "bd96801-wdg"),
};
static struct mfd_cell bd96801_cells[] = {
{
.name = "bd96801-wdt",
.resources = wdg_intb_irqs,
.num_resources = ARRAY_SIZE(wdg_intb_irqs),
}, {
.name = "bd96801-regulator",
.resources = regulator_intb_irqs,
.num_resources = ARRAY_SIZE(regulator_intb_irqs),
},
};
static const struct regmap_range bd96801_volatile_ranges[] = {
/* Status registers */
regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT),
regmap_reg_range(BD96801_REG_WD_ASK, BD96801_REG_WD_ASK),
regmap_reg_range(BD96801_REG_WD_STATUS, BD96801_REG_WD_STATUS),
regmap_reg_range(BD96801_REG_PMIC_STATE, BD96801_REG_INT_LDO7_INTB),
/* Registers which do not update value unless PMIC is in STBY */
regmap_reg_range(BD96801_REG_SSCG_CTRL, BD96801_REG_SHD_INTB),
regmap_reg_range(BD96801_REG_BUCK_OVP, BD96801_REG_BOOT_OVERTIME),
/*
* LDO control registers have single bit (LDO MODE) which does not
* change when we write it unless PMIC is in STBY. It's safer to not
* cache it.
*/
regmap_reg_range(BD96801_LDO5_VOL_LVL_REG, BD96801_LDO7_VOL_LVL_REG),
};
static const struct regmap_access_table volatile_regs = {
.yes_ranges = bd96801_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges),
};
static const struct regmap_irq bd96801_intb_irqs[] = {
/* STATUS SYSTEM INTB */
REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK),
REGMAP_IRQ_REG(BD96801_WDT_ERR_STAT, 0, BD96801_WDT_ERR_STAT_MASK),
REGMAP_IRQ_REG(BD96801_I2C_ERR_STAT, 0, BD96801_I2C_ERR_STAT_MASK),
REGMAP_IRQ_REG(BD96801_CHIP_IF_ERR_STAT, 0, BD96801_CHIP_IF_ERR_STAT_MASK),
/* STATUS BUCK1 INTB */
REGMAP_IRQ_REG(BD96801_BUCK1_OCPH_STAT, 1, BD96801_BUCK_OCPH_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_OCPL_STAT, 1, BD96801_BUCK_OCPL_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_OCPN_STAT, 1, BD96801_BUCK_OCPN_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_OVD_STAT, 1, BD96801_BUCK_OVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_UVD_STAT, 1, BD96801_BUCK_UVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK1_TW_CH_STAT, 1, BD96801_BUCK_TW_CH_STAT_MASK),
/* BUCK 2 INTB */
REGMAP_IRQ_REG(BD96801_BUCK2_OCPH_STAT, 2, BD96801_BUCK_OCPH_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_OCPL_STAT, 2, BD96801_BUCK_OCPL_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_OCPN_STAT, 2, BD96801_BUCK_OCPN_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_OVD_STAT, 2, BD96801_BUCK_OVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_UVD_STAT, 2, BD96801_BUCK_UVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK2_TW_CH_STAT, 2, BD96801_BUCK_TW_CH_STAT_MASK),
/* BUCK 3 INTB */
REGMAP_IRQ_REG(BD96801_BUCK3_OCPH_STAT, 3, BD96801_BUCK_OCPH_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_OCPL_STAT, 3, BD96801_BUCK_OCPL_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_OCPN_STAT, 3, BD96801_BUCK_OCPN_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_OVD_STAT, 3, BD96801_BUCK_OVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_UVD_STAT, 3, BD96801_BUCK_UVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK3_TW_CH_STAT, 3, BD96801_BUCK_TW_CH_STAT_MASK),
/* BUCK 4 INTB */
REGMAP_IRQ_REG(BD96801_BUCK4_OCPH_STAT, 4, BD96801_BUCK_OCPH_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_OCPL_STAT, 4, BD96801_BUCK_OCPL_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_OCPN_STAT, 4, BD96801_BUCK_OCPN_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_OVD_STAT, 4, BD96801_BUCK_OVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_UVD_STAT, 4, BD96801_BUCK_UVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_BUCK4_TW_CH_STAT, 4, BD96801_BUCK_TW_CH_STAT_MASK),
/* LDO5 INTB */
REGMAP_IRQ_REG(BD96801_LDO5_OCPH_STAT, 5, BD96801_LDO_OCPH_STAT_MASK),
REGMAP_IRQ_REG(BD96801_LDO5_OVD_STAT, 5, BD96801_LDO_OVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_LDO5_UVD_STAT, 5, BD96801_LDO_UVD_STAT_MASK),
/* LDO6 INTB */
REGMAP_IRQ_REG(BD96801_LDO6_OCPH_STAT, 6, BD96801_LDO_OCPH_STAT_MASK),
REGMAP_IRQ_REG(BD96801_LDO6_OVD_STAT, 6, BD96801_LDO_OVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_LDO6_UVD_STAT, 6, BD96801_LDO_UVD_STAT_MASK),
/* LDO7 INTB */
REGMAP_IRQ_REG(BD96801_LDO7_OCPH_STAT, 7, BD96801_LDO_OCPH_STAT_MASK),
REGMAP_IRQ_REG(BD96801_LDO7_OVD_STAT, 7, BD96801_LDO_OVD_STAT_MASK),
REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK),
};
static struct regmap_irq_chip bd96801_irq_chip_intb = {
.name = "bd96801-irq-intb",
.main_status = BD96801_REG_INT_MAIN,
.num_main_regs = 1,
.irqs = &bd96801_intb_irqs[0],
.num_irqs = ARRAY_SIZE(bd96801_intb_irqs),
.status_base = BD96801_REG_INT_SYS_INTB,
.mask_base = BD96801_REG_MASK_SYS_INTB,
.ack_base = BD96801_REG_INT_SYS_INTB,
.init_ack_masked = true,
.num_regs = 8,
.irq_reg_stride = 1,
};
static const struct regmap_config bd96801_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
.volatile_table = &volatile_regs,
.cache_type = REGCACHE_RBTREE,
};
static int bd96801_i2c_probe(struct i2c_client *i2c)
{
struct regmap_irq_chip_data *intb_irq_data;
const struct fwnode_handle *fwnode;
struct irq_domain *intb_domain;
struct regmap *regmap;
int ret, intb_irq;
fwnode = dev_fwnode(&i2c->dev);
if (!fwnode)
return dev_err_probe(&i2c->dev, -EINVAL, "Failed to find fwnode\n");
intb_irq = fwnode_irq_get_byname(fwnode, "intb");
if (intb_irq < 0)
return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n");
regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config);
if (IS_ERR(regmap))
return dev_err_probe(&i2c->dev, PTR_ERR(regmap),
"Regmap initialization failed\n");
ret = regmap_write(regmap, BD96801_LOCK_REG, BD96801_UNLOCK);
if (ret)
return dev_err_probe(&i2c->dev, ret, "Failed to unlock PMIC\n");
ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, intb_irq,
IRQF_ONESHOT, 0, &bd96801_irq_chip_intb,
&intb_irq_data);
if (ret)
return dev_err_probe(&i2c->dev, ret, "Failed to add INTB IRQ chip\n");
intb_domain = regmap_irq_get_domain(intb_irq_data);
ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
bd96801_cells,
ARRAY_SIZE(bd96801_cells), NULL, 0,
intb_domain);
if (ret)
dev_err(&i2c->dev, "Failed to create subdevices\n");
return ret;
}
static const struct of_device_id bd96801_of_match[] = {
{ .compatible = "rohm,bd96801", },
{ }
};
MODULE_DEVICE_TABLE(of, bd96801_of_match);
static struct i2c_driver bd96801_i2c_driver = {
.driver = {
.name = "rohm-bd96801",
.of_match_table = bd96801_of_match,
},
.probe = bd96801_i2c_probe,
};
static int __init bd96801_i2c_init(void)
{
return i2c_add_driver(&bd96801_i2c_driver);
}
/* Initialise early so consumer devices can complete system boot */
subsys_initcall(bd96801_i2c_init);
static void __exit bd96801_i2c_exit(void)
{
i2c_del_driver(&bd96801_i2c_driver);
}
module_exit(bd96801_i2c_exit);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("ROHM BD96801 Power Management IC driver");
MODULE_LICENSE("GPL");
drivers/regulator/Kconfig
+12
View File
@@ -274,6 +274,18 @@ config REGULATOR_BD957XMUF
This driver can also be built as a module. If so, the module
will be called bd9576-regulator.
config REGULATOR_BD96801
tristate "ROHM BD96801 Power Regulator"
depends on MFD_ROHM_BD96801
select REGULATOR_ROHM
help
This driver supports voltage regulators on ROHM BD96801 PMIC.
This will enable support for the software controllable buck
and LDO regulators.
This driver can also be built as a module. If so, the module
will be called bd96801-regulator.
config REGULATOR_CPCAP
tristate "Motorola CPCAP regulator"
depends on MFD_CPCAP
drivers/regulator/Makefile
+1
View File
@@ -38,6 +38,7 @@ obj-$(CONFIG_REGULATOR_BD718XX) += bd718x7-regulator.o
obj-$(CONFIG_REGULATOR_BD9571MWV) += bd9571mwv-regulator.o
obj-$(CONFIG_REGULATOR_BD957XMUF) += bd9576-regulator.o
obj-$(CONFIG_REGULATOR_DA903X) += da903x-regulator.o
obj-$(CONFIG_REGULATOR_BD96801) += bd96801-regulator.o
obj-$(CONFIG_REGULATOR_DA9052) += da9052-regulator.o
obj-$(CONFIG_REGULATOR_DA9055) += da9055-regulator.o
obj-$(CONFIG_REGULATOR_DA9062) += da9062-regulator.o
drivers/regulator/bd96801-regulator.c
+908
View File
File diff suppressed because it is too large Load Diff
drivers/watchdog/Kconfig
+13
View File
@@ -181,6 +181,19 @@ config BD957XMUF_WATCHDOG
watchdog. Alternatively say M to compile the driver as a module,
which will be called bd9576_wdt.
config BD96801_WATCHDOG
tristate "ROHM BD96801 PMIC Watchdog"
depends on MFD_ROHM_BD96801
select WATCHDOG_CORE
help
Support for the watchdog in the ROHM BD96801 PMIC. Watchdog can be
configured to only generate IRQ or to trigger system reset via reset
pin.
Say Y here to include support for the ROHM BD96801 watchdog.
Alternatively say M to compile the driver as a module,
which will be called bd96801_wdt.
config CROS_EC_WATCHDOG
tristate "ChromeOS EC-based watchdog"
select WATCHDOG_CORE
drivers/watchdog/Makefile
+1
View File
@@ -218,6 +218,7 @@ obj-$(CONFIG_XEN_WDT) += xen_wdt.o
# Architecture Independent
obj-$(CONFIG_BD957XMUF_WATCHDOG) += bd9576_wdt.o
obj-$(CONFIG_BD96801_WATCHDOG) += bd96801_wdt.o
obj-$(CONFIG_CROS_EC_WATCHDOG) += cros_ec_wdt.o
obj-$(CONFIG_DA9052_WATCHDOG) += da9052_wdt.o
obj-$(CONFIG_DA9055_WATCHDOG) += da9055_wdt.o
drivers/watchdog/bd96801_wdt.c
+416
View File
@@ -0,0 +1,416 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2024 ROHM Semiconductors
*
* ROHM BD96801 watchdog driver
*/
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mfd/rohm-bd96801.h>
#include <linux/mfd/rohm-generic.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/watchdog.h>
static bool nowayout;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Watchdog cannot be stopped once started (default=\"false\")");
#define BD96801_WD_TMO_SHORT_MASK 0x70
#define BD96801_WD_RATIO_MASK 0x3
#define BD96801_WD_TYPE_MASK 0x4
#define BD96801_WD_TYPE_SLOW 0x4
#define BD96801_WD_TYPE_WIN 0x0
#define BD96801_WD_EN_MASK 0x3
#define BD96801_WD_IF_EN 0x1
#define BD96801_WD_QA_EN 0x2
#define BD96801_WD_DISABLE 0x0
#define BD96801_WD_ASSERT_MASK 0x8
#define BD96801_WD_ASSERT_RST 0x8
#define BD96801_WD_ASSERT_IRQ 0x0
#define BD96801_WD_FEED_MASK 0x1
#define BD96801_WD_FEED 0x1
/* 1.1 mS */
#define FASTNG_MIN 11
#define FASTNG_MAX_US (100 * FASTNG_MIN << 7)
#define SLOWNG_MAX_US (16 * FASTNG_MAX_US)
#define BD96801_WDT_DEFAULT_MARGIN_MS 1843
/* Unit is seconds */
#define DEFAULT_TIMEOUT 30
/*
* BD96801 WDG supports window mode so the TMO consists of SHORT and LONG
* timeout values. SHORT time is meaningful only in window mode where feeding
* period shorter than SHORT would be an error. LONG time is used to detect if
* feeding is not occurring within given time limit (SoC SW hangs). The LONG
* timeout time is a multiple of (2, 4, 8 or 16 times) the SHORT timeout.
*/
struct wdtbd96801 {
struct device *dev;
struct regmap *regmap;
struct watchdog_device wdt;
};
static int bd96801_wdt_ping(struct watchdog_device *wdt)
{
struct wdtbd96801 *w = watchdog_get_drvdata(wdt);
return regmap_update_bits(w->regmap, BD96801_REG_WD_FEED,
BD96801_WD_FEED_MASK, BD96801_WD_FEED);
}
static int bd96801_wdt_start(struct watchdog_device *wdt)
{
struct wdtbd96801 *w = watchdog_get_drvdata(wdt);
return regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
BD96801_WD_EN_MASK, BD96801_WD_IF_EN);
}
static int bd96801_wdt_stop(struct watchdog_device *wdt)
{
struct wdtbd96801 *w = watchdog_get_drvdata(wdt);
return regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
BD96801_WD_EN_MASK, BD96801_WD_DISABLE);
}
static const struct watchdog_info bd96801_wdt_info = {
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING |
WDIOF_SETTIMEOUT,
.identity = "BD96801 Watchdog",
};
static const struct watchdog_ops bd96801_wdt_ops = {
.start = bd96801_wdt_start,
.stop = bd96801_wdt_stop,
.ping = bd96801_wdt_ping,
};
static int find_closest_fast(unsigned int target, int *sel, unsigned int *val)
{
unsigned int window = FASTNG_MIN;
int i;
for (i = 0; i < 8 && window < target; i++)
window <<= 1;
if (i == 8)
return -EINVAL;
*val = window;
*sel = i;
return 0;
}
static int find_closest_slow_by_fast(unsigned int fast_val, unsigned int *target,
int *slowsel)
{
static const int multipliers[] = {2, 4, 8, 16};
int sel;
for (sel = 0; sel < ARRAY_SIZE(multipliers) &&
multipliers[sel] * fast_val < *target; sel++)
;
if (sel == ARRAY_SIZE(multipliers))
return -EINVAL;
*slowsel = sel;
*target = multipliers[sel] * fast_val;
return 0;
}
static int find_closest_slow(unsigned int *target, int *slow_sel, int *fast_sel)
{
static const int multipliers[] = {2, 4, 8, 16};
unsigned int window = FASTNG_MIN;
unsigned int val = 0;
int i, j;
for (i = 0; i < 8; i++) {
for (j = 0; j < ARRAY_SIZE(multipliers); j++) {
unsigned int slow;
slow = window * multipliers[j];
if (slow >= *target && (!val || slow < val)) {
val = slow;
*fast_sel = i;
*slow_sel = j;
}
}
window <<= 1;
}
if (!val)
return -EINVAL;
*target = val;
return 0;
}
static int bd96801_set_wdt_mode(struct wdtbd96801 *w, unsigned int hw_margin,
unsigned int hw_margin_min)
{
int fastng, slowng, type, ret, reg, mask;
struct device *dev = w->dev;
if (hw_margin_min * 1000 > FASTNG_MAX_US) {
dev_err(dev, "Unsupported fast timeout %u uS [max %u]\n",
hw_margin_min * 1000, FASTNG_MAX_US);
return -EINVAL;
}
if (hw_margin * 1000 > SLOWNG_MAX_US) {
dev_err(dev, "Unsupported slow timeout %u uS [max %u]\n",
hw_margin * 1000, SLOWNG_MAX_US);
return -EINVAL;
}
/*
* Convert to 100uS to guarantee reasonable timeouts fit in
* 32bit maintaining also a decent accuracy.
*/
hw_margin *= 10;
hw_margin_min *= 10;
if (hw_margin_min) {
unsigned int min;
type = BD96801_WD_TYPE_WIN;
dev_dbg(dev, "Setting type WINDOW 0x%x\n", type);
ret = find_closest_fast(hw_margin_min, &fastng, &min);
if (ret)
return ret;
ret = find_closest_slow_by_fast(min, &hw_margin, &slowng);
if (ret) {
dev_err(dev,
"can't support slow timeout %u uS using fast %u uS. [max slow %u uS]\n",
hw_margin * 100, min * 100, min * 100 * 16);
return ret;
}
w->wdt.min_hw_heartbeat_ms = min / 10;
} else {
type = BD96801_WD_TYPE_SLOW;
dev_dbg(dev, "Setting type SLOW 0x%x\n", type);
ret = find_closest_slow(&hw_margin, &slowng, &fastng);
if (ret)
return ret;
}
w->wdt.max_hw_heartbeat_ms = hw_margin / 10;
fastng = FIELD_PREP(BD96801_WD_TMO_SHORT_MASK, fastng);
reg = slowng | fastng;
mask = BD96801_WD_RATIO_MASK | BD96801_WD_TMO_SHORT_MASK;
ret = regmap_update_bits(w->regmap, BD96801_REG_WD_TMO,
mask, reg);
if (ret)
return ret;
ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
BD96801_WD_TYPE_MASK, type);
return ret;
}
static int bd96801_set_heartbeat_from_hw(struct wdtbd96801 *w,
unsigned int conf_reg)
{
int ret;
unsigned int val, sel, fast;
/*
* The BD96801 supports a somewhat peculiar QA-mode, which we do not
* support in this driver. If the QA-mode is enabled then we just
* warn and bail-out.
*/
if ((conf_reg & BD96801_WD_EN_MASK) != BD96801_WD_IF_EN) {
dev_err(w->dev, "watchdog set to Q&A mode - exiting\n");
return -EINVAL;
}
ret = regmap_read(w->regmap, BD96801_REG_WD_TMO, &val);
if (ret)
return ret;
sel = FIELD_GET(BD96801_WD_TMO_SHORT_MASK, val);
fast = FASTNG_MIN << sel;
sel = (val & BD96801_WD_RATIO_MASK) + 1;
w->wdt.max_hw_heartbeat_ms = (fast << sel) / USEC_PER_MSEC;
if ((conf_reg & BD96801_WD_TYPE_MASK) == BD96801_WD_TYPE_WIN)
w->wdt.min_hw_heartbeat_ms = fast / USEC_PER_MSEC;
return 0;
}
static int init_wdg_hw(struct wdtbd96801 *w)
{
u32 hw_margin[2];
int count, ret;
u32 hw_margin_max = BD96801_WDT_DEFAULT_MARGIN_MS, hw_margin_min = 0;
count = device_property_count_u32(w->dev->parent, "rohm,hw-timeout-ms");
if (count < 0 && count != -EINVAL)
return count;
if (count > 0) {
if (count > ARRAY_SIZE(hw_margin))
return -EINVAL;
ret = device_property_read_u32_array(w->dev->parent,
"rohm,hw-timeout-ms",
&hw_margin[0], count);
if (ret < 0)
return ret;
if (count == 1)
hw_margin_max = hw_margin[0];
if (count == 2) {
if (hw_margin[1] > hw_margin[0]) {
hw_margin_max = hw_margin[1];
hw_margin_min = hw_margin[0];
} else {
hw_margin_max = hw_margin[0];
hw_margin_min = hw_margin[1];
}
}
}
ret = bd96801_set_wdt_mode(w, hw_margin_max, hw_margin_min);
if (ret)
return ret;
ret = device_property_match_string(w->dev->parent, "rohm,wdg-action",
"prstb");
if (ret >= 0) {
ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
BD96801_WD_ASSERT_MASK,
BD96801_WD_ASSERT_RST);
return ret;
}
ret = device_property_match_string(w->dev->parent, "rohm,wdg-action",
"intb-only");
if (ret >= 0) {
ret = regmap_update_bits(w->regmap, BD96801_REG_WD_CONF,
BD96801_WD_ASSERT_MASK,
BD96801_WD_ASSERT_IRQ);
return ret;
}
return 0;
}
static irqreturn_t bd96801_irq_hnd(int irq, void *data)
{
emergency_restart();
return IRQ_NONE;
}
static int bd96801_wdt_probe(struct platform_device *pdev)
{
struct wdtbd96801 *w;
int ret, irq;
unsigned int val;
w = devm_kzalloc(&pdev->dev, sizeof(*w), GFP_KERNEL);
if (!w)
return -ENOMEM;
w->regmap = dev_get_regmap(pdev->dev.parent, NULL);
w->dev = &pdev->dev;
w->wdt.info = &bd96801_wdt_info;
w->wdt.ops = &bd96801_wdt_ops;
w->wdt.parent = pdev->dev.parent;
w->wdt.timeout = DEFAULT_TIMEOUT;
watchdog_set_drvdata(&w->wdt, w);
ret = regmap_read(w->regmap, BD96801_REG_WD_CONF, &val);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Failed to get the watchdog state\n");
/*
* If the WDG is already enabled we assume it is configured by boot.
* In this case we just update the hw-timeout based on values set to
* the timeout / mode registers and leave the hardware configs
* untouched.
*/
if ((val & BD96801_WD_EN_MASK) != BD96801_WD_DISABLE) {
dev_dbg(&pdev->dev, "watchdog was running during probe\n");
ret = bd96801_set_heartbeat_from_hw(w, val);
if (ret)
return ret;
set_bit(WDOG_HW_RUNNING, &w->wdt.status);
} else {
/* If WDG is not running so we will initializate it */
ret = init_wdg_hw(w);
if (ret)
return ret;
}
dev_dbg(w->dev, "heartbeat set to %u - %u\n",
w->wdt.min_hw_heartbeat_ms, w->wdt.max_hw_heartbeat_ms);
watchdog_init_timeout(&w->wdt, 0, pdev->dev.parent);
watchdog_set_nowayout(&w->wdt, nowayout);
watchdog_stop_on_reboot(&w->wdt);
irq = platform_get_irq_byname(pdev, "bd96801-wdg");
if (irq > 0) {
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
bd96801_irq_hnd,
IRQF_ONESHOT, "bd96801-wdg",
NULL);
if (ret)
return dev_err_probe(&pdev->dev, ret,
"Failed to register IRQ\n");
}
return devm_watchdog_register_device(&pdev->dev, &w->wdt);
}
static const struct platform_device_id bd96801_wdt_id[] = {
{ "bd96801-wdt", },
{ }
};
MODULE_DEVICE_TABLE(platform, bd96801_wdt_id);
static struct platform_driver bd96801_wdt = {
.driver = {
.name = "bd96801-wdt"
},
.probe = bd96801_wdt_probe,
.id_table = bd96801_wdt_id,
};
module_platform_driver(bd96801_wdt);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("BD96801 watchdog driver");
MODULE_LICENSE("GPL");
include/linux/mfd/rohm-bd96801.h
+215
View File
@@ -0,0 +1,215 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/* Copyright (C) 2024 ROHM Semiconductors */
#ifndef __MFD_BD96801_H__
#define __MFD_BD96801_H__
#define BD96801_REG_SSCG_CTRL 0x09
#define BD96801_REG_SHD_INTB 0x20
#define BD96801_LDO5_VOL_LVL_REG 0x2c
#define BD96801_LDO6_VOL_LVL_REG 0x2d
#define BD96801_LDO7_VOL_LVL_REG 0x2e
#define BD96801_REG_BUCK_OVP 0x30
#define BD96801_REG_BUCK_OVD 0x35
#define BD96801_REG_LDO_OVP 0x31
#define BD96801_REG_LDO_OVD 0x36
#define BD96801_REG_BOOT_OVERTIME 0x3a
#define BD96801_REG_WD_TMO 0x40
#define BD96801_REG_WD_CONF 0x41
#define BD96801_REG_WD_FEED 0x42
#define BD96801_REG_WD_FAILCOUNT 0x43
#define BD96801_REG_WD_ASK 0x46
#define BD96801_REG_WD_STATUS 0x4a
#define BD96801_REG_PMIC_STATE 0x4f
#define BD96801_REG_EXT_STATE 0x50
#define BD96801_STATE_STBY 0x09
#define BD96801_LOCK_REG 0x04
#define BD96801_UNLOCK 0x9d
#define BD96801_LOCK 0x00
/* IRQ register area */
#define BD96801_REG_INT_MAIN 0x51
/*
* The BD96801 has two physical IRQ lines, INTB and ERRB.
*
* The 'main status register' is located at 0x51.
* The ERRB status registers are located at 0x52 ... 0x5B
* INTB status registers are at range 0x5c ... 0x63
*/
#define BD96801_REG_INT_SYS_ERRB1 0x52
#define BD96801_REG_INT_SYS_INTB 0x5c
#define BD96801_REG_INT_LDO7_INTB 0x63
/* MASK registers */
#define BD96801_REG_MASK_SYS_INTB 0x73
#define BD96801_REG_MASK_SYS_ERRB 0x69
#define BD96801_MAX_REGISTER 0x7a
#define BD96801_OTP_ERR_MASK BIT(0)
#define BD96801_DBIST_ERR_MASK BIT(1)
#define BD96801_EEP_ERR_MASK BIT(2)
#define BD96801_ABIST_ERR_MASK BIT(3)
#define BD96801_PRSTB_ERR_MASK BIT(4)
#define BD96801_DRMOS1_ERR_MASK BIT(5)
#define BD96801_DRMOS2_ERR_MASK BIT(6)
#define BD96801_SLAVE_ERR_MASK BIT(7)
#define BD96801_VREF_ERR_MASK BIT(0)
#define BD96801_TSD_ERR_MASK BIT(1)
#define BD96801_UVLO_ERR_MASK BIT(2)
#define BD96801_OVLO_ERR_MASK BIT(3)
#define BD96801_OSC_ERR_MASK BIT(4)
#define BD96801_PON_ERR_MASK BIT(5)
#define BD96801_POFF_ERR_MASK BIT(6)
#define BD96801_CMD_SHDN_ERR_MASK BIT(7)
#define BD96801_INT_PRSTB_WDT_ERR_MASK BIT(0)
#define BD96801_INT_CHIP_IF_ERR_MASK BIT(3)
#define BD96801_INT_SHDN_ERR_MASK BIT(7)
#define BD96801_OUT_PVIN_ERR_MASK BIT(0)
#define BD96801_OUT_OVP_ERR_MASK BIT(1)
#define BD96801_OUT_UVP_ERR_MASK BIT(2)
#define BD96801_OUT_SHDN_ERR_MASK BIT(7)
/* ERRB IRQs */
enum {
/* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
BD96801_OTP_ERR_STAT,
BD96801_DBIST_ERR_STAT,
BD96801_EEP_ERR_STAT,
BD96801_ABIST_ERR_STAT,
BD96801_PRSTB_ERR_STAT,
BD96801_DRMOS1_ERR_STAT,
BD96801_DRMOS2_ERR_STAT,
BD96801_SLAVE_ERR_STAT,
BD96801_VREF_ERR_STAT,
BD96801_TSD_ERR_STAT,
BD96801_UVLO_ERR_STAT,
BD96801_OVLO_ERR_STAT,
BD96801_OSC_ERR_STAT,
BD96801_PON_ERR_STAT,
BD96801_POFF_ERR_STAT,
BD96801_CMD_SHDN_ERR_STAT,
BD96801_INT_PRSTB_WDT_ERR,
BD96801_INT_CHIP_IF_ERR,
BD96801_INT_SHDN_ERR_STAT,
/* Reg 0x55 BUCK1 ERR IRQs */
BD96801_BUCK1_PVIN_ERR_STAT,
BD96801_BUCK1_OVP_ERR_STAT,
BD96801_BUCK1_UVP_ERR_STAT,
BD96801_BUCK1_SHDN_ERR_STAT,
/* Reg 0x56 BUCK2 ERR IRQs */
BD96801_BUCK2_PVIN_ERR_STAT,
BD96801_BUCK2_OVP_ERR_STAT,
BD96801_BUCK2_UVP_ERR_STAT,
BD96801_BUCK2_SHDN_ERR_STAT,
/* Reg 0x57 BUCK3 ERR IRQs */
BD96801_BUCK3_PVIN_ERR_STAT,
BD96801_BUCK3_OVP_ERR_STAT,
BD96801_BUCK3_UVP_ERR_STAT,
BD96801_BUCK3_SHDN_ERR_STAT,
/* Reg 0x58 BUCK4 ERR IRQs */
BD96801_BUCK4_PVIN_ERR_STAT,
BD96801_BUCK4_OVP_ERR_STAT,
BD96801_BUCK4_UVP_ERR_STAT,
BD96801_BUCK4_SHDN_ERR_STAT,
/* Reg 0x59 LDO5 ERR IRQs */
BD96801_LDO5_PVIN_ERR_STAT,
BD96801_LDO5_OVP_ERR_STAT,
BD96801_LDO5_UVP_ERR_STAT,
BD96801_LDO5_SHDN_ERR_STAT,
/* Reg 0x5a LDO6 ERR IRQs */
BD96801_LDO6_PVIN_ERR_STAT,
BD96801_LDO6_OVP_ERR_STAT,
BD96801_LDO6_UVP_ERR_STAT,
BD96801_LDO6_SHDN_ERR_STAT,
/* Reg 0x5b LDO7 ERR IRQs */
BD96801_LDO7_PVIN_ERR_STAT,
BD96801_LDO7_OVP_ERR_STAT,
BD96801_LDO7_UVP_ERR_STAT,
BD96801_LDO7_SHDN_ERR_STAT,
};
/* INTB IRQs */
enum {
/* Reg 0x5c (System INTB) */
BD96801_TW_STAT,
BD96801_WDT_ERR_STAT,
BD96801_I2C_ERR_STAT,
BD96801_CHIP_IF_ERR_STAT,
/* Reg 0x5d (BUCK1 INTB) */
BD96801_BUCK1_OCPH_STAT,
BD96801_BUCK1_OCPL_STAT,
BD96801_BUCK1_OCPN_STAT,
BD96801_BUCK1_OVD_STAT,
BD96801_BUCK1_UVD_STAT,
BD96801_BUCK1_TW_CH_STAT,
/* Reg 0x5e (BUCK2 INTB) */
BD96801_BUCK2_OCPH_STAT,
BD96801_BUCK2_OCPL_STAT,
BD96801_BUCK2_OCPN_STAT,
BD96801_BUCK2_OVD_STAT,
BD96801_BUCK2_UVD_STAT,
BD96801_BUCK2_TW_CH_STAT,
/* Reg 0x5f (BUCK3 INTB)*/
BD96801_BUCK3_OCPH_STAT,
BD96801_BUCK3_OCPL_STAT,
BD96801_BUCK3_OCPN_STAT,
BD96801_BUCK3_OVD_STAT,
BD96801_BUCK3_UVD_STAT,
BD96801_BUCK3_TW_CH_STAT,
/* Reg 0x60 (BUCK4 INTB)*/
BD96801_BUCK4_OCPH_STAT,
BD96801_BUCK4_OCPL_STAT,
BD96801_BUCK4_OCPN_STAT,
BD96801_BUCK4_OVD_STAT,
BD96801_BUCK4_UVD_STAT,
BD96801_BUCK4_TW_CH_STAT,
/* Reg 0x61 (LDO5 INTB) */
BD96801_LDO5_OCPH_STAT, /* bit [0] */
BD96801_LDO5_OVD_STAT, /* bit [3] */
BD96801_LDO5_UVD_STAT, /* bit [4] */
/* Reg 0x62 (LDO6 INTB) */
BD96801_LDO6_OCPH_STAT, /* bit [0] */
BD96801_LDO6_OVD_STAT, /* bit [3] */
BD96801_LDO6_UVD_STAT, /* bit [4] */
/* Reg 0x63 (LDO7 INTB) */
BD96801_LDO7_OCPH_STAT, /* bit [0] */
BD96801_LDO7_OVD_STAT, /* bit [3] */
BD96801_LDO7_UVD_STAT, /* bit [4] */
};
/* IRQ MASKs */
#define BD96801_TW_STAT_MASK BIT(0)
#define BD96801_WDT_ERR_STAT_MASK BIT(1)
#define BD96801_I2C_ERR_STAT_MASK BIT(2)
#define BD96801_CHIP_IF_ERR_STAT_MASK BIT(3)
#define BD96801_BUCK_OCPH_STAT_MASK BIT(0)
#define BD96801_BUCK_OCPL_STAT_MASK BIT(1)
#define BD96801_BUCK_OCPN_STAT_MASK BIT(2)
#define BD96801_BUCK_OVD_STAT_MASK BIT(3)
#define BD96801_BUCK_UVD_STAT_MASK BIT(4)
#define BD96801_BUCK_TW_CH_STAT_MASK BIT(5)
#define BD96801_LDO_OCPH_STAT_MASK BIT(0)
#define BD96801_LDO_OVD_STAT_MASK BIT(3)
#define BD96801_LDO_UVD_STAT_MASK BIT(4)
#endif
include/linux/mfd/rohm-generic.h
+1
View File
@@ -16,6 +16,7 @@ enum rohm_chip_type {
ROHM_CHIP_TYPE_BD71828,
ROHM_CHIP_TYPE_BD71837,
ROHM_CHIP_TYPE_BD71847,
ROHM_CHIP_TYPE_BD96801,
ROHM_CHIP_TYPE_AMOUNT
};