mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"This is all driver updates, the majority of which is a bunch of new
Qualcomm clk drivers that dominate the diffstat because we add support
for six SoCs from that particular vendor.
The other big change is the removal of various clk drivers that are no
longer used now that the kernel is dropping support for those SoCs.
Beyond that there's the usual non-critical fixes for existing drivers
and a good number of patches from Lee Jones that cleanup a bunch of
W=1 enabled builds.
Removed Drivers:
- Remove efm32 clk driver
- Remove tango4 clk driver
- Remove zte zx clk driver
- Remove sirf prima2/atlast clk drivers
- Remove u300 clk driver
New Drivers:
- PLL support on MStar/SigmaStar ARMv7 SoCs
- CPU clks for Qualcomm SDX55
- GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
- GCC clks for Qualcomm SM8350
- GPU clks for Qualcomm SDM660/SDM630
Updates:
- Video clk fixups on Qualcomm SM8250
- Improvements for multimedia clks on Qualcomm MSM8998
- Fix many warnings with W=1 enabled builds under drivers/clk/
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid
glitches at boot
- Convert Xilinx VCU clk driver to a proper clk provider driver
- Expose Xilinx ZynqMP clk driver to more platforms
- Amlogic pll driver fixup
- Amlogic meson8b clock controller dt support clean up
- Remove mipi clk from the Amlogic axg clock controller
- New Rockchip rk3368 clock ids related to camera input
- Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk
reparenting
- A series from Liu Ying that adds some SCU clocks support for
i.MX8qxp DC0/MIPI-LVDS subsystems
- A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ,
and clkout1/2 support for i.MX8MM/MN
- Add I2c and Ethernet (RAVB) clocks on Renesas R-Car V3U
- Add timer (TMU) clocks on most Renesas R-Car Gen3 SoCs
- Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial
(HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA
(SYS-DMAC) clocks on Renesas R-Car V3U
- Add support for the USB 2.0 clock selector on Renesas RZ/G2 SoCs
- Allwinner H616 SoC clk support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (171 commits)
clk: mstar: msc313-mpll: Fix format specifier
clk: mstar: Allow MStar clk drivers to be compile tested
clk: qoriq: use macros to generate pll_mask
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
dt-bindings: clock: Add RPMHCC bindings for SC7280
clk: qcom: gcc-sm8350: add gdsc
dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
clk: qcom: gdsc: Implement NO_RET_PERIPH flag
clk: mstar: MStar/SigmaStar MPLL driver
...
This commit is contained in:
Linus Torvalds
@@ -20,6 +20,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- adi,axi-clkgen-2.00.a
|
||||
- adi,zynqmp-axi-clkgen-2.00.a
|
||||
|
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clocks:
|
||||
description:
|
||||
|
||||
@@ -41,6 +41,8 @@ properties:
|
||||
- allwinner,sun50i-h5-ccu
|
||||
- allwinner,sun50i-h6-ccu
|
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- allwinner,sun50i-h6-r-ccu
|
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- allwinner,sun50i-h616-ccu
|
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- allwinner,sun50i-h616-r-ccu
|
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- allwinner,suniv-f1c100s-ccu
|
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- nextthing,gr8-ccu
|
||||
|
||||
@@ -82,6 +84,7 @@ if:
|
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- allwinner,sun50i-a64-r-ccu
|
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- allwinner,sun50i-a100-r-ccu
|
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- allwinner,sun50i-h6-r-ccu
|
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- allwinner,sun50i-h616-r-ccu
|
||||
|
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then:
|
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properties:
|
||||
@@ -100,6 +103,7 @@ else:
|
||||
enum:
|
||||
- allwinner,sun50i-a100-ccu
|
||||
- allwinner,sun50i-h6-ccu
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||||
- allwinner,sun50i-h616-ccu
|
||||
|
||||
then:
|
||||
properties:
|
||||
|
||||
@@ -1,55 +0,0 @@
|
||||
* Clock and reset bindings for CSR atlas7
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "sirf,atlas7-car"
|
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- reg: Address and length of the register set
|
||||
- #clock-cells: Should be <1>
|
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- #reset-cells: Should be <1>
|
||||
|
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The clock consumer should specify the desired clock by having the clock
|
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ID in its "clocks" phandle cell.
|
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The ID list atlas7_clks defined in drivers/clk/sirf/clk-atlas7.c
|
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|
||||
The reset consumer should specify the desired reset by having the reset
|
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ID in its "reset" phandle cell.
|
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The ID list atlas7_reset_unit defined in drivers/clk/sirf/clk-atlas7.c
|
||||
|
||||
Examples: Clock and reset controller node:
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car: clock-controller@18620000 {
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compatible = "sirf,atlas7-car";
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reg = <0x18620000 0x1000>;
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#clock-cells = <1>;
|
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#reset-cells = <1>;
|
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};
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||||
|
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Examples: Consumers using clock or reset:
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timer@10dc0000 {
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compatible = "sirf,macro-tick";
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reg = <0x10dc0000 0x1000>;
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clocks = <&car 54>;
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interrupts = <0 0 0>,
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<0 1 0>,
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<0 2 0>,
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<0 49 0>,
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<0 50 0>,
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<0 51 0>;
|
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};
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uart1: uart@18020000 {
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cell-index = <1>;
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compatible = "sirf,macro-uart";
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reg = <0x18020000 0x1000>;
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clocks = <&clks 95>;
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interrupts = <0 18 0>;
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fifosize = <32>;
|
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};
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vpp@13110000 {
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compatible = "sirf,prima2-vpp";
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reg = <0x13110000 0x10000>;
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interrupts = <0 31 0>;
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clocks = <&car 85>;
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resets = <&car 29>;
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};
|
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@@ -59,6 +59,12 @@ properties:
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minItems: 1
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maxItems: 2
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idt,xtal-load-femtofarads:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 9000
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maximum: 22760
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description: Optional load capacitor for XTAL1 and XTAL2
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|
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patternProperties:
|
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"^OUT[1-4]$":
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type: object
|
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|
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
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title: Clock bindings for Freescale i.MX27
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|
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maintainers:
|
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- Fabio Estevam <fabio.estevam@nxp.com>
|
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- Fabio Estevam <festevam@gmail.com>
|
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|
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description: |
|
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The clock consumer should specify the desired clock by having the clock
|
||||
|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
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title: Clock bindings for Freescale i.MX31
|
||||
|
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maintainers:
|
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- Fabio Estevam <fabio.estevam@nxp.com>
|
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- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
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|
||||
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
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title: Clock bindings for Freescale i.MX5
|
||||
|
||||
maintainers:
|
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- Fabio Estevam <fabio.estevam@nxp.com>
|
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- Fabio Estevam <festevam@gmail.com>
|
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|
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description: |
|
||||
The clock consumer should specify the desired clock by having the clock
|
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|
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@@ -0,0 +1,46 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
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%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: Intel SoCFPGA eASIC N5X platform clock controller binding
|
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|
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maintainers:
|
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- Dinh Nguyen <dinguyen@kernel.org>
|
||||
|
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description:
|
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The Intel eASIC N5X Clock controller is an integrated clock controller, which
|
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generates and supplies to all modules.
|
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|
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properties:
|
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compatible:
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const: intel,easic-n5x-clkmgr
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|
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'#clock-cells':
|
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const: 1
|
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|
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reg:
|
||||
maxItems: 1
|
||||
|
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clocks:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
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- reg
|
||||
- clocks
|
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- '#clock-cells'
|
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|
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additionalProperties: false
|
||||
|
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examples:
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# Clock controller node:
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- |
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clkmgr: clock-controller@ffd10000 {
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compatible = "intel,easic-n5x-clkmgr";
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reg = <0xffd10000 0x1000>;
|
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clocks = <&osc1>;
|
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#clock-cells = <1>;
|
||||
};
|
||||
...
|
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@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MStar/Sigmastar MSC313 MPLL
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
||||
description: |
|
||||
The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
|
||||
takes the external xtal input and multiplies it to create a high
|
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frequency clock and divides that down into a number of clocks that
|
||||
peripherals use.
|
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|
||||
properties:
|
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compatible:
|
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const: mstar,msc313-mpll
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|
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"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- reg
|
||||
|
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additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mpll@206000 {
|
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compatible = "mstar,msc313-mpll";
|
||||
reg = <0x206000 0x200>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
};
|
||||
@@ -1,73 +0,0 @@
|
||||
* Clock bindings for CSR SiRFprimaII
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "sirf,prima2-clkc"
|
||||
- reg: Address and length of the register set
|
||||
- interrupts: Should contain clock controller interrupt
|
||||
- #clock-cells: Should be <1>
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. The following is a full list of prima2
|
||||
clocks and IDs.
|
||||
|
||||
Clock ID
|
||||
---------------------------
|
||||
rtc 0
|
||||
osc 1
|
||||
pll1 2
|
||||
pll2 3
|
||||
pll3 4
|
||||
mem 5
|
||||
sys 6
|
||||
security 7
|
||||
dsp 8
|
||||
gps 9
|
||||
mf 10
|
||||
io 11
|
||||
cpu 12
|
||||
uart0 13
|
||||
uart1 14
|
||||
uart2 15
|
||||
tsc 16
|
||||
i2c0 17
|
||||
i2c1 18
|
||||
spi0 19
|
||||
spi1 20
|
||||
pwmc 21
|
||||
efuse 22
|
||||
pulse 23
|
||||
dmac0 24
|
||||
dmac1 25
|
||||
nand 26
|
||||
audio 27
|
||||
usp0 28
|
||||
usp1 29
|
||||
usp2 30
|
||||
vip 31
|
||||
gfx 32
|
||||
mm 33
|
||||
lcd 34
|
||||
vpp 35
|
||||
mmc01 36
|
||||
mmc23 37
|
||||
mmc45 38
|
||||
usbpll 39
|
||||
usb0 40
|
||||
usb1 41
|
||||
|
||||
Examples:
|
||||
|
||||
clks: clock-controller@88000000 {
|
||||
compatible = "sirf,prima2-clkc";
|
||||
reg = <0x88000000 0x1000>;
|
||||
interrupts = <3>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@b00e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00e0000 0x10000>;
|
||||
interrupts = <24>;
|
||||
clocks = <&clks 17>;
|
||||
};
|
||||
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm A7 PLL Binding
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description:
|
||||
The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
|
||||
frequency clock to the CPU.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sdx55-a7pll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: board XO clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
a7pll: clock@17808000 {
|
||||
compatible = "qcom,sdx55-a7pll";
|
||||
reg = <0x17808000 0x1000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "bi_tcxo";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
@@ -0,0 +1,92 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc7280.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc7280
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE-0 pipe clock source
|
||||
- description: PCIE-1 pipe clock source
|
||||
- description: USF phy rx symbol 0 clock source
|
||||
- description: USF phy rx symbol 1 clock source
|
||||
- description: USF phy tx symbol 0 clock source
|
||||
- description: USB30 phy wrapper pipe clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
- const: pcie_0_pipe_clk
|
||||
- const: pcie_1_pipe_clk
|
||||
- const: ufs_phy_rx_symbol_0_clk
|
||||
- const: ufs_phy_rx_symbol_1_clk
|
||||
- const: ufs_phy_tx_symbol_0_clk
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc7280";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>,
|
||||
<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
|
||||
<&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
|
||||
<&ufs_phy_tx_symbol_0_clk>,
|
||||
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
|
||||
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk",
|
||||
"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
|
||||
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
|
||||
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC8180x
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC8180x.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc8180x.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sc8180x
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Board active XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: bi_tcxo_ao
|
||||
- const: sleep_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sc8180x";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK_A>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,96 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8350
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8350.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-sm8350
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PLL test clock source (Optional clock)
|
||||
- description: PCIE 0 Pipe clock source (Optional clock)
|
||||
- description: PCIE 1 Pipe clock source (Optional clock)
|
||||
- description: UFS card Rx symbol 0 clock source (Optional clock)
|
||||
- description: UFS card Rx symbol 1 clock source (Optional clock)
|
||||
- description: UFS card Tx symbol 0 clock source (Optional clock)
|
||||
- description: UFS phy Rx symbol 0 clock source (Optional clock)
|
||||
- description: UFS phy Rx symbol 1 clock source (Optional clock)
|
||||
- description: UFS phy Tx symbol 0 clock source (Optional clock)
|
||||
- description: USB3 phy wrapper pipe clock source (Optional clock)
|
||||
- description: USB3 phy sec pipe clock source (Optional clock)
|
||||
minItems: 2
|
||||
maxItems: 13
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: bi_tcxo
|
||||
- const: sleep_clk
|
||||
- const: core_bi_pll_test_se # Optional clock
|
||||
- const: pcie_0_pipe_clk # Optional clock
|
||||
- const: pcie_1_pipe_clk # Optional clock
|
||||
- const: ufs_card_rx_symbol_0_clk # Optional clock
|
||||
- const: ufs_card_rx_symbol_1_clk # Optional clock
|
||||
- const: ufs_card_tx_symbol_0_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_0_clk # Optional clock
|
||||
- const: ufs_phy_rx_symbol_1_clk # Optional clock
|
||||
- const: ufs_phy_tx_symbol_0_clk # Optional clock
|
||||
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
|
||||
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
|
||||
minItems: 2
|
||||
maxItems: 13
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sm8350";
|
||||
reg = <0x00100000 0x1f0000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>;
|
||||
clock-names = "bi_tcxo", "sleep_clk";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -0,0 +1,76 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on SDM630 and SDM660.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sdm660.h.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gpucc-sdm630
|
||||
- qcom,gpucc-sdm660
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 main gpu branch
|
||||
- description: GPLL0 divider gpu branch
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: gcc_gpu_gpll0_clk
|
||||
- const: gcc_gpu_gpll0_div_clk
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sdm660.h>
|
||||
#include <dt-bindings/clock/qcom,rpmcc.h>
|
||||
|
||||
clock-controller@5065000 {
|
||||
compatible = "qcom,gpucc-sdm660";
|
||||
reg = <0x05065000 0x9038>;
|
||||
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_GPU_GPLL0_CLK>,
|
||||
<&gcc GCC_GPU_GPLL0_DIV_CLK>;
|
||||
clock-names = "xo", "gcc_gpu_gpll0_clk",
|
||||
"gcc_gpu_gpll0_div_clk";
|
||||
#clock-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
...
|
||||
@@ -24,6 +24,8 @@ properties:
|
||||
- qcom,mmcc-msm8974
|
||||
- qcom,mmcc-msm8996
|
||||
- qcom,mmcc-msm8998
|
||||
- qcom,mmcc-sdm630
|
||||
- qcom,mmcc-sdm660
|
||||
|
||||
clocks:
|
||||
items:
|
||||
|
||||
@@ -18,6 +18,8 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
- qcom,sdm845-rpmh-clk
|
||||
- qcom,sdx55-rpmh-clk
|
||||
- qcom,sm8150-rpmh-clk
|
||||
|
||||
@@ -35,6 +35,9 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a774a1-rcar-usb2-clock-sel # RZ/G2M
|
||||
- renesas,r8a774b1-rcar-usb2-clock-sel # RZ/G2N
|
||||
- renesas,r8a774e1-rcar-usb2-clock-sel # RZ/G2H
|
||||
- renesas,r8a7795-rcar-usb2-clock-sel # R-Car H3
|
||||
- renesas,r8a7796-rcar-usb2-clock-sel # R-Car M3-W
|
||||
- renesas,r8a77961-rcar-usb2-clock-sel # R-Car M3-W+
|
||||
|
||||
@@ -28,6 +28,8 @@ Optional properties:
|
||||
- clock-frequency: Output frequency to generate. This defines the output
|
||||
frequency set during boot. It can be reprogrammed during
|
||||
runtime through the common clock framework.
|
||||
- silabs,skip-recall: Do not perform NVM->RAM recall operation. It will rely
|
||||
on hardware loading of RAM from NVM at power on.
|
||||
|
||||
Example:
|
||||
si570: clock-generator@5d {
|
||||
|
||||
@@ -1,80 +0,0 @@
|
||||
Clock bindings for ST-Ericsson U300 System Controller Clocks
|
||||
|
||||
Bindings for the gated system controller clocks:
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "stericsson,u300-syscon-clk"
|
||||
- #clock-cells: must be <0>
|
||||
- clock-type: specifies the type of clock:
|
||||
0 = slow clock
|
||||
1 = fast clock
|
||||
2 = rest/remaining clock
|
||||
- clock-id: specifies the clock in the type range
|
||||
|
||||
Optional properties:
|
||||
- clocks: parent clock(s)
|
||||
|
||||
The available clocks per type are as follows:
|
||||
|
||||
Type: ID: Clock:
|
||||
-------------------
|
||||
0 0 Slow peripheral bridge clock
|
||||
0 1 UART0 clock
|
||||
0 4 GPIO clock
|
||||
0 6 RTC clock
|
||||
0 7 Application timer clock
|
||||
0 8 Access timer clock
|
||||
|
||||
1 0 Fast peripheral bridge clock
|
||||
1 1 I2C bus 0 clock
|
||||
1 2 I2C bus 1 clock
|
||||
1 5 MMC interface peripheral (silicon) clock
|
||||
1 6 SPI clock
|
||||
|
||||
2 3 CPU clock
|
||||
2 4 DMA controller clock
|
||||
2 5 External Memory Interface (EMIF) clock
|
||||
2 6 NAND flask interface clock
|
||||
2 8 XGAM graphics engine clock
|
||||
2 9 Shared External Memory Interface (SEMI) clock
|
||||
2 10 AHB Subsystem Bridge clock
|
||||
2 12 Interrupt controller clock
|
||||
|
||||
Example:
|
||||
|
||||
gpio_clk: gpio_clk@13M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "stericsson,u300-syscon-clk";
|
||||
clock-type = <0>; /* Slow */
|
||||
clock-id = <4>;
|
||||
clocks = <&slow_clk>;
|
||||
};
|
||||
|
||||
gpio: gpio@c0016000 {
|
||||
compatible = "stericsson,gpio-coh901";
|
||||
(...)
|
||||
clocks = <&gpio_clk>;
|
||||
};
|
||||
|
||||
|
||||
Bindings for the MMC/SD card clock:
|
||||
|
||||
Required properties:
|
||||
- compatible: must be "stericsson,u300-syscon-mclk"
|
||||
- #clock-cells: must be <0>
|
||||
|
||||
Optional properties:
|
||||
- clocks: parent clock(s)
|
||||
|
||||
mmc_mclk: mmc_mclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "stericsson,u300-syscon-mclk";
|
||||
clocks = <&mmc_pclk>;
|
||||
};
|
||||
|
||||
mmcsd: mmcsd@c0001000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
clocks = <&mmc_pclk>, <&mmc_mclk>;
|
||||
clock-names = "apb_pclk", "mclk";
|
||||
(...)
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user