mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'phy-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next
Vinod writes: phy for 5.9 - New PHY Drivers: - Samsung UFS - Qcom USB DWC for ipq806x - Xilinx ZynqMP Gigabit Transceiver - Qcom USB QMP for IPQ8074 - BCM63xx USBH - Removed: - Qcom ufs qmp phy driver - Updates: - Support for Qcom SM8250 QMP V4 USB3 UNIPHY - qcom-snps runtime pm support - Cleanup of W=1 warns in the subsystem * tag 'phy-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (46 commits) phy: qualcomm: fix setting of tx_deamp_3_5db when device property read fails phy: bcm63xx-usbh: Add BCM63xx USBH driver dt-bindings: phy: add bcm63xx-usbh bindings phy: armada-38x: fix NETA lockup when repeatedly switching speeds dt: update Marvell Armada 38x COMPHY binding phy: samsung-ufs: Fix IS_ERR argument dt-bindings: phy: renesas,usb3-phy: Add r8a774e1 support dt-bindings: phy: renesas,usb2-phy: Add r8a774e1 support phy: renesas: rcar-gen3-usb2: exit if request_irq() failed phy: renesas: rcar-gen3-usb2: move irq registration to init devicetree: bindings: phy: Document ipq806x dwc3 qcom phy phy: qualcomm: add qcom ipq806x dwc usb phy driver phy: samsung-ufs: add UFS PHY driver for samsung SoC dt-bindings: phy: Document Samsung UFS PHY bindings phy: sun4i-usb: explicitly include gpio/consumer.h phy: stm32: use NULL instead of zero phy: exynos5-usbdrd: use correct format for structure description phy: rockchip-typec: use correct format for structure description phy: xgene: remove unsigned integer comparison with less than zero phy: mapphone-mdm6600: Add missing description for some structure fields ...
This commit is contained in:
Greg Kroah-Hartman
@@ -0,0 +1,79 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
|
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---
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||||
$id: "http://devicetree.org/schemas/phy/brcm,bcm63xx-usbh-phy.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: BCM63xx USBH PHY
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||||
|
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maintainers:
|
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- Álvaro Fernández Rojas <noltari@gmail.com>
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|
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properties:
|
||||
compatible:
|
||||
enum:
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- brcm,bcm6318-usbh-phy
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- brcm,bcm6328-usbh-phy
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- brcm,bcm6358-usbh-phy
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- brcm,bcm6362-usbh-phy
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- brcm,bcm6368-usbh-phy
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- brcm,bcm63268-usbh-phy
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|
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reg:
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maxItems: 1
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|
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clocks:
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minItems: 1
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maxItems: 2
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|
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clock-names:
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minItems: 1
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maxItems: 2
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items:
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- const: usbh
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- const: usb_ref
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resets:
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maxItems: 1
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"#phy-cells":
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const: 1
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additionalProperties: false
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- "#phy-cells"
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|
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if:
|
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properties:
|
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compatible:
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enum:
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- brcm,bcm6318-usbh-phy
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- brcm,bcm6328-usbh-phy
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- brcm,bcm6362-usbh-phy
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- brcm,bcm63268-usbh-phy
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then:
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properties:
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power-domains:
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maxItems: 1
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required:
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- power-domains
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else:
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properties:
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power-domains: false
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examples:
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- |
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usbh: usb-phy@10001700 {
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compatible = "brcm,bcm6368-usbh-phy";
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reg = <0x10001700 0x38>;
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clocks = <&periph_clk 15>;
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clock-names = "usbh";
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resets = <&periph_rst 12>;
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#phy-cells = <1>;
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};
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@@ -12,6 +12,13 @@ Required properties:
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- #address-cells: should be 1.
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- #size-cells: should be 0.
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Optional properties:
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- reg-names: must be "comphy" as the first name, and "conf".
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- reg: must contain the comphy register location and length as the first
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pair, followed by an optional configuration register address and
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length pair.
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A sub-node is required for each comphy lane provided by the comphy.
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Required properties (child nodes):
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@@ -24,7 +31,8 @@ Example:
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comphy: phy@18300 {
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compatible = "marvell,armada-380-comphy";
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reg = <0x18300 0x100>;
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reg-names = "comphy", "conf";
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reg = <0x18300 0x100>, <0x18460 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -0,0 +1,55 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-hs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
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maintainers:
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- Ansuel Smith <ansuelsmth@gmail.com>
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description:
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DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
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controllers used in ipq806x. Each DWC3 PHY controller should have its
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own node.
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properties:
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compatible:
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const: qcom,ipq806x-usb-phy-hs
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|
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"#phy-cells":
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const: 0
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|
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reg:
|
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maxItems: 1
|
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|
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clocks:
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minItems: 1
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maxItems: 2
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|
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clock-names:
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minItems: 1
|
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maxItems: 2
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items:
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- const: ref
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- const: xo
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|
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required:
|
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- compatible
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- "#phy-cells"
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- reg
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- clocks
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- clock-names
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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hs_phy_0: phy@110f8800 {
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compatible = "qcom,ipq806x-usb-phy-hs";
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reg = <0x110f8800 0x30>;
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clocks = <&gcc USB30_0_UTMI_CLK>;
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clock-names = "ref";
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#phy-cells = <0>;
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};
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@@ -0,0 +1,73 @@
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/phy/qcom,ipq806x-usb-phy-ss.yaml#
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||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
|
||||
title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER
|
||||
|
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maintainers:
|
||||
- Ansuel Smith <ansuelsmth@gmail.com>
|
||||
|
||||
description:
|
||||
DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
|
||||
controllers used in ipq806x. Each DWC3 PHY controller should have its
|
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own node.
|
||||
|
||||
properties:
|
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compatible:
|
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const: qcom,ipq806x-usb-phy-ss
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|
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"#phy-cells":
|
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const: 0
|
||||
|
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reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
items:
|
||||
- const: ref
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- const: xo
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|
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qcom,rx-eq:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Override value for rx_eq.
|
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default: 4
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maximum: 7
|
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|
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qcom,tx-deamp-3_5db:
|
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Override value for transmit preemphasis.
|
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default: 23
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maximum: 63
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||||
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qcom,mpll:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Override value for mpll.
|
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default: 0
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maximum: 7
|
||||
|
||||
required:
|
||||
- compatible
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||||
- "#phy-cells"
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
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||||
|
||||
examples:
|
||||
- |
|
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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|
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ss_phy_0: phy@110f8830 {
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compatible = "qcom,ipq806x-usb-phy-ss";
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reg = <0x110f8830 0x30>;
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clocks = <&gcc USB30_0_MASTER_CLK>;
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clock-names = "ref";
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#phy-cells = <0>;
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||||
};
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@@ -18,6 +18,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq8074-qmp-pcie-phy
|
||||
- qcom,ipq8074-qmp-usb3-phy
|
||||
- qcom,msm8996-qmp-pcie-phy
|
||||
- qcom,msm8996-qmp-ufs-phy
|
||||
- qcom,msm8996-qmp-usb3-phy
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||||
@@ -161,6 +162,7 @@ allOf:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,ipq8074-qmp-usb3-phy
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||||
- qcom,msm8996-qmp-usb3-phy
|
||||
- qcom,msm8998-qmp-pcie-phy
|
||||
- qcom,msm8998-qmp-usb3-phy
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||||
|
||||
@@ -18,6 +18,7 @@ properties:
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||||
oneOf:
|
||||
- items:
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||||
- enum:
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||||
- qcom,ipq8074-qusb2-phy
|
||||
- qcom,msm8996-qusb2-phy
|
||||
- qcom,msm8998-qusb2-phy
|
||||
- items:
|
||||
|
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@@ -21,6 +21,7 @@ properties:
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||||
- renesas,usb2-phy-r8a774a1 # RZ/G2M
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- renesas,usb2-phy-r8a774b1 # RZ/G2N
|
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- renesas,usb2-phy-r8a774c0 # RZ/G2E
|
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- renesas,usb2-phy-r8a774e1 # RZ/G2H
|
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- renesas,usb2-phy-r8a7795 # R-Car H3
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- renesas,usb2-phy-r8a7796 # R-Car M3-W
|
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- renesas,usb2-phy-r8a77961 # R-Car M3-W+
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@@ -15,6 +15,7 @@ properties:
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- enum:
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- renesas,r8a774a1-usb3-phy # RZ/G2M
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- renesas,r8a774b1-usb3-phy # RZ/G2N
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- renesas,r8a774e1-usb3-phy # RZ/G2H
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- renesas,r8a7795-usb3-phy # R-Car H3
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- renesas,r8a7796-usb3-phy # R-Car M3-W
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- renesas,r8a77961-usb3-phy # R-Car M3-W+
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@@ -0,0 +1,75 @@
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||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: Samsung SoC series UFS PHY Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Alim Akhtar <alim.akhtar@samsung.com>
|
||||
|
||||
properties:
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos7-ufs-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
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|
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reg-names:
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items:
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- const: phy-pma
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|
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clocks:
|
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items:
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- description: PLL reference clock
|
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- description: symbol clock for input symbol ( rx0-ch0 symbol clock)
|
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- description: symbol clock for input symbol ( rx1-ch1 symbol clock)
|
||||
- description: symbol clock for output symbol ( tx0 symbol clock)
|
||||
|
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clock-names:
|
||||
items:
|
||||
- const: ref_clk
|
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- const: rx1_symbol_clk
|
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- const: rx0_symbol_clk
|
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- const: tx0_symbol_clk
|
||||
|
||||
samsung,pmu-syscon:
|
||||
$ref: '/schemas/types.yaml#/definitions/phandle'
|
||||
description: phandle for PMU system controller interface, used to
|
||||
control pmu registers bits for ufs m-phy
|
||||
|
||||
required:
|
||||
- "#phy-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- clocks
|
||||
- clock-names
|
||||
- samsung,pmu-syscon
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/exynos7-clk.h>
|
||||
|
||||
ufs_phy: ufs-phy@15571800 {
|
||||
compatible = "samsung,exynos7-ufs-phy";
|
||||
reg = <0x15571800 0x240>;
|
||||
reg-names = "phy-pma";
|
||||
samsung,pmu-syscon = <&pmu_system_controller>;
|
||||
#phy-cells = <0>;
|
||||
clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
|
||||
<&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
|
||||
<&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
|
||||
<&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
|
||||
clock-names = "ref_clk", "rx1_symbol_clk",
|
||||
"rx0_symbol_clk", "tx0_symbol_clk";
|
||||
|
||||
};
|
||||
...
|
||||
@@ -31,12 +31,16 @@ properties:
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
oneOf:
|
||||
- const: link # for PXs2
|
||||
- items: # for PXs3
|
||||
- items: # for PXs3 with phy-ext
|
||||
- const: link
|
||||
- const: phy
|
||||
- const: phy-ext
|
||||
- items: # for others
|
||||
- const: link
|
||||
- const: phy
|
||||
|
||||
|
||||
@@ -0,0 +1,105 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
|
||||
description: |
|
||||
This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
|
||||
GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
|
||||
Ethernet SGMII controllers.
|
||||
|
||||
properties:
|
||||
"#phy-cells":
|
||||
const: 4
|
||||
description: |
|
||||
The cells contain the following arguments.
|
||||
|
||||
- description: The GTR lane
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
- description: The PHY type
|
||||
enum:
|
||||
- PHY_TYPE_DP
|
||||
- PHY_TYPE_PCIE
|
||||
- PHY_TYPE_SATA
|
||||
- PHY_TYPE_SGMII
|
||||
- PHY_TYPE_USB
|
||||
- description: The PHY instance
|
||||
minimum: 0
|
||||
maximum: 1 # for DP, SATA or USB
|
||||
maximum: 3 # for PCIE or SGMII
|
||||
- description: The reference clock number
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- xlnx,zynqmp-psgtr-v1.1
|
||||
- xlnx,zynqmp-psgtr
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
description: |
|
||||
Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
|
||||
inputs shall not have an entry.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
items:
|
||||
pattern: "^ref[0-3]$"
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: SERDES registers block
|
||||
- description: SIOU registers block
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: serdes
|
||||
- const: siou
|
||||
|
||||
xlnx,tx-termination-fix:
|
||||
description: |
|
||||
Include this for fixing functional issue with the TX termination
|
||||
resistance in GT, which can be out of spec for the XCZU9EG silicon
|
||||
version.
|
||||
type: boolean
|
||||
|
||||
required:
|
||||
- "#phy-cells"
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: xlnx,zynqmp-psgtr-v1.1
|
||||
|
||||
then:
|
||||
properties:
|
||||
xlnx,tx-termination-fix: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy: phy@fd400000 {
|
||||
compatible = "xlnx,zynqmp-psgtr-v1.1";
|
||||
reg = <0xfd400000 0x40000>,
|
||||
<0xfd3d0000 0x1000>;
|
||||
reg-names = "serdes", "siou";
|
||||
clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
#phy-cells = <4>;
|
||||
};
|
||||
|
||||
...
|
||||
@@ -18862,6 +18862,15 @@ F: Documentation/devicetree/bindings/media/xilinx/
|
||||
F: drivers/media/platform/xilinx/
|
||||
F: include/uapi/linux/xilinx-v4l2-controls.h
|
||||
|
||||
XILINX ZYNQMP PSGTR PHY DRIVER
|
||||
M: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
|
||||
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Supported
|
||||
T: git https://github.com/Xilinx/linux-xlnx.git
|
||||
F: Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
|
||||
F: drivers/phy/xilinx/phy-zynqmp.c
|
||||
|
||||
XILLYBUS DRIVER
|
||||
M: Eli Billauer <eli.billauer@gmail.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
|
||||
@@ -70,5 +70,6 @@ source "drivers/phy/st/Kconfig"
|
||||
source "drivers/phy/tegra/Kconfig"
|
||||
source "drivers/phy/ti/Kconfig"
|
||||
source "drivers/phy/intel/Kconfig"
|
||||
source "drivers/phy/xilinx/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
@@ -8,24 +8,25 @@ obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
|
||||
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
|
||||
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
|
||||
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
|
||||
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
|
||||
obj-$(CONFIG_ARCH_MESON) += amlogic/
|
||||
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
|
||||
obj-$(CONFIG_ARCH_RENESAS) += renesas/
|
||||
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
||||
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
||||
obj-y += broadcom/ \
|
||||
obj-y += allwinner/ \
|
||||
amlogic/ \
|
||||
broadcom/ \
|
||||
cadence/ \
|
||||
freescale/ \
|
||||
hisilicon/ \
|
||||
intel/ \
|
||||
lantiq/ \
|
||||
marvell/ \
|
||||
mediatek/ \
|
||||
motorola/ \
|
||||
mscc/ \
|
||||
qualcomm/ \
|
||||
ralink/ \
|
||||
renesas/ \
|
||||
rockchip/ \
|
||||
samsung/ \
|
||||
socionext/ \
|
||||
st/ \
|
||||
ti/
|
||||
tegra/ \
|
||||
ti/ \
|
||||
xilinx/
|
||||
|
||||
@@ -22,7 +22,7 @@ config PHY_SUN4I_USB
|
||||
config PHY_SUN6I_MIPI_DPHY
|
||||
tristate "Allwinner A31 MIPI D-PHY Support"
|
||||
depends on ARCH_SUNXI || COMPILE_TEST
|
||||
depends on HAS_IOMEM
|
||||
depends on HAS_IOMEM && COMMON_CLK
|
||||
depends on RESET_CONTROLLER
|
||||
select GENERIC_PHY
|
||||
select GENERIC_PHY_MIPI_DPHY
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
* Based on code from
|
||||
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
|
||||
*
|
||||
* Modelled after: Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
|
||||
* Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
|
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
||||
* Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
|
||||
*/
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/extcon-provider.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
@@ -233,7 +233,7 @@ static int sun6i_dphy_exit(struct phy *phy)
|
||||
}
|
||||
|
||||
|
||||
static struct phy_ops sun6i_dphy_ops = {
|
||||
static const struct phy_ops sun6i_dphy_ops = {
|
||||
.configure = sun6i_dphy_configure,
|
||||
.power_on = sun6i_dphy_power_on,
|
||||
.power_off = sun6i_dphy_power_off,
|
||||
@@ -241,7 +241,7 @@ static struct phy_ops sun6i_dphy_ops = {
|
||||
.exit = sun6i_dphy_exit,
|
||||
};
|
||||
|
||||
static struct regmap_config sun6i_dphy_regmap_config = {
|
||||
static const struct regmap_config sun6i_dphy_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
|
||||
@@ -2,6 +2,14 @@
|
||||
#
|
||||
# Phy drivers for Broadcom platforms
|
||||
#
|
||||
config PHY_BCM63XX_USBH
|
||||
tristate "BCM63xx USBH PHY driver"
|
||||
depends on BMIPS_GENERIC || COMPILE_TEST
|
||||
select GENERIC_PHY
|
||||
help
|
||||
Enable this to support the BCM63xx USBH PHY driver.
|
||||
If unsure, say N.
|
||||
|
||||
config PHY_CYGNUS_PCIE
|
||||
tristate "Broadcom Cygnus PCIe PHY driver"
|
||||
depends on OF && (ARCH_BCM_CYGNUS || COMPILE_TEST)
|
||||
|
||||
@@ -1,4 +1,5 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_PHY_BCM63XX_USBH) += phy-bcm63xx-usbh.o
|
||||
obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o
|
||||
obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
|
||||
obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o
|
||||
|
||||
@@ -0,0 +1,457 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* BCM6328 USBH PHY Controller Driver
|
||||
*
|
||||
* Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
* Copyright (C) 2015 Simon Arlott
|
||||
*
|
||||
* Derived from bcm963xx_4.12L.06B_consumer/kernel/linux/arch/mips/bcm963xx/setup.c:
|
||||
* Copyright (C) 2002 Broadcom Corporation
|
||||
*
|
||||
* Derived from OpenWrt patches:
|
||||
* Copyright (C) 2013 Jonas Gorski <jonas.gorski@gmail.com>
|
||||
* Copyright (C) 2013 Florian Fainelli <f.fainelli@gmail.com>
|
||||
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset.h>
|
||||
|
||||
/* USBH control register offsets */
|
||||
enum usbh_regs {
|
||||
USBH_BRT_CONTROL1 = 0,
|
||||
USBH_BRT_CONTROL2,
|
||||
USBH_BRT_STATUS1,
|
||||
USBH_BRT_STATUS2,
|
||||
USBH_UTMI_CONTROL1,
|
||||
#define USBH_UC1_DEV_MODE_SEL BIT(0)
|
||||
USBH_TEST_PORT_CONTROL,
|
||||
USBH_PLL_CONTROL1,
|
||||
#define USBH_PLLC_REFCLKSEL_SHIFT 0
|
||||
#define USBH_PLLC_REFCLKSEL_MASK (0x3 << USBH_PLLC_REFCLKSEL_SHIFT)
|
||||
#define USBH_PLLC_CLKSEL_SHIFT 2
|
||||
#define USBH_PLLC_CLKSEL_MASK (0x3 << USBH_PLLC_CLKSEL_MASK)
|
||||
#define USBH_PLLC_XTAL_PWRDWNB BIT(4)
|
||||
#define USBH_PLLC_PLL_PWRDWNB BIT(5)
|
||||
#define USBH_PLLC_PLL_CALEN BIT(6)
|
||||
#define USBH_PLLC_PHYPLL_BYP BIT(7)
|
||||
#define USBH_PLLC_PLL_RESET BIT(8)
|
||||
#define USBH_PLLC_PLL_IDDQ_PWRDN BIT(9)
|
||||
#define USBH_PLLC_PLL_PWRDN_DELAY BIT(10)
|
||||
#define USBH_6318_PLLC_PLL_SUSPEND_EN BIT(27)
|
||||
#define USBH_6318_PLLC_PHYPLL_BYP BIT(29)
|
||||
#define USBH_6318_PLLC_PLL_RESET BIT(30)
|
||||
#define USBH_6318_PLLC_PLL_IDDQ_PWRDN BIT(31)
|
||||
USBH_SWAP_CONTROL,
|
||||
#define USBH_SC_OHCI_DATA_SWAP BIT(0)
|
||||
#define USBH_SC_OHCI_ENDIAN_SWAP BIT(1)
|
||||
#define USBH_SC_OHCI_LOGICAL_ADDR_EN BIT(2)
|
||||
#define USBH_SC_EHCI_DATA_SWAP BIT(3)
|
||||
#define USBH_SC_EHCI_ENDIAN_SWAP BIT(4)
|
||||
#define USBH_SC_EHCI_LOGICAL_ADDR_EN BIT(5)
|
||||
#define USBH_SC_USB_DEVICE_SEL BIT(6)
|
||||
USBH_GENERIC_CONTROL,
|
||||
#define USBH_GC_PLL_SUSPEND_EN BIT(1)
|
||||
USBH_FRAME_ADJUST_VALUE,
|
||||
USBH_SETUP,
|
||||
#define USBH_S_IOC BIT(4)
|
||||
#define USBH_S_IPP BIT(5)
|
||||
USBH_MDIO,
|
||||
USBH_MDIO32,
|
||||
USBH_USB_SIM_CONTROL,
|
||||
#define USBH_USC_LADDR_SEL BIT(5)
|
||||
|
||||
__USBH_ENUM_SIZE
|
||||
};
|
||||
|
||||
struct bcm63xx_usbh_phy_variant {
|
||||
/* Registers */
|
||||
long regs[__USBH_ENUM_SIZE];
|
||||
|
||||
/* PLLC bits to set/clear for power on */
|
||||
u32 power_pllc_clr;
|
||||
u32 power_pllc_set;
|
||||
|
||||
/* Setup bits to set/clear for power on */
|
||||
u32 setup_clr;
|
||||
u32 setup_set;
|
||||
|
||||
/* Swap Control bits to set */
|
||||
u32 swapctl_dev_set;
|
||||
|
||||
/* Test Port Control value to set if non-zero */
|
||||
u32 tpc_val;
|
||||
|
||||
/* USB Sim Control bits to set */
|
||||
u32 usc_set;
|
||||
|
||||
/* UTMI Control 1 bits to set */
|
||||
u32 utmictl1_dev_set;
|
||||
};
|
||||
|
||||
struct bcm63xx_usbh_phy {
|
||||
void __iomem *base;
|
||||
struct clk *usbh_clk;
|
||||
struct clk *usb_ref_clk;
|
||||
struct reset_control *reset;
|
||||
const struct bcm63xx_usbh_phy_variant *variant;
|
||||
bool device_mode;
|
||||
};
|
||||
|
||||
static const struct bcm63xx_usbh_phy_variant usbh_bcm6318 = {
|
||||
.regs = {
|
||||
[USBH_BRT_CONTROL1] = -1,
|
||||
[USBH_BRT_CONTROL2] = -1,
|
||||
[USBH_BRT_STATUS1] = -1,
|
||||
[USBH_BRT_STATUS2] = -1,
|
||||
[USBH_UTMI_CONTROL1] = 0x2c,
|
||||
[USBH_TEST_PORT_CONTROL] = 0x1c,
|
||||
[USBH_PLL_CONTROL1] = 0x04,
|
||||
[USBH_SWAP_CONTROL] = 0x0c,
|
||||
[USBH_GENERIC_CONTROL] = -1,
|
||||
[USBH_FRAME_ADJUST_VALUE] = 0x08,
|
||||
[USBH_SETUP] = 0x00,
|
||||
[USBH_MDIO] = 0x14,
|
||||
[USBH_MDIO32] = 0x18,
|
||||
[USBH_USB_SIM_CONTROL] = 0x20,
|
||||
},
|
||||
.power_pllc_clr = USBH_6318_PLLC_PLL_IDDQ_PWRDN,
|
||||
.power_pllc_set = USBH_6318_PLLC_PLL_SUSPEND_EN,
|
||||
.setup_set = USBH_S_IOC,
|
||||
.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
|
||||
.usc_set = USBH_USC_LADDR_SEL,
|
||||
.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
|
||||
};
|
||||
|
||||
static const struct bcm63xx_usbh_phy_variant usbh_bcm6328 = {
|
||||
.regs = {
|
||||
[USBH_BRT_CONTROL1] = 0x00,
|
||||
[USBH_BRT_CONTROL2] = 0x04,
|
||||
[USBH_BRT_STATUS1] = 0x08,
|
||||
[USBH_BRT_STATUS2] = 0x0c,
|
||||
[USBH_UTMI_CONTROL1] = 0x10,
|
||||
[USBH_TEST_PORT_CONTROL] = 0x14,
|
||||
[USBH_PLL_CONTROL1] = 0x18,
|
||||
[USBH_SWAP_CONTROL] = 0x1c,
|
||||
[USBH_GENERIC_CONTROL] = 0x20,
|
||||
[USBH_FRAME_ADJUST_VALUE] = 0x24,
|
||||
[USBH_SETUP] = 0x28,
|
||||
[USBH_MDIO] = 0x2c,
|
||||
[USBH_MDIO32] = 0x30,
|
||||
[USBH_USB_SIM_CONTROL] = 0x34,
|
||||
},
|
||||
.setup_set = USBH_S_IOC,
|
||||
.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
|
||||
.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
|
||||
};
|
||||
|
||||
static const struct bcm63xx_usbh_phy_variant usbh_bcm6358 = {
|
||||
.regs = {
|
||||
[USBH_BRT_CONTROL1] = -1,
|
||||
[USBH_BRT_CONTROL2] = -1,
|
||||
[USBH_BRT_STATUS1] = -1,
|
||||
[USBH_BRT_STATUS2] = -1,
|
||||
[USBH_UTMI_CONTROL1] = -1,
|
||||
[USBH_TEST_PORT_CONTROL] = 0x24,
|
||||
[USBH_PLL_CONTROL1] = -1,
|
||||
[USBH_SWAP_CONTROL] = 0x00,
|
||||
[USBH_GENERIC_CONTROL] = -1,
|
||||
[USBH_FRAME_ADJUST_VALUE] = -1,
|
||||
[USBH_SETUP] = -1,
|
||||
[USBH_MDIO] = -1,
|
||||
[USBH_MDIO32] = -1,
|
||||
[USBH_USB_SIM_CONTROL] = -1,
|
||||
},
|
||||
/*
|
||||
* The magic value comes for the original vendor BSP
|
||||
* and is needed for USB to work. Datasheet does not
|
||||
* help, so the magic value is used as-is.
|
||||
*/
|
||||
.tpc_val = 0x1c0020,
|
||||
};
|
||||
|
||||
static const struct bcm63xx_usbh_phy_variant usbh_bcm6368 = {
|
||||
.regs = {
|
||||
[USBH_BRT_CONTROL1] = 0x00,
|
||||
[USBH_BRT_CONTROL2] = 0x04,
|
||||
[USBH_BRT_STATUS1] = 0x08,
|
||||
[USBH_BRT_STATUS2] = 0x0c,
|
||||
[USBH_UTMI_CONTROL1] = 0x10,
|
||||
[USBH_TEST_PORT_CONTROL] = 0x14,
|
||||
[USBH_PLL_CONTROL1] = 0x18,
|
||||
[USBH_SWAP_CONTROL] = 0x1c,
|
||||
[USBH_GENERIC_CONTROL] = -1,
|
||||
[USBH_FRAME_ADJUST_VALUE] = 0x24,
|
||||
[USBH_SETUP] = 0x28,
|
||||
[USBH_MDIO] = 0x2c,
|
||||
[USBH_MDIO32] = 0x30,
|
||||
[USBH_USB_SIM_CONTROL] = 0x34,
|
||||
},
|
||||
.power_pllc_clr = USBH_PLLC_PLL_IDDQ_PWRDN | USBH_PLLC_PLL_PWRDN_DELAY,
|
||||
.setup_set = USBH_S_IOC,
|
||||
.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
|
||||
.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
|
||||
};
|
||||
|
||||
static const struct bcm63xx_usbh_phy_variant usbh_bcm63268 = {
|
||||
.regs = {
|
||||
[USBH_BRT_CONTROL1] = 0x00,
|
||||
[USBH_BRT_CONTROL2] = 0x04,
|
||||
[USBH_BRT_STATUS1] = 0x08,
|
||||
[USBH_BRT_STATUS2] = 0x0c,
|
||||
[USBH_UTMI_CONTROL1] = 0x10,
|
||||
[USBH_TEST_PORT_CONTROL] = 0x14,
|
||||
[USBH_PLL_CONTROL1] = 0x18,
|
||||
[USBH_SWAP_CONTROL] = 0x1c,
|
||||
[USBH_GENERIC_CONTROL] = 0x20,
|
||||
[USBH_FRAME_ADJUST_VALUE] = 0x24,
|
||||
[USBH_SETUP] = 0x28,
|
||||
[USBH_MDIO] = 0x2c,
|
||||
[USBH_MDIO32] = 0x30,
|
||||
[USBH_USB_SIM_CONTROL] = 0x34,
|
||||
},
|
||||
.power_pllc_clr = USBH_PLLC_PLL_IDDQ_PWRDN | USBH_PLLC_PLL_PWRDN_DELAY,
|
||||
.setup_clr = USBH_S_IPP,
|
||||
.setup_set = USBH_S_IOC,
|
||||
.swapctl_dev_set = USBH_SC_USB_DEVICE_SEL,
|
||||
.utmictl1_dev_set = USBH_UC1_DEV_MODE_SEL,
|
||||
};
|
||||
|
||||
static inline bool usbh_has_reg(struct bcm63xx_usbh_phy *usbh, int reg)
|
||||
{
|
||||
return (usbh->variant->regs[reg] >= 0);
|
||||
}
|
||||
|
||||
static inline u32 usbh_readl(struct bcm63xx_usbh_phy *usbh, int reg)
|
||||
{
|
||||
return __raw_readl(usbh->base + usbh->variant->regs[reg]);
|
||||
}
|
||||
|
||||
static inline void usbh_writel(struct bcm63xx_usbh_phy *usbh, int reg,
|
||||
u32 value)
|
||||
{
|
||||
__raw_writel(value, usbh->base + usbh->variant->regs[reg]);
|
||||
}
|
||||
|
||||
static int bcm63xx_usbh_phy_init(struct phy *phy)
|
||||
{
|
||||
struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(usbh->usbh_clk);
|
||||
if (ret) {
|
||||
dev_err(&phy->dev, "unable to enable usbh clock: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(usbh->usb_ref_clk);
|
||||
if (ret) {
|
||||
dev_err(&phy->dev, "unable to enable usb_ref clock: %d\n", ret);
|
||||
clk_disable_unprepare(usbh->usbh_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_reset(usbh->reset);
|
||||
if (ret) {
|
||||
dev_err(&phy->dev, "unable to reset device: %d\n", ret);
|
||||
clk_disable_unprepare(usbh->usb_ref_clk);
|
||||
clk_disable_unprepare(usbh->usbh_clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure to work in native CPU endian */
|
||||
if (usbh_has_reg(usbh, USBH_SWAP_CONTROL)) {
|
||||
u32 val = usbh_readl(usbh, USBH_SWAP_CONTROL);
|
||||
|
||||
val |= USBH_SC_EHCI_DATA_SWAP;
|
||||
val &= ~USBH_SC_EHCI_ENDIAN_SWAP;
|
||||
|
||||
val |= USBH_SC_OHCI_DATA_SWAP;
|
||||
val &= ~USBH_SC_OHCI_ENDIAN_SWAP;
|
||||
|
||||
if (usbh->device_mode && usbh->variant->swapctl_dev_set)
|
||||
val |= usbh->variant->swapctl_dev_set;
|
||||
|
||||
usbh_writel(usbh, USBH_SWAP_CONTROL, val);
|
||||
}
|
||||
|
||||
if (usbh_has_reg(usbh, USBH_SETUP)) {
|
||||
u32 val = usbh_readl(usbh, USBH_SETUP);
|
||||
|
||||
val |= usbh->variant->setup_set;
|
||||
val &= ~usbh->variant->setup_clr;
|
||||
|
||||
usbh_writel(usbh, USBH_SETUP, val);
|
||||
}
|
||||
|
||||
if (usbh_has_reg(usbh, USBH_USB_SIM_CONTROL)) {
|
||||
u32 val = usbh_readl(usbh, USBH_USB_SIM_CONTROL);
|
||||
|
||||
val |= usbh->variant->usc_set;
|
||||
|
||||
usbh_writel(usbh, USBH_USB_SIM_CONTROL, val);
|
||||
}
|
||||
|
||||
if (usbh->variant->tpc_val &&
|
||||
usbh_has_reg(usbh, USBH_TEST_PORT_CONTROL))
|
||||
usbh_writel(usbh, USBH_TEST_PORT_CONTROL,
|
||||
usbh->variant->tpc_val);
|
||||
|
||||
if (usbh->device_mode &&
|
||||
usbh_has_reg(usbh, USBH_UTMI_CONTROL1) &&
|
||||
usbh->variant->utmictl1_dev_set) {
|
||||
u32 val = usbh_readl(usbh, USBH_UTMI_CONTROL1);
|
||||
|
||||
val |= usbh->variant->utmictl1_dev_set;
|
||||
|
||||
usbh_writel(usbh, USBH_UTMI_CONTROL1, val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_usbh_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
|
||||
|
||||
if (usbh_has_reg(usbh, USBH_PLL_CONTROL1)) {
|
||||
u32 val = usbh_readl(usbh, USBH_PLL_CONTROL1);
|
||||
|
||||
val |= usbh->variant->power_pllc_set;
|
||||
val &= ~usbh->variant->power_pllc_clr;
|
||||
|
||||
usbh_writel(usbh, USBH_PLL_CONTROL1, val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_usbh_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
|
||||
|
||||
if (usbh_has_reg(usbh, USBH_PLL_CONTROL1)) {
|
||||
u32 val = usbh_readl(usbh, USBH_PLL_CONTROL1);
|
||||
|
||||
val &= ~usbh->variant->power_pllc_set;
|
||||
val |= usbh->variant->power_pllc_clr;
|
||||
|
||||
usbh_writel(usbh, USBH_PLL_CONTROL1, val);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_usbh_phy_exit(struct phy *phy)
|
||||
{
|
||||
struct bcm63xx_usbh_phy *usbh = phy_get_drvdata(phy);
|
||||
|
||||
clk_disable_unprepare(usbh->usbh_clk);
|
||||
clk_disable_unprepare(usbh->usb_ref_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct phy_ops bcm63xx_usbh_phy_ops = {
|
||||
.exit = bcm63xx_usbh_phy_exit,
|
||||
.init = bcm63xx_usbh_phy_init,
|
||||
.power_off = bcm63xx_usbh_phy_power_off,
|
||||
.power_on = bcm63xx_usbh_phy_power_on,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static struct phy *bcm63xx_usbh_phy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct bcm63xx_usbh_phy *usbh = dev_get_drvdata(dev);
|
||||
|
||||
usbh->device_mode = !!args->args[0];
|
||||
|
||||
return of_phy_simple_xlate(dev, args);
|
||||
}
|
||||
|
||||
static int __init bcm63xx_usbh_phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct bcm63xx_usbh_phy *usbh;
|
||||
const struct bcm63xx_usbh_phy_variant *variant;
|
||||
struct phy *phy;
|
||||
struct phy_provider *phy_provider;
|
||||
|
||||
usbh = devm_kzalloc(dev, sizeof(*usbh), GFP_KERNEL);
|
||||
if (!usbh)
|
||||
return -ENOMEM;
|
||||
|
||||
variant = device_get_match_data(dev);
|
||||
if (!variant)
|
||||
return -EINVAL;
|
||||
usbh->variant = variant;
|
||||
|
||||
usbh->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(usbh->base))
|
||||
return PTR_ERR(usbh->base);
|
||||
|
||||
usbh->reset = devm_reset_control_get_exclusive(dev, NULL);
|
||||
if (IS_ERR(usbh->reset)) {
|
||||
if (PTR_ERR(usbh->reset) != -EPROBE_DEFER)
|
||||
dev_err(dev, "failed to get reset\n");
|
||||
return PTR_ERR(usbh->reset);
|
||||
}
|
||||
|
||||
usbh->usbh_clk = devm_clk_get_optional(dev, "usbh");
|
||||
if (IS_ERR(usbh->usbh_clk))
|
||||
return PTR_ERR(usbh->usbh_clk);
|
||||
|
||||
usbh->usb_ref_clk = devm_clk_get_optional(dev, "usb_ref");
|
||||
if (IS_ERR(usbh->usb_ref_clk))
|
||||
return PTR_ERR(usbh->usb_ref_clk);
|
||||
|
||||
phy = devm_phy_create(dev, NULL, &bcm63xx_usbh_phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "failed to create PHY\n");
|
||||
return PTR_ERR(phy);
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, usbh);
|
||||
phy_set_drvdata(phy, usbh);
|
||||
|
||||
phy_provider = devm_of_phy_provider_register(dev,
|
||||
bcm63xx_usbh_phy_xlate);
|
||||
if (IS_ERR(phy_provider)) {
|
||||
dev_err(dev, "failed to register PHY provider\n");
|
||||
return PTR_ERR(phy_provider);
|
||||
}
|
||||
|
||||
dev_dbg(dev, "Registered BCM63xx USB PHY driver\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id bcm63xx_usbh_phy_ids[] __initconst = {
|
||||
{ .compatible = "brcm,bcm6318-usbh-phy", .data = &usbh_bcm6318 },
|
||||
{ .compatible = "brcm,bcm6328-usbh-phy", .data = &usbh_bcm6328 },
|
||||
{ .compatible = "brcm,bcm6358-usbh-phy", .data = &usbh_bcm6358 },
|
||||
{ .compatible = "brcm,bcm6362-usbh-phy", .data = &usbh_bcm6368 },
|
||||
{ .compatible = "brcm,bcm6368-usbh-phy", .data = &usbh_bcm6368 },
|
||||
{ .compatible = "brcm,bcm63268-usbh-phy", .data = &usbh_bcm63268 },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, bcm63xx_usbh_phy_ids);
|
||||
|
||||
static struct platform_driver bcm63xx_usbh_phy_driver __refdata = {
|
||||
.driver = {
|
||||
.name = "bcm63xx-usbh-phy",
|
||||
.of_match_table = bcm63xx_usbh_phy_ids,
|
||||
},
|
||||
.probe = bcm63xx_usbh_phy_probe,
|
||||
};
|
||||
module_platform_driver(bcm63xx_usbh_phy_driver);
|
||||
|
||||
MODULE_DESCRIPTION("BCM63xx USBH PHY driver");
|
||||
MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
|
||||
MODULE_AUTHOR("Simon Arlott");
|
||||
MODULE_LICENSE("GPL");
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user