mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branches 'for-next/misc', 'for-next/kselftest', 'for-next/efi-preempt', 'for-next/assembler-macro', 'for-next/typos', 'for-next/sme-ptrace-disable', 'for-next/local-tlbi-page-reused', 'for-next/mpam', 'for-next/acpi' and 'for-next/documentation', remote-tracking branch 'arm64/for-next/perf' into for-next/core
* arm64/for-next/perf: perf: arm_spe: Add support for filtering on data source perf: Add perf_event_attr::config4 perf/imx_ddr: Add support for PMU in DB (system interconnects) perf/imx_ddr: Get and enable optional clks perf/imx_ddr: Move ida_alloc() from ddr_perf_init() to ddr_perf_probe() dt-bindings: perf: fsl-imx-ddr: Add compatible string for i.MX8QM, i.MX8QXP and i.MX8DXL arch_topology: Provide a stub topology_core_has_smt() for !CONFIG_GENERIC_ARCH_TOPOLOGY perf/arm-ni: Fix and optimise register offset calculation perf: arm_pmuv3: Add new Cortex and C1 CPU PMUs perf: arm_cspmu: fix error handling in arm_cspmu_impl_unregister() perf/arm-ni: Add NoC S3 support perf/arm_cspmu: nvidia: Add pmevfiltr2 support perf/arm_cspmu: nvidia: Add revision id matching perf/arm_cspmu: Add pmpidr support perf/arm_cspmu: Add callback to reset filter config perf: arm_pmuv3: Don't use PMCCNTR_EL0 on SMT cores * for-next/misc: : Miscellaneous patches arm64: atomics: lse: Remove unused parameters from ATOMIC_FETCH_OP_AND macros arm64: remove duplicate ARCH_HAS_MEM_ENCRYPT arm64: mm: use untagged address to calculate page index arm64: mm: make linear mapping permission update more robust for patial range arm64/mm: Elide TLB flush in certain pte protection transitions arm64/mm: Rename try_pgd_pgtable_alloc_init_mm arm64/mm: Allow __create_pgd_mapping() to propagate pgtable_alloc() errors arm64: add unlikely hint to MTE async fault check in el0_svc_common arm64: acpi: add newline to deferred APEI warning arm64: entry: Clean out some indirection arm64/mm: Ensure PGD_SIZE is aligned to 64 bytes when PA_BITS = 52 arm64/mm: Drop cpu_set_[default|idmap]_tcr_t0sz() arm64: remove unused ARCH_PFN_OFFSET arm64: use SOFTIRQ_ON_OWN_STACK for enabling softirq stack arm64: Remove assertion on CONFIG_VMAP_STACK * for-next/kselftest: : arm64 kselftest patches kselftest/arm64: Align zt-test register dumps * for-next/efi-preempt: : arm64: Make EFI calls preemptible arm64/efi: Call EFI runtime services without disabling preemption arm64/efi: Move uaccess en/disable out of efi_set_pgd() arm64/efi: Drop efi_rt_lock spinlock from EFI arch wrapper arm64/fpsimd: Permit kernel mode NEON with IRQs off arm64/fpsimd: Don't warn when EFI execution context is preemptible efi/runtime-wrappers: Keep track of the efi_runtime_lock owner efi: Add missing static initializer for efi_mm::cpus_allowed_lock * for-next/assembler-macro: : arm64: Replace __ASSEMBLY__ with __ASSEMBLER__ in headers arm64: Replace __ASSEMBLY__ with __ASSEMBLER__ in non-uapi headers arm64: Replace __ASSEMBLY__ with __ASSEMBLER__ in uapi headers * for-next/typos: : Random typo/spelling fixes arm64: Fix double word in comments arm64: Fix typos and spelling errors in comments * for-next/sme-ptrace-disable: : Support disabling streaming mode via ptrace on SME only systems kselftest/arm64: Cover disabling streaming mode without SVE in fp-ptrace kselftst/arm64: Test NT_ARM_SVE FPSIMD format writes on non-SVE systems arm64/sme: Support disabling streaming mode via ptrace on SME only systems * for-next/local-tlbi-page-reused: : arm64, mm: avoid TLBI broadcast if page reused in write fault arm64, tlbflush: don't TLBI broadcast if page reused in write fault mm: add spurious fault fixing support for huge pmd * for-next/mpam: (34 commits) : Basic Arm MPAM driver (more to follow) MAINTAINERS: new entry for MPAM Driver arm_mpam: Add kunit tests for props_mismatch() arm_mpam: Add kunit test for bitmap reset arm_mpam: Add helper to reset saved mbwu state arm_mpam: Use long MBWU counters if supported arm_mpam: Probe for long/lwd mbwu counters arm_mpam: Consider overflow in bandwidth counter state arm_mpam: Track bandwidth counter state for power management arm_mpam: Add mpam_msmon_read() to read monitor value arm_mpam: Add helpers to allocate monitors arm_mpam: Probe and reset the rest of the features arm_mpam: Allow configuration to be applied and restored during cpu online arm_mpam: Use a static key to indicate when mpam is enabled arm_mpam: Register and enable IRQs arm_mpam: Extend reset logic to allow devices to be reset any time arm_mpam: Add a helper to touch an MSC from any CPU arm_mpam: Reset MSC controls from cpuhp callbacks arm_mpam: Merge supported features during mpam_enable() into mpam_class arm_mpam: Probe the hardware features resctrl supports arm_mpam: Add helpers for managing the locking around the mon_sel registers ... * for-next/acpi: : arm64 acpi updates ACPI: GTDT: Get rid of acpi_arch_timer_mem_init() * for-next/documentation: : arm64 Documentation updates Documentation/arm64: Fix the typo of register names
This commit is contained in:
Catalin Marinas
@@ -391,13 +391,13 @@ Before jumping into the kernel, the following conditions must be met:
|
||||
- SMCR_EL2.LEN must be initialised to the same value for all CPUs the
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kernel will execute on.
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||||
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||||
- HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
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||||
- HFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
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||||
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- HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
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||||
- HFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
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||||
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- HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
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- HFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
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- HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
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- HFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
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For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64):
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@@ -402,6 +402,11 @@ The regset data starts with struct user_sve_header, containing:
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streaming mode and any SETREGSET of NT_ARM_SSVE will enter streaming mode
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if the target was not in streaming mode.
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* On systems that do not support SVE it is permitted to use SETREGSET to
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write SVE_PT_REGS_FPSIMD formatted data via NT_ARM_SVE, in this case the
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vector length should be specified as 0. This allows streaming mode to be
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disabled on systems with SME but not SVE.
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* If any register data is provided along with SVE_PT_VL_ONEXEC then the
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registers data will be interpreted with the current vector length, not
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the vector length configured for use on exec.
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+10
@@ -17448,6 +17448,16 @@ S: Maintained
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F: Documentation/devicetree/bindings/leds/backlight/mps,mp3309c.yaml
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F: drivers/video/backlight/mp3309c.c
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MPAM DRIVER
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M: James Morse <james.morse@arm.com>
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M: Ben Horgan <ben.horgan@arm.com>
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R: Reinette Chatre <reinette.chatre@intel.com>
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R: Fenghua Yu <fenghuay@nvidia.com>
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S: Maintained
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F: drivers/resctrl/mpam_*
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F: drivers/resctrl/test_mpam_*
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F: include/linux/arm_mpam.h
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MPS MP2869 DRIVER
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M: Wensheng Wang <wenswang@yeah.net>
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L: linux-hwmon@vger.kernel.org
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+25
-1
@@ -47,7 +47,6 @@ config ARM64
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select ARCH_HAS_SETUP_DMA_OPS
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select ARCH_HAS_SET_DIRECT_MAP
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select ARCH_HAS_SET_MEMORY
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select ARCH_HAS_MEM_ENCRYPT
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select ARCH_HAS_FORCE_DMA_UNENCRYPTED
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select ARCH_STACKWALK
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select ARCH_HAS_STRICT_KERNEL_RWX
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@@ -2023,6 +2022,31 @@ config ARM64_TLB_RANGE
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ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
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range of input addresses.
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config ARM64_MPAM
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bool "Enable support for MPAM"
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select ARM64_MPAM_DRIVER if EXPERT # does nothing yet
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select ACPI_MPAM if ACPI
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help
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Memory System Resource Partitioning and Monitoring (MPAM) is an
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optional extension to the Arm architecture that allows each
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transaction issued to the memory system to be labelled with a
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Partition identifier (PARTID) and Performance Monitoring Group
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identifier (PMG).
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Memory system components, such as the caches, can be configured with
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policies to control how much of various physical resources (such as
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memory bandwidth or cache memory) the transactions labelled with each
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PARTID can consume. Depending on the capabilities of the hardware,
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the PARTID and PMG can also be used as filtering criteria to measure
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the memory system resource consumption of different parts of a
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workload.
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Use of this extension requires CPU support, support in the
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Memory System Components (MSC), and a description from firmware
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of where the MSCs are in the address space.
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MPAM is exposed to user-space via the resctrl pseudo filesystem.
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endmenu # "ARMv8.4 architectural features"
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menu "ARMv8.5 architectural features"
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@@ -19,7 +19,7 @@
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#error "cpucaps have overflown ARM64_CB_BIT"
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#endif
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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#include <linux/stringify.h>
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@@ -207,7 +207,7 @@ alternative_endif
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#define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \
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alternative_insn insn1, insn2, cap, IS_ENABLED(cfg)
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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|
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/*
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* Usage: asm(ALTERNATIVE(oldinstr, newinstr, cpucap));
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@@ -219,7 +219,7 @@ alternative_endif
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#define ALTERNATIVE(oldinstr, newinstr, ...) \
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_ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1)
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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#include <linux/types.h>
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@@ -263,6 +263,6 @@ l_yes:
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return true;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif /* __ASM_ALTERNATIVE_MACROS_H */
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@@ -4,7 +4,7 @@
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#include <asm/alternative-macros.h>
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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#include <linux/init.h>
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#include <linux/types.h>
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@@ -34,5 +34,5 @@ static inline void apply_alternatives_module(void *start, size_t length) { }
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void alt_cb_patch_nops(struct alt_instr *alt, __le32 *origptr,
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__le32 *updptr, int nr_inst);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASSEMBLER__ */
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#endif /* __ASM_ALTERNATIVE_H */
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@@ -9,7 +9,7 @@
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#include <asm/sysreg.h>
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLER__
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#include <linux/irqchip/arm-gic-common.h>
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#include <linux/stringify.h>
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@@ -188,5 +188,5 @@ static inline bool gic_has_relaxed_pmr_sync(void)
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return cpus_have_cap(ARM64_HAS_GIC_PRIO_RELAXED_SYNC);
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}
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#endif /* __ASSEMBLY__ */
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||||
#endif /* __ASSEMBLER__ */
|
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#endif /* __ASM_ARCH_GICV3_H */
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||||
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||||
@@ -27,7 +27,7 @@
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/* Data fields for EX_TYPE_UACCESS_CPY */
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#define EX_DATA_UACCESS_WRITE BIT(0)
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#ifdef __ASSEMBLY__
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#ifdef __ASSEMBLER__
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#define __ASM_EXTABLE_RAW(insn, fixup, type, data) \
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.pushsection __ex_table, "a"; \
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@@ -77,7 +77,7 @@
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__ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_UACCESS_CPY, \uaccess_is_write)
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.endm
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||||
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||||
#else /* __ASSEMBLY__ */
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#else /* __ASSEMBLER__ */
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||||
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||||
#include <linux/stringify.h>
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||||
|
||||
@@ -132,6 +132,6 @@
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||||
EX_DATA_REG(ADDR, addr) \
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")")
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#endif /* __ASSEMBLY__ */
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||||
#endif /* __ASSEMBLER__ */
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||||
|
||||
#endif /* __ASM_ASM_EXTABLE_H */
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||||
@@ -5,7 +5,7 @@
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||||
* Copyright (C) 1996-2000 Russell King
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||||
* Copyright (C) 2012 ARM Ltd.
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||||
*/
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||||
#ifndef __ASSEMBLY__
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||||
#ifndef __ASSEMBLER__
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||||
#error "Only include this from assembly code"
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||||
#endif
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||||
|
||||
@@ -371,7 +371,7 @@ alternative_endif
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||||
* [start, end) with dcache line size explicitly provided.
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||||
*
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||||
* op: operation passed to dc instruction
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||||
* domain: domain used in dsb instruciton
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||||
* domain: domain used in dsb instruction
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||||
* start: starting virtual address of the region
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||||
* end: end virtual address of the region
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||||
* linesz: dcache line size
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||||
@@ -412,7 +412,7 @@ alternative_endif
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||||
* [start, end)
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*
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* op: operation passed to dc instruction
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* domain: domain used in dsb instruciton
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||||
* domain: domain used in dsb instruction
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||||
* start: starting virtual address of the region
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||||
* end: end virtual address of the region
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* fixup: optional label to branch to on user fault
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||||
|
||||
@@ -103,17 +103,17 @@ static __always_inline void __lse_atomic_and(int i, atomic_t *v)
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return __lse_atomic_andnot(~i, v);
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||||
}
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||||
|
||||
#define ATOMIC_FETCH_OP_AND(name, mb, cl...) \
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||||
#define ATOMIC_FETCH_OP_AND(name) \
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||||
static __always_inline int \
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||||
__lse_atomic_fetch_and##name(int i, atomic_t *v) \
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||||
{ \
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||||
return __lse_atomic_fetch_andnot##name(~i, v); \
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||||
}
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||||
|
||||
ATOMIC_FETCH_OP_AND(_relaxed, )
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ATOMIC_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC_FETCH_OP_AND(_release, l, "memory")
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||||
ATOMIC_FETCH_OP_AND( , al, "memory")
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||||
ATOMIC_FETCH_OP_AND(_relaxed)
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||||
ATOMIC_FETCH_OP_AND(_acquire)
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||||
ATOMIC_FETCH_OP_AND(_release)
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||||
ATOMIC_FETCH_OP_AND( )
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||||
|
||||
#undef ATOMIC_FETCH_OP_AND
|
||||
|
||||
@@ -210,17 +210,17 @@ static __always_inline void __lse_atomic64_and(s64 i, atomic64_t *v)
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||||
return __lse_atomic64_andnot(~i, v);
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||||
}
|
||||
|
||||
#define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \
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||||
#define ATOMIC64_FETCH_OP_AND(name) \
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||||
static __always_inline long \
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||||
__lse_atomic64_fetch_and##name(s64 i, atomic64_t *v) \
|
||||
{ \
|
||||
return __lse_atomic64_fetch_andnot##name(~i, v); \
|
||||
}
|
||||
|
||||
ATOMIC64_FETCH_OP_AND(_relaxed, )
|
||||
ATOMIC64_FETCH_OP_AND(_acquire, a, "memory")
|
||||
ATOMIC64_FETCH_OP_AND(_release, l, "memory")
|
||||
ATOMIC64_FETCH_OP_AND( , al, "memory")
|
||||
ATOMIC64_FETCH_OP_AND(_relaxed)
|
||||
ATOMIC64_FETCH_OP_AND(_acquire)
|
||||
ATOMIC64_FETCH_OP_AND(_release)
|
||||
ATOMIC64_FETCH_OP_AND( )
|
||||
|
||||
#undef ATOMIC64_FETCH_OP_AND
|
||||
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
#ifndef __ASM_BARRIER_H
|
||||
#define __ASM_BARRIER_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <linux/kasan-checks.h>
|
||||
|
||||
@@ -221,6 +221,6 @@ do { \
|
||||
|
||||
#include <asm-generic/barrier.h>
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* __ASM_BARRIER_H */
|
||||
|
||||
@@ -35,7 +35,7 @@
|
||||
#define ARCH_DMA_MINALIGN (128)
|
||||
#define ARCH_KMALLOC_MINALIGN (8)
|
||||
|
||||
#if !defined(__ASSEMBLY__) && !defined(BUILD_VDSO)
|
||||
#if !defined(__ASSEMBLER__) && !defined(BUILD_VDSO)
|
||||
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/kasan-enabled.h>
|
||||
@@ -135,6 +135,6 @@ static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
|
||||
return ctr;
|
||||
}
|
||||
|
||||
#endif /* !defined(__ASSEMBLY__) && !defined(BUILD_VDSO) */
|
||||
#endif /* !defined(__ASSEMBLER__) && !defined(BUILD_VDSO) */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -5,7 +5,7 @@
|
||||
|
||||
#include <asm/cpucap-defs.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <linux/types.h>
|
||||
/*
|
||||
* Check whether a cpucap is possible at compiletime.
|
||||
@@ -77,6 +77,6 @@ cpucap_is_possible(const unsigned int cap)
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* __ASM_CPUCAPS_H */
|
||||
|
||||
@@ -19,7 +19,7 @@
|
||||
#define ARM64_SW_FEATURE_OVERRIDE_HVHE 4
|
||||
#define ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF 8
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <linux/bug.h>
|
||||
#include <linux/jump_label.h>
|
||||
@@ -199,7 +199,7 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
|
||||
* registers (e.g, SCTLR, TCR etc.) or patching the kernel via
|
||||
* alternatives. The kernel patching is batched and performed at later
|
||||
* point. The actions are always initiated only after the capability
|
||||
* is finalised. This is usally denoted by "enabling" the capability.
|
||||
* is finalised. This is usually denoted by "enabling" the capability.
|
||||
* The actions are initiated as follows :
|
||||
* a) Action is triggered on all online CPUs, after the capability is
|
||||
* finalised, invoked within the stop_machine() context from
|
||||
@@ -251,7 +251,7 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
|
||||
#define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0))
|
||||
#define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1))
|
||||
/*
|
||||
* The capabilitiy is detected on the Boot CPU and is used by kernel
|
||||
* The capability is detected on the Boot CPU and is used by kernel
|
||||
* during early boot. i.e, the capability should be "detected" and
|
||||
* "enabled" as early as possibly on all booting CPUs.
|
||||
*/
|
||||
@@ -1078,6 +1078,6 @@ static inline bool cpu_has_lpa2(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -249,7 +249,7 @@
|
||||
#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
|
||||
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <asm/sysreg.h>
|
||||
|
||||
@@ -328,6 +328,6 @@ static inline u32 __attribute_const__ read_cpuid_cachetype(void)
|
||||
{
|
||||
return read_cpuid(CTR_EL0);
|
||||
}
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
|
||||
#include <linux/compiler.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
struct task_struct;
|
||||
|
||||
@@ -23,7 +23,7 @@ static __always_inline struct task_struct *get_current(void)
|
||||
|
||||
#define current get_current()
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* __ASM_CURRENT_H */
|
||||
|
||||
|
||||
@@ -48,7 +48,7 @@
|
||||
#define AARCH32_BREAK_THUMB2_LO 0xf7f0
|
||||
#define AARCH32_BREAK_THUMB2_HI 0xa000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
struct task_struct;
|
||||
|
||||
#define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */
|
||||
@@ -88,5 +88,5 @@ static inline bool try_step_suspended_breakpoints(struct pt_regs *regs)
|
||||
|
||||
bool try_handle_aarch32_break(struct pt_regs *regs);
|
||||
|
||||
#endif /* __ASSEMBLY */
|
||||
#endif /* __ASSEMBLER__ */
|
||||
#endif /* __ASM_DEBUG_MONITORS_H */
|
||||
|
||||
@@ -126,21 +126,14 @@ static inline void efi_set_pgd(struct mm_struct *mm)
|
||||
if (mm != current->active_mm) {
|
||||
/*
|
||||
* Update the current thread's saved ttbr0 since it is
|
||||
* restored as part of a return from exception. Enable
|
||||
* access to the valid TTBR0_EL1 and invoke the errata
|
||||
* workaround directly since there is no return from
|
||||
* exception when invoking the EFI run-time services.
|
||||
* restored as part of a return from exception.
|
||||
*/
|
||||
update_saved_ttbr0(current, mm);
|
||||
uaccess_ttbr0_enable();
|
||||
post_ttbr_update_workaround();
|
||||
} else {
|
||||
/*
|
||||
* Defer the switch to the current thread's TTBR0_EL1
|
||||
* until uaccess_enable(). Restore the current
|
||||
* thread's saved ttbr0 corresponding to its active_mm
|
||||
* Restore the current thread's saved ttbr0
|
||||
* corresponding to its active_mm
|
||||
*/
|
||||
uaccess_ttbr0_disable();
|
||||
update_saved_ttbr0(current, current->active_mm);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -7,7 +7,7 @@
|
||||
#ifndef __ARM_KVM_INIT_H__
|
||||
#define __ARM_KVM_INIT_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
#error Assembly-only header
|
||||
#endif
|
||||
|
||||
@@ -28,7 +28,7 @@
|
||||
* Fruity CPUs seem to have HCR_EL2.E2H set to RAO/WI, but
|
||||
* don't advertise it (they predate this relaxation).
|
||||
*
|
||||
* Initalize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H
|
||||
* Initialize HCR_EL2.E2H so that later code can rely upon HCR_EL2.E2H
|
||||
* indicating whether the CPU is running in E2H mode.
|
||||
*/
|
||||
mrs_s x1, SYS_ID_AA64MMFR4_EL1
|
||||
|
||||
@@ -133,7 +133,7 @@
|
||||
#define ELF_ET_DYN_BASE (2 * DEFAULT_MAP_WINDOW_64 / 3)
|
||||
#endif /* CONFIG_ARM64_FORCE_52BIT */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
#include <uapi/linux/elf.h>
|
||||
#include <linux/bug.h>
|
||||
@@ -293,6 +293,6 @@ static inline int arch_check_elf(void *ehdr, bool has_interp,
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
#endif
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user