mirror of
https://github.com/linux-msm/laptops-kernel.git
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Merge tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic updates from Arnd Bergmann:
"The asm-generic tree contains three separate changes for linux-5.19:
- The h8300 architecture is retired after it has been effectively
unmaintained for a number of years. This is the last architecture
we supported that has no MMU implementation, but there are still a
few architectures (arm, m68k, riscv, sh and xtensa) that support
CPUs with and without an MMU.
- A series to add a generic ticket spinlock that can be shared by
most architectures with a working cmpxchg or ll/sc type atomic,
including the conversion of riscv, csky and openrisc. This series
is also a prerequisite for the loongarch64 architecture port that
will come as a separate pull request.
- A cleanup of some exported uapi header files to ensure they can be
included from user space without relying on other kernel headers"
* tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
h8300: remove stale bindings and symlink
sparc: add asm/stat.h to UAPI compile-test coverage
powerpc: add asm/stat.h to UAPI compile-test coverage
mips: add asm/stat.h to UAPI compile-test coverage
riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage
kbuild: prevent exported headers from including <stdlib.h>, <stdbool.h>
agpgart.h: do not include <stdlib.h> from exported header
csky: Move to generic ticket-spinlock
RISC-V: Move to queued RW locks
RISC-V: Move to generic spinlocks
openrisc: Move to ticket-spinlock
asm-generic: qrwlock: Document the spinlock fairness requirements
asm-generic: qspinlock: Indicate the use of mixed-size atomics
asm-generic: ticket-lock: New generic ticket-based spinlock
remove the h8300 architecture
This commit is contained in:
Linus Torvalds
@@ -1,24 +0,0 @@
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* Renesas H8/300 divider clock
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Required Properties:
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- compatible: Must be "renesas,h8300-div-clock"
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- clocks: Reference to the parent clocks ("extal1" and "extal2")
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- #clock-cells: Must be 1
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- reg: Base address and length of the divide rate selector
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- renesas,width: bit width of selector
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Example
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-------
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cclk: cclk {
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compatible = "renesas,h8300-div-clock";
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clocks = <&xclk>;
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#clock-cells = <0>;
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reg = <0xfee01b 2>;
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renesas,width = <2>;
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};
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@@ -1,23 +0,0 @@
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Renesas H8S2678 PLL clock
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This device is Clock multiplyer
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Required Properties:
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- compatible: Must be "renesas,h8s2678-pll-clock"
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- clocks: Reference to the parent clocks
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- #clock-cells: Must be 0
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- reg: Two rate selector (Multiply / Divide) register address
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Example
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-------
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pllclk: pllclk {
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compatible = "renesas,h8s2678-pll-clock";
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clocks = <&xclk>;
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#clock-cells = <0>;
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reg = <0xfee03b 2>, <0xfee045 2>;
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};
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@@ -1,13 +0,0 @@
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* H8/300 CPU bindings
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Required properties:
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- compatible: Compatible property value should be "renesas,h8300".
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- clock-frequency: Contains the clock frequency for CPU, in Hz.
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Example:
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cpu@0 {
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compatible = "renesas,h8300";
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clock-frequency = <20000000>;
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};
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@@ -1,22 +0,0 @@
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* H8/300H Interrupt controller
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Required properties:
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- compatible: has to be "renesas,h8300h-intc", "renesas,h8300-intc" as fallback.
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- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
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interrupts.txt in this directory
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- regs: Base address of interrupt controller registers.
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Optional properties:
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- any properties, listed in interrupts.txt, and any standard resource allocation
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properties
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Example:
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h8intc: interrupt-controller@fee012 {
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compatible = "renesas,h8300h-intc", "renesas,h8300-intc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xfee012 7>;
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};
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@@ -1,22 +0,0 @@
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* H8S Interrupt controller
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Required properties:
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- compatible: has to be "renesas,h8s-intc", "renesas,h8300-intc" as fallback.
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- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
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interrupts.txt in this directory
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- regs: Base address of interrupt controller registers.
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Optional properties:
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- any properties, listed in interrupts.txt, and any standard resource allocation
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properties
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Example:
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h8intc: interrupt-controller@fffe00 {
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compatible = "renesas,h8s-intc", "renesas,h8300-intc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0xfffe00 24>;
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};
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@@ -1,35 +0,0 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/renesas,h8300-bsc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: H8/300 bus controller
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Yoshinori Sato <ysato@users.sourceforge.jp>
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properties:
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compatible:
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items:
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- enum:
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- renesas,h8300h-bsc
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- renesas,h8s-bsc
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- const: renesas,h8300-bsc
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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memory-controller@fee01e {
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compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
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reg = <0xfee01e 8>;
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};
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@@ -1,25 +0,0 @@
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* Renesas H8/300 16bit timer
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The 16bit timer is a 16bit timer/counter with configurable clock inputs and
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programmable compare match.
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Required Properties:
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- compatible: must contain "renesas,16bit-timer"
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- reg: base address and length of the registers block for the timer module.
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- interrupts: interrupt-specifier for the timer, IMIA
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- clocks: a list of phandle, one for each entry in clock-names.
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- clock-names: must contain "peripheral_clk" for the functional clock.
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- renesas,channel: timer channel number.
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Example:
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timer16: timer@ffff68 {
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compatible = "reneas,16bit-timer";
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reg = <0xffff68 8>, <0xffff60 8>;
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interrupts = <24>;
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renesas,channel = <0>;
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clocks = <&pclk>;
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clock-names = "peripheral_clk";
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};
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@@ -1,25 +0,0 @@
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* Renesas H8/300 8bit timer
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The 8bit timer is a 8bit timer/counter with configurable clock inputs and
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programmable compare match.
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This implement only supported cascade mode.
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Required Properties:
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- compatible: must contain "renesas,8bit-timer"
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- reg: base address and length of the registers block for the timer module.
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- interrupts: interrupt-specifier for the timer, CMIA and TOVI
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- clocks: a list of phandle, one for each entry in clock-names.
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- clock-names: must contain "fck" for the functional clock.
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Example:
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timer8_0: timer@ffff80 {
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compatible = "renesas,8bit-timer";
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reg = <0xffff80 10>;
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interrupts = <36>;
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clocks = <&fclk>;
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clock-names = "fck";
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};
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@@ -11,7 +11,6 @@
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| arm: | TODO |
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| arm64: | TODO |
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| csky: | TODO |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | TODO |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | ok |
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| h8300: | TODO |
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| hexagon: | ok |
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| ia64: | ok |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | TODO |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | TODO |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | ok |
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| h8300: | TODO |
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| hexagon: | ok |
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| ia64: | ok |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | TODO |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | TODO |
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| arm64: | ok |
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| csky: | TODO |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | ok |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | TODO |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | TODO |
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| h8300: | ok |
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| hexagon: | ok |
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| ia64: | TODO |
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| m68k: | TODO |
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@@ -11,7 +11,6 @@
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| arm: | ok |
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| arm64: | ok |
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| csky: | ok |
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| h8300: | TODO |
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| hexagon: | TODO |
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| ia64: | TODO |
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| m68k: | TODO |
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