mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
powerpc: Remove core support for Marvell mv64x60 hostbridges
There are no longer any platforms that use Marvell's mv64x60 hostbridges so remove the supporting kernel code. CC: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Mark Greer <mgreer@animalcreek.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Mark Greer
committed by
Michael Ellerman
Michael Ellerman
parent
297f831401
commit
04debf21fa
File diff suppressed because it is too large
Load Diff
@@ -28,9 +28,6 @@ obj-$(CONFIG_FSL_85XX_CACHE_SRAM) += fsl_85xx_l2ctlr.o fsl_85xx_cache_sram.o
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obj-$(CONFIG_SIMPLE_GPIO) += simple_gpio.o
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obj-$(CONFIG_FSL_RIO) += fsl_rio.o fsl_rmu.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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mv64x60-$(CONFIG_PCI) += mv64x60_pci.o
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obj-$(CONFIG_MV64X60) += $(mv64x60-y) mv64x60_pic.o mv64x60_dev.o \
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mv64x60_udbg.o
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obj-$(CONFIG_RTC_DRV_CMOS) += rtc_cmos_setup.o
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obj-$(CONFIG_PPC_INDIRECT_PCI) += indirect_pci.o
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@@ -1,13 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MV64X60_H__
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#define __MV64X60_H__
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#include <linux/init.h>
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extern void __init mv64x60_init_irq(void);
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extern unsigned int mv64x60_get_irq(void);
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extern void __init mv64x60_pci_init(void);
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extern void __init mv64x60_init_early(void);
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#endif /* __MV64X60_H__ */
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File diff suppressed because it is too large
Load Diff
@@ -1,171 +0,0 @@
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/*
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* PCI bus setup for Marvell mv64360/mv64460 host bridges (Discovery)
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*
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* Author: Dale Farnsworth <dale@farnsworth.org>
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*
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* 2007 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/stat.h>
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#include <linux/pci.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#define PCI_HEADER_TYPE_INVALID 0x7f /* Invalid PCI header type */
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#ifdef CONFIG_SYSFS
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/* 32-bit hex or dec stringified number + '\n' */
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#define MV64X60_VAL_LEN_MAX 11
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#define MV64X60_PCICFG_CPCI_HOTSWAP 0x68
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static ssize_t mv64x60_hs_reg_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t off, size_t count)
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{
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struct pci_dev *phb;
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u32 v;
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if (off > 0)
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return 0;
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if (count < MV64X60_VAL_LEN_MAX)
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return -EINVAL;
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phb = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (!phb)
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return -ENODEV;
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pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v);
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pci_dev_put(phb);
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return sprintf(buf, "0x%08x\n", v);
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}
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static ssize_t mv64x60_hs_reg_write(struct file *filp, struct kobject *kobj,
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struct bin_attribute *attr, char *buf,
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loff_t off, size_t count)
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{
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struct pci_dev *phb;
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u32 v;
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if (off > 0)
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return 0;
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if (count <= 0)
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return -EINVAL;
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if (sscanf(buf, "%i", &v) != 1)
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return -EINVAL;
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phb = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
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if (!phb)
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return -ENODEV;
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pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v);
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pci_dev_put(phb);
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return count;
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}
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static const struct bin_attribute mv64x60_hs_reg_attr = { /* Hotswap register */
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.attr = {
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.name = "hs_reg",
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.mode = 0644,
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},
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.size = MV64X60_VAL_LEN_MAX,
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.read = mv64x60_hs_reg_read,
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.write = mv64x60_hs_reg_write,
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};
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static int __init mv64x60_sysfs_init(void)
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{
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struct device_node *np;
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struct platform_device *pdev;
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const unsigned int *prop;
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np = of_find_compatible_node(NULL, NULL, "marvell,mv64360");
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if (!np)
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return 0;
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prop = of_get_property(np, "hs_reg_valid", NULL);
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of_node_put(np);
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pdev = platform_device_register_simple("marvell,mv64360", 0, NULL, 0);
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if (IS_ERR(pdev))
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return PTR_ERR(pdev);
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return sysfs_create_bin_file(&pdev->dev.kobj, &mv64x60_hs_reg_attr);
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}
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subsys_initcall(mv64x60_sysfs_init);
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#endif /* CONFIG_SYSFS */
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static void mv64x60_pci_fixup_early(struct pci_dev *dev)
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{
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/*
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* Set the host bridge hdr_type to an invalid value so that
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* pci_setup_device() will ignore the host bridge.
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*/
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dev->hdr_type = PCI_HEADER_TYPE_INVALID;
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64360,
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mv64x60_pci_fixup_early);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_MV64460,
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mv64x60_pci_fixup_early);
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static int __init mv64x60_add_bridge(struct device_node *dev)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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const int *bus_range;
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int primary;
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memset(&rsrc, 0, sizeof(rsrc));
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/* Fetch host bridge registers address */
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if (of_address_to_resource(dev, 0, &rsrc)) {
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printk(KERN_ERR "No PCI reg property in device tree\n");
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return -ENODEV;
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}
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/* Get bus range if any */
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
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" bus 0\n", dev);
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hose = pcibios_alloc_controller(dev);
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if (!hose)
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return -ENOMEM;
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hose->first_busno = bus_range ? bus_range[0] : 0;
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hose->last_busno = bus_range ? bus_range[1] : 0xff;
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setup_indirect_pci(hose, rsrc.start, rsrc.start + 4, 0);
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hose->self_busno = hose->first_busno;
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printk(KERN_INFO "Found MV64x60 PCI host bridge at 0x%016llx. "
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"Firmware bus number: %d->%d\n",
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(unsigned long long)rsrc.start, hose->first_busno,
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hose->last_busno);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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primary = (hose->first_busno == 0);
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pci_process_bridge_OF_ranges(hose, dev, primary);
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return 0;
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}
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void __init mv64x60_pci_init(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, "pci", "marvell,mv64360-pci")
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mv64x60_add_bridge(np);
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}
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@@ -1,297 +0,0 @@
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/*
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* Interrupt handling for Marvell mv64360/mv64460 host bridges (Discovery)
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*
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* Author: Dale Farnsworth <dale@farnsworth.org>
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*
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* 2007 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#include "mv64x60.h"
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/* Interrupt Controller Interface Registers */
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#define MV64X60_IC_MAIN_CAUSE_LO 0x0004
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#define MV64X60_IC_MAIN_CAUSE_HI 0x000c
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#define MV64X60_IC_CPU0_INTR_MASK_LO 0x0014
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#define MV64X60_IC_CPU0_INTR_MASK_HI 0x001c
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#define MV64X60_IC_CPU0_SELECT_CAUSE 0x0024
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#define MV64X60_HIGH_GPP_GROUPS 0x0f000000
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#define MV64X60_SELECT_CAUSE_HIGH 0x40000000
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/* General Purpose Pins Controller Interface Registers */
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#define MV64x60_GPP_INTR_CAUSE 0x0008
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#define MV64x60_GPP_INTR_MASK 0x000c
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#define MV64x60_LEVEL1_LOW 0
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#define MV64x60_LEVEL1_HIGH 1
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#define MV64x60_LEVEL1_GPP 2
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#define MV64x60_LEVEL1_MASK 0x00000060
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#define MV64x60_LEVEL1_OFFSET 5
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#define MV64x60_LEVEL2_MASK 0x0000001f
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#define MV64x60_NUM_IRQS 96
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static DEFINE_SPINLOCK(mv64x60_lock);
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static void __iomem *mv64x60_irq_reg_base;
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static void __iomem *mv64x60_gpp_reg_base;
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/*
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* Interrupt Controller Handling
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*
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* The interrupt controller handles three groups of interrupts:
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* main low: IRQ0-IRQ31
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* main high: IRQ32-IRQ63
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* gpp: IRQ64-IRQ95
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*
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* This code handles interrupts in two levels. Level 1 selects the
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* interrupt group, and level 2 selects an IRQ within that group.
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* Each group has its own irq_chip structure.
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*/
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static u32 mv64x60_cached_low_mask;
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static u32 mv64x60_cached_high_mask = MV64X60_HIGH_GPP_GROUPS;
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static u32 mv64x60_cached_gpp_mask;
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static struct irq_domain *mv64x60_irq_host;
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/*
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* mv64x60_chip_low functions
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*/
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static void mv64x60_mask_low(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_low_mask &= ~(1 << level2);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
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mv64x60_cached_low_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
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}
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static void mv64x60_unmask_low(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_low_mask |= 1 << level2;
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
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mv64x60_cached_low_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
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}
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static struct irq_chip mv64x60_chip_low = {
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.name = "mv64x60_low",
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.irq_mask = mv64x60_mask_low,
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.irq_mask_ack = mv64x60_mask_low,
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.irq_unmask = mv64x60_unmask_low,
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};
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/*
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* mv64x60_chip_high functions
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*/
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static void mv64x60_mask_high(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_high_mask &= ~(1 << level2);
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
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mv64x60_cached_high_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
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}
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static void mv64x60_unmask_high(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_high_mask |= 1 << level2;
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out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
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mv64x60_cached_high_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
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}
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static struct irq_chip mv64x60_chip_high = {
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.name = "mv64x60_high",
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.irq_mask = mv64x60_mask_high,
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.irq_mask_ack = mv64x60_mask_high,
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.irq_unmask = mv64x60_unmask_high,
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};
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/*
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* mv64x60_chip_gpp functions
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*/
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static void mv64x60_mask_gpp(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_gpp_mask &= ~(1 << level2);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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mv64x60_cached_gpp_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
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}
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static void mv64x60_mask_ack_gpp(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_gpp_mask &= ~(1 << level2);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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mv64x60_cached_gpp_mask);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE,
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~(1 << level2));
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
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}
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static void mv64x60_unmask_gpp(struct irq_data *d)
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{
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int level2 = irqd_to_hwirq(d) & MV64x60_LEVEL2_MASK;
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unsigned long flags;
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spin_lock_irqsave(&mv64x60_lock, flags);
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mv64x60_cached_gpp_mask |= 1 << level2;
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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mv64x60_cached_gpp_mask);
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spin_unlock_irqrestore(&mv64x60_lock, flags);
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(void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
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}
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static struct irq_chip mv64x60_chip_gpp = {
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.name = "mv64x60_gpp",
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.irq_mask = mv64x60_mask_gpp,
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.irq_mask_ack = mv64x60_mask_ack_gpp,
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.irq_unmask = mv64x60_unmask_gpp,
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};
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/*
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* mv64x60_host_ops functions
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*/
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static struct irq_chip *mv64x60_chips[] = {
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[MV64x60_LEVEL1_LOW] = &mv64x60_chip_low,
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[MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high,
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[MV64x60_LEVEL1_GPP] = &mv64x60_chip_gpp,
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};
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static int mv64x60_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hwirq)
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{
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int level1;
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irq_set_status_flags(virq, IRQ_LEVEL);
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level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
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BUG_ON(level1 > MV64x60_LEVEL1_GPP);
|
||||
irq_set_chip_and_handler(virq, mv64x60_chips[level1],
|
||||
handle_level_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops mv64x60_host_ops = {
|
||||
.map = mv64x60_host_map,
|
||||
};
|
||||
|
||||
/*
|
||||
* Global functions
|
||||
*/
|
||||
|
||||
void __init mv64x60_init_irq(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
phys_addr_t paddr;
|
||||
unsigned int size;
|
||||
const unsigned int *reg;
|
||||
unsigned long flags;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
|
||||
reg = of_get_property(np, "reg", &size);
|
||||
paddr = of_translate_address(np, reg);
|
||||
mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
|
||||
of_node_put(np);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-pic");
|
||||
reg = of_get_property(np, "reg", &size);
|
||||
paddr = of_translate_address(np, reg);
|
||||
mv64x60_irq_reg_base = ioremap(paddr, reg[1]);
|
||||
|
||||
mv64x60_irq_host = irq_domain_add_linear(np, MV64x60_NUM_IRQS,
|
||||
&mv64x60_host_ops, NULL);
|
||||
|
||||
spin_lock_irqsave(&mv64x60_lock, flags);
|
||||
out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
|
||||
mv64x60_cached_gpp_mask);
|
||||
out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO,
|
||||
mv64x60_cached_low_mask);
|
||||
out_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI,
|
||||
mv64x60_cached_high_mask);
|
||||
|
||||
out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE, 0);
|
||||
out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_LO, 0);
|
||||
out_le32(mv64x60_irq_reg_base + MV64X60_IC_MAIN_CAUSE_HI, 0);
|
||||
spin_unlock_irqrestore(&mv64x60_lock, flags);
|
||||
}
|
||||
|
||||
unsigned int mv64x60_get_irq(void)
|
||||
{
|
||||
u32 cause;
|
||||
int level1;
|
||||
irq_hw_number_t hwirq;
|
||||
int virq = 0;
|
||||
|
||||
cause = in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_SELECT_CAUSE);
|
||||
if (cause & MV64X60_SELECT_CAUSE_HIGH) {
|
||||
cause &= mv64x60_cached_high_mask;
|
||||
level1 = MV64x60_LEVEL1_HIGH;
|
||||
if (cause & MV64X60_HIGH_GPP_GROUPS) {
|
||||
cause = in_le32(mv64x60_gpp_reg_base +
|
||||
MV64x60_GPP_INTR_CAUSE);
|
||||
cause &= mv64x60_cached_gpp_mask;
|
||||
level1 = MV64x60_LEVEL1_GPP;
|
||||
}
|
||||
} else {
|
||||
cause &= mv64x60_cached_low_mask;
|
||||
level1 = MV64x60_LEVEL1_LOW;
|
||||
}
|
||||
if (cause) {
|
||||
hwirq = (level1 << MV64x60_LEVEL1_OFFSET) | __ilog2(cause);
|
||||
virq = irq_linear_revmap(mv64x60_irq_host, hwirq);
|
||||
}
|
||||
|
||||
return virq;
|
||||
}
|
||||
@@ -1,152 +0,0 @@
|
||||
/*
|
||||
* udbg serial input/output routines for the Marvell MV64x60 (Discovery).
|
||||
*
|
||||
* Author: Dale Farnsworth <dale@farnsworth.org>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc. This file is licensed under
|
||||
* the terms of the GNU General Public License version 2. This program
|
||||
* is licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
|
||||
#include <sysdev/mv64x60.h>
|
||||
|
||||
#define MPSC_0_CR1_OFFSET 0x000c
|
||||
|
||||
#define MPSC_0_CR2_OFFSET 0x0010
|
||||
#define MPSC_CHR_2_TCS (1 << 9)
|
||||
|
||||
#define MPSC_0_CHR_10_OFFSET 0x0030
|
||||
|
||||
#define MPSC_INTR_CAUSE_OFF_0 0x0004
|
||||
#define MPSC_INTR_CAUSE_OFF_1 0x000c
|
||||
#define MPSC_INTR_CAUSE_RCC (1<<6)
|
||||
|
||||
static void __iomem *mpsc_base;
|
||||
static void __iomem *mpsc_intr_cause;
|
||||
|
||||
static void mv64x60_udbg_putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
mv64x60_udbg_putc('\r');
|
||||
|
||||
while(in_le32(mpsc_base + MPSC_0_CR2_OFFSET) & MPSC_CHR_2_TCS)
|
||||
;
|
||||
out_le32(mpsc_base + MPSC_0_CR1_OFFSET, c);
|
||||
out_le32(mpsc_base + MPSC_0_CR2_OFFSET, MPSC_CHR_2_TCS);
|
||||
}
|
||||
|
||||
static int mv64x60_udbg_testc(void)
|
||||
{
|
||||
return (in_le32(mpsc_intr_cause) & MPSC_INTR_CAUSE_RCC) != 0;
|
||||
}
|
||||
|
||||
static int mv64x60_udbg_getc(void)
|
||||
{
|
||||
int cause = 0;
|
||||
int c;
|
||||
|
||||
while (!mv64x60_udbg_testc())
|
||||
;
|
||||
|
||||
c = in_8(mpsc_base + MPSC_0_CHR_10_OFFSET + 2);
|
||||
out_8(mpsc_base + MPSC_0_CHR_10_OFFSET + 2, c);
|
||||
out_le32(mpsc_intr_cause, cause & ~MPSC_INTR_CAUSE_RCC);
|
||||
return c;
|
||||
}
|
||||
|
||||
static int mv64x60_udbg_getc_poll(void)
|
||||
{
|
||||
if (!mv64x60_udbg_testc())
|
||||
return -1;
|
||||
|
||||
return mv64x60_udbg_getc();
|
||||
}
|
||||
|
||||
static void mv64x60_udbg_init(void)
|
||||
{
|
||||
struct device_node *np, *mpscintr, *stdout = NULL;
|
||||
const char *path;
|
||||
const phandle *ph;
|
||||
struct resource r[2];
|
||||
const int *block_index;
|
||||
int intr_cause_offset;
|
||||
int err;
|
||||
|
||||
path = of_get_property(of_chosen, "linux,stdout-path", NULL);
|
||||
if (!path)
|
||||
return;
|
||||
|
||||
stdout = of_find_node_by_path(path);
|
||||
if (!stdout)
|
||||
return;
|
||||
|
||||
for_each_compatible_node(np, NULL, "marvell,mv64360-mpsc") {
|
||||
if (np == stdout)
|
||||
break;
|
||||
}
|
||||
|
||||
of_node_put(stdout);
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
block_index = of_get_property(np, "cell-index", NULL);
|
||||
if (!block_index)
|
||||
goto error;
|
||||
|
||||
switch (*block_index) {
|
||||
case 0:
|
||||
intr_cause_offset = MPSC_INTR_CAUSE_OFF_0;
|
||||
break;
|
||||
case 1:
|
||||
intr_cause_offset = MPSC_INTR_CAUSE_OFF_1;
|
||||
break;
|
||||
default:
|
||||
goto error;
|
||||
}
|
||||
|
||||
err = of_address_to_resource(np, 0, &r[0]);
|
||||
if (err)
|
||||
goto error;
|
||||
|
||||
ph = of_get_property(np, "mpscintr", NULL);
|
||||
mpscintr = of_find_node_by_phandle(*ph);
|
||||
if (!mpscintr)
|
||||
goto error;
|
||||
|
||||
err = of_address_to_resource(mpscintr, 0, &r[1]);
|
||||
of_node_put(mpscintr);
|
||||
if (err)
|
||||
goto error;
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
mpsc_base = ioremap(r[0].start, resource_size(&r[0]));
|
||||
if (!mpsc_base)
|
||||
return;
|
||||
|
||||
mpsc_intr_cause = ioremap(r[1].start, resource_size(&r[1]));
|
||||
if (!mpsc_intr_cause) {
|
||||
iounmap(mpsc_base);
|
||||
return;
|
||||
}
|
||||
mpsc_intr_cause += intr_cause_offset;
|
||||
|
||||
udbg_putc = mv64x60_udbg_putc;
|
||||
udbg_getc = mv64x60_udbg_getc;
|
||||
udbg_getc_poll = mv64x60_udbg_getc_poll;
|
||||
|
||||
return;
|
||||
|
||||
error:
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
void mv64x60_init_early(void)
|
||||
{
|
||||
mv64x60_udbg_init();
|
||||
}
|
||||
Reference in New Issue
Block a user