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scsi: ufs: core: Add support for TX Equalization
MIPI Unipro3.0 introduced PA_TxEQGnSetting and PA_PreCodeEn attributes for TX Equalization and Pre-Coding. It is Host Software's responsibility to configure these attributes for both host and device before initiating Power Mode Change to High-Speed Gears. MIPI Unipro3.0 also introduced TX Equalization Training (EQTR) to identify optimal TX Equalization settings for use by both Host's and Device's UniPro. TX EQTR shall be initiated from the most reliable High-Speed Gear (HS-G1) targeting High-Speed Gears (HS-G4 to HS-G6). Implement TX Equalization configuration and TX EQTR procedure as defined in UFSHCI v5.0 specification. The TX EQTR procedure determines the optimal TX Equalization settings by iterating through all possible PreShoot and DeEmphasis combinations and selecting the best combinations for both Host and Device based on Figure of Merit (FOM) evaluation. Reviewed-by: Bean Huo <beanhuo@micron.com> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Can Guo <can.guo@oss.qualcomm.com> Reviewed-by: Peter Wang <peter.wang@mediatek.com> Link: https://patch.msgid.link/20260325152154.1604082-5-can.guo@oss.qualcomm.com Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Can Guo
committed by
Martin K. Petersen
Martin K. Petersen
parent
6669ab18c2
commit
03e5d38e2f
@@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_SCSI_UFSHCD) += ufshcd-core.o
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ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o
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ufshcd-core-y += ufshcd.o ufs-sysfs.o ufs-mcq.o ufs-txeq.o
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ufshcd-core-$(CONFIG_RPMB) += ufs-rpmb.o
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ufshcd-core-$(CONFIG_DEBUG_FS) += ufs-debugfs.o
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ufshcd-core-$(CONFIG_SCSI_UFS_BSG) += ufs_bsg.o
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File diff suppressed because it is too large
Load Diff
@@ -103,6 +103,12 @@ int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
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int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
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int ufshcd_read_device_lvl_exception_id(struct ufs_hba *hba, u64 *exception_id);
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int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear);
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void ufshcd_apply_valid_tx_eq_settings(struct ufs_hba *hba);
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int ufshcd_config_tx_eq_settings(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *pwr_mode);
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void ufshcd_print_tx_eq_params(struct ufs_hba *hba);
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/* Wrapper functions for safely calling variant operations */
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static inline const char *ufshcd_get_var_name(struct ufs_hba *hba)
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{
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@@ -297,6 +303,38 @@ static inline u32 ufshcd_vops_freq_to_gear_speed(struct ufs_hba *hba, unsigned l
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return 0;
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}
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static inline int ufshcd_vops_get_rx_fom(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *pwr_mode,
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struct tx_eqtr_iter *h_iter,
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struct tx_eqtr_iter *d_iter)
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{
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if (hba->vops && hba->vops->get_rx_fom)
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return hba->vops->get_rx_fom(hba, pwr_mode, h_iter, d_iter);
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return 0;
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}
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static inline int ufshcd_vops_apply_tx_eqtr_settings(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *pwr_mode,
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struct tx_eqtr_iter *h_iter,
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struct tx_eqtr_iter *d_iter)
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{
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if (hba->vops && hba->vops->apply_tx_eqtr_settings)
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return hba->vops->apply_tx_eqtr_settings(hba, pwr_mode, h_iter, d_iter);
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return 0;
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}
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static inline int ufshcd_vops_tx_eqtr_notify(struct ufs_hba *hba,
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enum ufs_notify_change_status status,
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struct ufs_pa_layer_attr *pwr_mode)
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{
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if (hba->vops && hba->vops->tx_eqtr_notify)
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return hba->vops->tx_eqtr_notify(hba, status, pwr_mode);
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return 0;
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}
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extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
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/**
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@@ -4343,16 +4343,18 @@ static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
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ret = __ufshcd_send_uic_cmd(hba, cmd);
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if (ret) {
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dev_err(hba->dev,
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"pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
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cmd->command, cmd->argument3, ret);
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"pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) uic error %d\n",
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cmd->command, UIC_GET_ATTR_ID(cmd->argument1),
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cmd->argument3, ret);
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goto out;
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}
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if (!wait_for_completion_timeout(hba->uic_async_done,
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msecs_to_jiffies(uic_cmd_timeout))) {
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dev_err(hba->dev,
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"pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n",
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cmd->command, cmd->argument3);
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"pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) completion timeout\n",
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cmd->command, UIC_GET_ATTR_ID(cmd->argument1),
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cmd->argument3);
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if (!cmd->cmd_active) {
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dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n",
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@@ -4368,14 +4370,16 @@ check_upmcrs:
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status = ufshcd_get_upmcrs(hba);
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if (status != PWR_LOCAL) {
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dev_err(hba->dev,
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"pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
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cmd->command, status);
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"pwr ctrl cmd 0x%x with (MIBattribute 0x%x, mode 0x%x) failed, host upmcrs:0x%x\n",
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cmd->command, UIC_GET_ATTR_ID(cmd->argument1),
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cmd->argument3, status);
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ret = (status != PWR_OK) ? status : -1;
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}
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out:
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if (ret) {
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ufshcd_print_host_state(hba);
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ufshcd_print_pwr_info(hba);
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ufshcd_print_tx_eq_params(hba);
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ufshcd_print_evt_hist(hba);
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}
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@@ -4401,6 +4405,29 @@ out_unlock:
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return ret;
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}
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/**
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* ufshcd_uic_tx_eqtr - Perform UIC TX Equalization Training
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* @hba: per adapter instance
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* @gear: target gear for EQTR
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*
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* Returns 0 on success, negative error code otherwise
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*/
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int ufshcd_uic_tx_eqtr(struct ufs_hba *hba, int gear)
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{
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struct uic_command uic_cmd = {
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.command = UIC_CMD_DME_SET,
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.argument1 = UIC_ARG_MIB(PA_EQTR_GEAR),
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.argument3 = gear,
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};
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int ret;
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ufshcd_hold(hba);
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ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
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ufshcd_release(hba);
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return ret;
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}
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/**
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* ufshcd_send_bsg_uic_cmd - Send UIC commands requested via BSG layer and retrieve the result
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* @hba: per adapter instance
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@@ -4824,6 +4851,12 @@ int ufshcd_config_pwr_mode(struct ufs_hba *hba,
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memcpy(&final_params, desired_pwr_mode, sizeof(final_params));
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}
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ret = ufshcd_config_tx_eq_settings(hba, &final_params);
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if (ret)
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dev_warn(hba->dev, "Failed to configure TX Equalization for HS-G%u, Rate-%s: %d\n",
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final_params.gear_tx,
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ufs_hs_rate_to_str(final_params.hs_rate), ret);
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return ufshcd_change_power_mode(hba, &final_params, pmc_policy);
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}
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EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode);
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@@ -6823,6 +6856,7 @@ again:
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spin_unlock_irqrestore(hba->host->host_lock, flags);
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ufshcd_print_host_state(hba);
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ufshcd_print_pwr_info(hba);
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ufshcd_print_tx_eq_params(hba);
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ufshcd_print_evt_hist(hba);
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ufshcd_print_tmrs(hba, hba->outstanding_tasks);
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ufshcd_print_trs_all(hba, pr_prdt);
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@@ -7086,6 +7120,7 @@ static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status)
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ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE,
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"host_regs: ");
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ufshcd_print_pwr_info(hba);
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ufshcd_print_tx_eq_params(hba);
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}
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ufshcd_schedule_eh_work(hba);
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retval |= IRQ_HANDLED;
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@@ -7867,6 +7902,7 @@ static int ufshcd_abort(struct scsi_cmnd *cmd)
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ufshcd_print_evt_hist(hba);
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ufshcd_print_host_state(hba);
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ufshcd_print_pwr_info(hba);
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ufshcd_print_tx_eq_params(hba);
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ufshcd_print_tr(hba, cmd, true);
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} else {
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ufshcd_print_tr(hba, cmd, false);
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@@ -8844,6 +8880,8 @@ static void ufshcd_tune_unipro_params(struct ufs_hba *hba)
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if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_HIBER8TIME)
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ufshcd_quirk_override_pa_h8time(hba);
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ufshcd_apply_valid_tx_eq_settings(hba);
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}
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static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba)
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@@ -287,6 +287,84 @@ struct ufs_pwr_mode_info {
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struct ufs_pa_layer_attr info;
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};
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#define UFS_MAX_LANES 2
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/**
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* struct tx_eqtr_iter - TX Equalization Training iterator
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* @preshoot_bitmap: PreShoot bitmap
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* @deemphasis_bitmap: DeEmphasis bitmap
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* @preshoot: PreShoot value
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* @deemphasis: DeEmphasis value
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* @fom: Figure-of-Merit read out from RX_FOM
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* @is_updated: Flag to indicate if updated since previous iteration
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*/
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struct tx_eqtr_iter {
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unsigned long preshoot_bitmap;
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unsigned long deemphasis_bitmap;
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u8 preshoot;
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u8 deemphasis;
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u8 fom[UFS_MAX_LANES];
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bool is_updated;
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};
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/**
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* struct ufshcd_tx_eq_settings - TX Equalization settings
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* @preshoot: PreShoot value
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* @deemphasis: DeEmphasis value
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* @fom_val: Figure-of-Merit value read out from RX_FOM (Bit[6:0])
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* @precode_en: Flag to indicate whether need to enable pre-coding
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*/
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struct ufshcd_tx_eq_settings {
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u8 preshoot;
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u8 deemphasis;
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u8 fom_val;
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bool precode_en;
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};
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/**
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* struct ufshcd_tx_eqtr_data - Data used during TX Equalization Training procedure
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* @host: Optimal TX EQ settings identified for host TX Lanes during TX EQTR
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* @device: Optimal TX EQ settings identified for device TX Lanes during TX EQTR
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* @host_fom: Host TX EQTR FOM record
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* @device_fom: Device TX EQTR FOM record
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*/
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struct ufshcd_tx_eqtr_data {
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struct ufshcd_tx_eq_settings host[UFS_MAX_LANES];
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struct ufshcd_tx_eq_settings device[UFS_MAX_LANES];
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u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
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u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
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};
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/**
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* struct ufshcd_tx_eqtr_record - TX Equalization Training record
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* @host_fom: Host TX EQTR FOM record
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* @device_fom: Device TX EQTR FOM record
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* @last_record_ts: Timestamp of the most recent TX EQTR record
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* @last_record_index: Index of the most recent TX EQTR record
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*/
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struct ufshcd_tx_eqtr_record {
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u8 host_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
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u8 device_fom[UFS_MAX_LANES][TX_HS_NUM_PRESHOOT][TX_HS_NUM_DEEMPHASIS];
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ktime_t last_record_ts;
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u16 last_record_index;
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};
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/**
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* struct ufshcd_tx_eq_params - TX Equalization parameters structure
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* @host: TX EQ settings for host TX Lanes
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* @device: TX EQ settings for device TX Lanes
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* @eqtr_record: Pointer to TX EQTR record
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* @is_valid: True if parameter contains valid TX Equalization settings
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* @is_applied: True if settings have been applied to UniPro of both sides
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*/
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struct ufshcd_tx_eq_params {
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struct ufshcd_tx_eq_settings host[UFS_MAX_LANES];
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struct ufshcd_tx_eq_settings device[UFS_MAX_LANES];
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struct ufshcd_tx_eqtr_record *eqtr_record;
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bool is_valid;
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bool is_applied;
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};
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/**
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* struct ufs_hba_variant_ops - variant specific callbacks
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* @name: variant name
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@@ -330,6 +408,11 @@ struct ufs_pwr_mode_info {
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* @config_esi: called to config Event Specific Interrupt
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* @config_scsi_dev: called to configure SCSI device parameters
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* @freq_to_gear_speed: called to map clock frequency to the max supported gear speed
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* @apply_tx_eqtr_settings: called to apply settings for TX Equalization
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* Training settings.
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* @get_rx_fom: called to get Figure of Merit (FOM) value.
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* @tx_eqtr_notify: called before and after TX Equalization Training procedure
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* to allow platform vendor specific configs to take place.
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*/
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struct ufs_hba_variant_ops {
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const char *name;
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@@ -381,6 +464,17 @@ struct ufs_hba_variant_ops {
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int (*config_esi)(struct ufs_hba *hba);
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void (*config_scsi_dev)(struct scsi_device *sdev);
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u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq);
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int (*get_rx_fom)(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *pwr_mode,
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struct tx_eqtr_iter *h_iter,
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struct tx_eqtr_iter *d_iter);
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int (*apply_tx_eqtr_settings)(struct ufs_hba *hba,
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struct ufs_pa_layer_attr *pwr_mode,
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struct tx_eqtr_iter *h_iter,
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struct tx_eqtr_iter *d_iter);
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int (*tx_eqtr_notify)(struct ufs_hba *hba,
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enum ufs_notify_change_status status,
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struct ufs_pa_layer_attr *pwr_mode);
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};
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/* clock gating state */
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@@ -779,6 +873,13 @@ enum ufshcd_caps {
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* WriteBooster when scaling the clock down.
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*/
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UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
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/*
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* This capability allows the host controller driver to apply TX
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* Equalization settings discovered from UFS attributes, variant
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* specific operations and TX Equaliztion Training procedure.
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*/
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UFSHCD_CAP_TX_EQUALIZATION = 1 << 13,
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};
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struct ufs_hba_variant_params {
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@@ -955,6 +1056,15 @@ enum ufshcd_mcq_opr {
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* @dev_lvl_exception_count: count of device level exceptions since last reset
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* @dev_lvl_exception_id: vendor specific information about the device level exception event.
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* @rpmbs: list of OP-TEE RPMB devices (one per RPMB region)
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* @host_preshoot_cap: a bitfield to indicate supported PreShoot dBs of host's TX lanes, cache of
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* host M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15)
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* @host_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of host's TX lanes, cache
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* of host M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12)
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* @device_preshoot_cap: a bitfield to indicate supported PreShoot dBs of device's TX lanes, cache
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* of device M-PHY TX_HS_PreShoot_Setting_Capability Attribute (ID 0x15)
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* @device_deemphasis_cap: a bitfield to indicate supported DeEmphasis dBs of device's TX lanes,
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* cache of device M-PHY TX_HS_DeEmphasis_Setting_Capability Attribute (ID 0x12)
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* @tx_eq_params: TX Equalization settings
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*/
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struct ufs_hba {
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void __iomem *mmio_base;
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@@ -1128,6 +1238,12 @@ struct ufs_hba {
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u64 dev_lvl_exception_id;
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u32 vcc_off_delay_us;
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struct list_head rpmbs;
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u8 host_preshoot_cap;
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u8 host_deemphasis_cap;
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u8 device_preshoot_cap;
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u8 device_deemphasis_cap;
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struct ufshcd_tx_eq_params tx_eq_params[UFS_HS_GEAR_MAX];
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};
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/**
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@@ -1272,6 +1388,13 @@ static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
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return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
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}
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static inline bool ufshcd_is_tx_eq_supported(struct ufs_hba *hba)
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{
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return hba->caps & UFSHCD_CAP_TX_EQUALIZATION &&
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hba->ufs_version >= ufshci_version(5, 0) &&
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hba->dev_info.wspecversion >= 0x500;
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}
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#define ufsmcq_writel(hba, val, reg) \
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writel((val), (hba)->mcq_base + (reg))
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#define ufsmcq_readl(hba, reg) \
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@@ -1287,6 +1410,18 @@ static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
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#define ufshcd_readl(hba, reg) \
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readl((hba)->mmio_base + (reg))
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static inline const char *ufs_hs_rate_to_str(enum ufs_hs_gear_rate rate)
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{
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switch (rate) {
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case PA_HS_MODE_A:
|
||||
return "A";
|
||||
case PA_HS_MODE_B:
|
||||
return "B";
|
||||
default:
|
||||
return "Unknown";
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ufshcd_rmwl - perform read/modify/write for a controller register
|
||||
* @hba: per adapter instance
|
||||
|
||||
+112
-2
@@ -10,6 +10,8 @@
|
||||
* M-TX Configuration Attributes
|
||||
*/
|
||||
#define TX_HIBERN8TIME_CAPABILITY 0x000F
|
||||
#define TX_HS_DEEMPHASIS_SETTING_CAP 0x0012
|
||||
#define TX_HS_PRESHOOT_SETTING_CAP 0x0015
|
||||
#define TX_MODE 0x0021
|
||||
#define TX_HSRATE_SERIES 0x0022
|
||||
#define TX_HSGEAR 0x0023
|
||||
@@ -38,6 +40,9 @@
|
||||
/*
|
||||
* M-RX Configuration Attributes
|
||||
*/
|
||||
#define RX_HS_G5_ADAPT_INITIAL_CAP 0x0074
|
||||
#define RX_HS_G6_ADAPT_INITIAL_CAP 0x007B
|
||||
#define RX_HS_G6_ADAPT_INITIAL_L0L1L2L3_CAP 0x007D
|
||||
#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
|
||||
#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
|
||||
#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
|
||||
@@ -50,6 +55,7 @@
|
||||
#define RX_HIBERN8TIME_CAP 0x0092
|
||||
#define RX_ADV_HIBERN8TIME_CAP 0x0099
|
||||
#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
|
||||
#define RX_HS_G4_ADAPT_INITIAL_CAP 0x009F
|
||||
#define RX_MODE 0x00A1
|
||||
#define RX_HSRATE_SERIES 0x00A2
|
||||
#define RX_HSGEAR 0x00A3
|
||||
@@ -64,6 +70,7 @@
|
||||
#define CFGRXCDR8 0x00BA
|
||||
#define CFGRXOVR8 0x00BD
|
||||
#define CFGRXOVR6 0x00BF
|
||||
#define RX_FOM 0x00C2
|
||||
#define RXDIRECTCTRL2 0x00C7
|
||||
#define CFGRXOVR4 0x00E9
|
||||
#define RX_REFCLKFREQ 0x00EB
|
||||
@@ -73,7 +80,6 @@
|
||||
#define ENARXDIRECTCFG3 0x00F3
|
||||
#define ENARXDIRECTCFG2 0x00F4
|
||||
|
||||
|
||||
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
|
||||
#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
|
||||
#define SYNC_LEN_FINE(x) ((x) & 0x3F)
|
||||
@@ -99,6 +105,18 @@
|
||||
|
||||
#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
|
||||
|
||||
#define ADAPT_LENGTH_MASK 0x7F
|
||||
#define ADAPT_RANGE_BIT BIT(7)
|
||||
#define IS_ADAPT_RANGE_COARSE(x) ((x) & ADAPT_RANGE_BIT)
|
||||
|
||||
/* Adapt definitions */
|
||||
#define ADAPT_LENGTH_MAX 0x91
|
||||
#define ADAPT_L0L3_LENGTH_MAX 0x90
|
||||
#define ADAPT_L0L1L2L3_LENGTH_MAX 0x8C
|
||||
#define TADAPT_FACTOR 650
|
||||
#define TADAPT_L0L3_FACTOR (1 << 9)
|
||||
#define TADAPT_L0L1L2L3_FACTOR (1 << 15)
|
||||
|
||||
/*
|
||||
* PHY Adapter attributes
|
||||
*/
|
||||
@@ -164,10 +182,26 @@
|
||||
#define PA_PACPERRORCOUNT 0x15C1
|
||||
#define PA_PHYTESTCONTROL 0x15C2
|
||||
#define PA_TXHSG4SYNCLENGTH 0x15D0
|
||||
#define PA_PEERRXHSG4ADAPTINITIAL 0x15D3
|
||||
#define PA_TXHSADAPTTYPE 0x15D4
|
||||
#define PA_TXHSG5SYNCLENGTH 0x15D6
|
||||
#define PA_PEERRXHSG5ADAPTINITIAL 0x15D9
|
||||
#define PA_PEERRXHSG6ADAPTREFRESHL0L1L2L3 0x15DE
|
||||
#define PA_PEERRXHSG6ADAPTINITIALL0L3 0x15DF
|
||||
#define PA_PEERRXHSG6ADAPTINITIALL0L1L2L3 0x15E0
|
||||
#define PA_TXEQG1SETTING 0x15E1
|
||||
#define PA_TXEQG2SETTING 0x15E2
|
||||
#define PA_TXEQG3SETTING 0x15E3
|
||||
#define PA_TXEQG4SETTING 0x15E4
|
||||
#define PA_TXEQG5SETTING 0x15E5
|
||||
#define PA_TXEQG6SETTING 0x15E6
|
||||
#define PA_TXEQTRSETTING 0x15E7
|
||||
#define PA_PEERTXEQTRSETTING 0x15E8
|
||||
#define PA_PRECODEEN 0x15E9
|
||||
#define PA_EQTR_GEAR 0x15EA
|
||||
#define PA_TXADAPTLENGTH_EQTR 0x15EB
|
||||
|
||||
/* Adpat type for PA_TXHSADAPTTYPE attribute */
|
||||
/* Adapt type for PA_TXHSADAPTTYPE attribute */
|
||||
#define PA_REFRESH_ADAPT 0x00
|
||||
#define PA_INITIAL_ADAPT 0x01
|
||||
#define PA_NO_ADAPT 0x03
|
||||
@@ -187,6 +221,82 @@
|
||||
/* PHY Adapter Protocol Constants */
|
||||
#define PA_MAXDATALANES 4
|
||||
|
||||
/*
|
||||
* TX EQTR's minimum TAdapt should not be less than 10us.
|
||||
* This value is rounded up into the nearest Unit Intervals (UI)
|
||||
*/
|
||||
#define TX_EQTR_HS_G4_MIN_T_ADAPT 166400
|
||||
#define TX_EQTR_HS_G5_MIN_T_ADAPT 332800
|
||||
#define TX_EQTR_HS_G6_MIN_T_ADAPT 262144
|
||||
|
||||
#define TX_EQTR_HS_G4_ADAPT_DEFAULT 0x88
|
||||
#define TX_EQTR_HS_G5_ADAPT_DEFAULT 0x89
|
||||
#define TX_EQTR_HS_G6_ADAPT_DEFAULT 0x89
|
||||
|
||||
#define TX_EQTR_CAP_MASK 0x7F
|
||||
|
||||
#define TX_EQTR_ADAPT_LENGTH_L0L1L2L3_SHIFT 8
|
||||
#define TX_EQTR_ADAPT_RESERVED 0xFF
|
||||
|
||||
#define TX_HS_NUM_PRESHOOT 8
|
||||
#define TX_HS_NUM_DEEMPHASIS 8
|
||||
#define TX_HS_PRESHOOT_SHIFT 4
|
||||
#define TX_HS_DEEMPHASIS_SHIFT 4
|
||||
#define TX_HS_PRESHOOT_OFFSET 0
|
||||
#define TX_HS_DEEMPHASIS_OFFSET 16
|
||||
|
||||
#define TX_HS_PRESHOOT_LANE_SHIFT(lane) \
|
||||
(TX_HS_PRESHOOT_OFFSET + (lane) * TX_HS_PRESHOOT_SHIFT)
|
||||
#define TX_HS_DEEMPHASIS_LANE_SHIFT(lane) \
|
||||
(TX_HS_DEEMPHASIS_OFFSET + (lane) * TX_HS_DEEMPHASIS_SHIFT)
|
||||
|
||||
#define TX_HS_PRESHOOT_BITS(lane, val) \
|
||||
((val) << TX_HS_PRESHOOT_LANE_SHIFT(lane))
|
||||
#define TX_HS_DEEMPHASIS_BITS(lane, val) \
|
||||
((val) << TX_HS_DEEMPHASIS_LANE_SHIFT(lane))
|
||||
|
||||
#define RX_FOM_VALUE_MASK 0x7F
|
||||
#define RX_FOM_PRECODING_EN_BIT BIT(7)
|
||||
|
||||
#define PRECODEEN_TX_OFFSET 0
|
||||
#define PRECODEEN_RX_OFFSET 4
|
||||
#define PRECODEEN_TX_BIT(lane) (1 << (PRECODEEN_TX_OFFSET + (lane)))
|
||||
#define PRECODEEN_RX_BIT(lane) (1 << (PRECODEEN_RX_OFFSET + (lane)))
|
||||
|
||||
enum ufs_tx_eq_preset {
|
||||
UFS_TX_EQ_PRESET_P0,
|
||||
UFS_TX_EQ_PRESET_P1,
|
||||
UFS_TX_EQ_PRESET_P2,
|
||||
UFS_TX_EQ_PRESET_P3,
|
||||
UFS_TX_EQ_PRESET_P4,
|
||||
UFS_TX_EQ_PRESET_P5,
|
||||
UFS_TX_EQ_PRESET_P6,
|
||||
UFS_TX_EQ_PRESET_P7,
|
||||
UFS_TX_EQ_PRESET_MAX,
|
||||
};
|
||||
|
||||
enum ufs_tx_hs_preshoot {
|
||||
UFS_TX_HS_PRESHOOT_DB_0P0,
|
||||
UFS_TX_HS_PRESHOOT_DB_0P4,
|
||||
UFS_TX_HS_PRESHOOT_DB_0P8,
|
||||
UFS_TX_HS_PRESHOOT_DB_1P2,
|
||||
UFS_TX_HS_PRESHOOT_DB_1P6,
|
||||
UFS_TX_HS_PRESHOOT_DB_2P5,
|
||||
UFS_TX_HS_PRESHOOT_DB_3P5,
|
||||
UFS_TX_HS_PRESHOOT_DB_4P7,
|
||||
};
|
||||
|
||||
enum ufs_tx_hs_deemphasis {
|
||||
UFS_TX_HS_DEEMPHASIS_DB_0P0,
|
||||
UFS_TX_HS_DEEMPHASIS_DB_0P8,
|
||||
UFS_TX_HS_DEEMPHASIS_DB_1P6,
|
||||
UFS_TX_HS_DEEMPHASIS_DB_2P5,
|
||||
UFS_TX_HS_DEEMPHASIS_DB_3P5,
|
||||
UFS_TX_HS_DEEMPHASIS_DB_4P7,
|
||||
UFS_TX_HS_DEEMPHASIS_DB_6P0,
|
||||
UFS_TX_HS_DEEMPHASIS_DB_7P6,
|
||||
};
|
||||
|
||||
#define DL_FC0ProtectionTimeOutVal_Default 8191
|
||||
#define DL_TC0ReplayTimeOutVal_Default 65535
|
||||
#define DL_AFC0ReqTimeOutVal_Default 32767
|
||||
|
||||
Reference in New Issue
Block a user