mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Olof Johansson: "Driver updates for ARM SoCs: Reset subsystem, merged through arm-soc by tradition: - Make bool drivers explicitly non-modular - New support for i.MX7 and Arria10 reset controllers PATA driver for Palmchip BK371 (acked by Tejun) Power domain drivers for i.MX (GPC, GPCv2) - Moved out of mach-imx for GPC - Bunch of tweaks, fixes, etc PMC support for Tegra186 SoC detection support for Renesas RZ/G1H and RZ/G1N Move Tegra flow controller driver from mach directory to drivers/soc - (Power management / CPU power driver) Misc smaller tweaks for other platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) soc: pm-domain: Fix the mangled urls soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0 soc: renesas: rcar-sysc: Add support for fixing up power area tables soc: renesas: Register SoC device early soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible soc: imx: gpc: add defines for domain index soc: imx: Add GPCv2 power gating driver dt-bindings: Add GPCv2 power gating driver ARM/clk: move the ICST library to drivers/clk ARM: plat-versatile: remove stale clock header ARM: keystone: Drop PM domain support for k2g soc: ti: Add ti_sci_pm_domains driver dt-bindings: Add TI SCI PM Domains PM / Domains: Do not check if simple providers have phandle cells PM / Domains: Add generic data pointer to genpd data struct soc/tegra: Add initial flowctrl support for Tegra132/210 soc/tegra: flowctrl: Add basic platform driver soc/tegra: Move Tegra flowctrl driver ARM: tegra: Remove unnecessary inclusion of flowctrl header ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,34 @@
|
||||
NVIDIA Tegra Power Management Controller (PMC)
|
||||
|
||||
Required properties:
|
||||
- compatible: Should contain one of the following:
|
||||
- "nvidia,tegra186-pmc": for Tegra186
|
||||
- reg: Must contain an (offset, length) pair of the register set for each
|
||||
entry in reg-names.
|
||||
- reg-names: Must include the following entries:
|
||||
- "pmc"
|
||||
- "wake"
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||||
- "aotag"
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- "scratch"
|
||||
|
||||
Optional properties:
|
||||
- nvidia,invert-interrupt: If present, inverts the PMU interrupt signal.
|
||||
|
||||
Example:
|
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|
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SoC DTSI:
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|
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pmc@c3600000 {
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compatible = "nvidia,tegra186-pmc";
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reg = <0 0x0c360000 0 0x10000>,
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<0 0x0c370000 0 0x10000>,
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<0 0x0c380000 0 0x10000>,
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<0 0x0c390000 0 0x10000>;
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reg-names = "pmc", "wake", "aotag", "scratch";
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};
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Board DTS:
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pmc@c360000 {
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nvidia,invert-interrupt;
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};
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@@ -1,22 +1,42 @@
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Freescale i.MX General Power Controller
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||||
=======================================
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|
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The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
|
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counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
|
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domains.
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The i.MX6 General Power Control (GPC) block contains DVFS load tracking
|
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counters and Power Gating Control (PGC).
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|
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Required properties:
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- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc"
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- compatible: Should be one of the following:
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- fsl,imx6q-gpc
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- fsl,imx6qp-gpc
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- fsl,imx6sl-gpc
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- reg: should be register base and length as documented in the
|
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datasheet
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- interrupts: Should contain GPC interrupt request 1
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- pu-supply: Link to the LDO regulator powering the PU power domain
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- clocks: Clock phandles to devices in the PU power domain that need
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to be enabled during domain power-up for reset propagation.
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- #power-domain-cells: Should be 1, see below:
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- interrupts: Should contain one interrupt specifier for the GPC interrupt
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- clocks: Must contain an entry for each entry in clock-names.
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See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- ipg
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The gpc node is a power-controller as documented by the generic power domain
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bindings in Documentation/devicetree/bindings/power/power_domain.txt.
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The power domains are generic power domain providers as documented in
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Documentation/devicetree/bindings/power/power_domain.txt. They are described as
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subnodes of the power gating controller 'pgc' node of the GPC and should
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contain the following:
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Required properties:
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- reg: Must contain the DOMAIN_INDEX of this power domain
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The following DOMAIN_INDEX values are valid for i.MX6Q:
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ARM_DOMAIN 0
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PU_DOMAIN 1
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The following additional DOMAIN_INDEX value is valid for i.MX6SL:
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DISPLAY_DOMAIN 2
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- #power-domain-cells: Should be 0
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|
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Optional properties:
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- clocks: a number of phandles to clocks that need to be enabled during domain
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power-up sequencing to ensure reset propagation into devices located inside
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this power domain
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- power-supply: a phandle to the regulator powering this domain
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Example:
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@@ -25,14 +45,30 @@ Example:
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reg = <0x020dc000 0x4000>;
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interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
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<0 90 IRQ_TYPE_LEVEL_HIGH>;
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pu-supply = <®_pu>;
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clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
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<&clks IMX6QDL_CLK_GPU3D_SHADER>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>,
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<&clks IMX6QDL_CLK_GPU2D_AXI>,
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<&clks IMX6QDL_CLK_OPENVG_AXI>,
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<&clks IMX6QDL_CLK_VPU_AXI>;
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#power-domain-cells = <1>;
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clocks = <&clks IMX6QDL_CLK_IPG>;
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clock-names = "ipg";
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pgc {
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#address-cells = <1>;
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#size-cells = <0>;
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|
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power-domain@0 {
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reg = <0>;
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#power-domain-cells = <0>;
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};
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pd_pu: power-domain@1 {
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reg = <1>;
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#power-domain-cells = <0>;
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power-supply = <®_pu>;
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clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
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<&clks IMX6QDL_CLK_GPU3D_SHADER>,
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<&clks IMX6QDL_CLK_GPU2D_CORE>,
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<&clks IMX6QDL_CLK_GPU2D_AXI>,
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<&clks IMX6QDL_CLK_OPENVG_AXI>,
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<&clks IMX6QDL_CLK_VPU_AXI>;
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||||
};
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};
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};
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@@ -40,20 +76,13 @@ Specifying power domain for IP modules
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======================================
|
||||
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IP cores belonging to a power domain should contain a 'power-domains' property
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that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying
|
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the power domain the device belongs to.
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||||
that is a phandle pointing to the power domain the device belongs to.
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||||
|
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Example of a device that is part of the PU power domain:
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vpu: vpu@02040000 {
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reg = <0x02040000 0x3c000>;
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/* ... */
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power-domains = <&gpc 1>;
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power-domains = <&pd_pu>;
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/* ... */
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};
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The following DOMAIN_INDEX values are valid for i.MX6Q:
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ARM_DOMAIN 0
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PU_DOMAIN 1
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The following additional DOMAIN_INDEX value is valid for i.MX6SL:
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DISPLAY_DOMAIN 2
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|
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@@ -0,0 +1,71 @@
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Freescale i.MX General Power Controller v2
|
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==========================================
|
||||
|
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The i.MX7S/D General Power Control (GPC) block contains Power Gating
|
||||
Control (PGC) for various power domains.
|
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|
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Required properties:
|
||||
|
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- compatible: Should be "fsl,imx7d-gpc"
|
||||
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
|
||||
- interrupts: Should contain GPC interrupt request 1
|
||||
|
||||
Power domains contained within GPC node are generic power domain
|
||||
providers, documented in
|
||||
Documentation/devicetree/bindings/power/power_domain.txt, which are
|
||||
described as subnodes of the power gating controller 'pgc' node,
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which, in turn, is expected to contain the following:
|
||||
|
||||
Required properties:
|
||||
|
||||
- reg: Power domain index. Valid values are defined in
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include/dt-bindings/power/imx7-power.h
|
||||
|
||||
- #power-domain-cells: Should be 0
|
||||
|
||||
Optional properties:
|
||||
|
||||
- power-supply: Power supply used to power the domain
|
||||
|
||||
Example:
|
||||
|
||||
gpc: gpc@303a0000 {
|
||||
compatible = "fsl,imx7d-gpc";
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||||
reg = <0x303a0000 0x1000>;
|
||||
interrupt-controller;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
|
||||
|
||||
pgc {
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#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pgc_pcie_phy: power-domain@3 {
|
||||
#power-domain-cells = <0>;
|
||||
|
||||
reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
|
||||
power-supply = <®_1p0d>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Specifying power domain for IP modules
|
||||
======================================
|
||||
|
||||
IP cores belonging to a power domain should contain a 'power-domains'
|
||||
property that is a phandle for PGC node representing the domain.
|
||||
|
||||
Example of a device that is part of the PCIE_PHY power domain:
|
||||
|
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pcie: pcie@33800000 {
|
||||
reg = <0x33800000 0x4000>,
|
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<0x4ff00000 0x80000>;
|
||||
/* ... */
|
||||
power-domains = <&pgc_pcie_phy>;
|
||||
/* ... */
|
||||
};
|
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@@ -0,0 +1,47 @@
|
||||
Freescale i.MX7 System Reset Controller
|
||||
======================================
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,imx7-src", "syscon"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain SRC interrupt
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
example:
|
||||
|
||||
src: reset-controller@30390000 {
|
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compatible = "fsl,imx7d-src", "syscon";
|
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reg = <0x30390000 0x2000>;
|
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
|
||||
The system reset controller can be used to reset various set of
|
||||
peripherals. Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
Example:
|
||||
|
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pcie: pcie@33800000 {
|
||||
|
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...
|
||||
|
||||
resets = <&src IMX7_RESET_PCIEPHY>,
|
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<&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
|
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reset-names = "pciephy", "apps";
|
||||
|
||||
...
|
||||
};
|
||||
|
||||
|
||||
For list of all valid reset indicies see
|
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<dt-bindings/reset/imx7-reset.h>
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||||
@@ -0,0 +1,57 @@
|
||||
Texas Instruments TI-SCI Generic Power Domain
|
||||
---------------------------------------------
|
||||
|
||||
Some TI SoCs contain a system controller (like the PMMC, etc...) that is
|
||||
responsible for controlling the state of the IPs that are present.
|
||||
Communication between the host processor running an OS and the system
|
||||
controller happens through a protocol known as TI-SCI [1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
|
||||
PM Domain Node
|
||||
==============
|
||||
The PM domain node represents the global PM domain managed by the PMMC, which
|
||||
in this case is the implementation as documented by the generic PM domain
|
||||
bindings in Documentation/devicetree/bindings/power/power_domain.txt. Because
|
||||
this relies on the TI SCI protocol to communicate with the PMMC it must be a
|
||||
child of the pmmc node.
|
||||
|
||||
Required Properties:
|
||||
--------------------
|
||||
- compatible: should be "ti,sci-pm-domain"
|
||||
- #power-domain-cells: Must be 1 so that an id can be provided in each
|
||||
device node.
|
||||
|
||||
Example (K2G):
|
||||
-------------
|
||||
pmmc: pmmc {
|
||||
compatible = "ti,k2g-sci";
|
||||
...
|
||||
|
||||
k2g_pds: power-controller {
|
||||
compatible = "ti,sci-pm-domain";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
PM Domain Consumers
|
||||
===================
|
||||
Hardware blocks belonging to a PM domain should contain a "power-domains"
|
||||
property that is a phandle pointing to the corresponding PM domain node
|
||||
along with an index representing the device id to be passed to the PMMC
|
||||
for device control.
|
||||
|
||||
Required Properties:
|
||||
--------------------
|
||||
- power-domains: phandle pointing to the corresponding PM domain node
|
||||
and an ID representing the device.
|
||||
|
||||
See dt-bindings/genpd/k2g.h for the list of valid identifiers for k2g.
|
||||
|
||||
Example (K2G):
|
||||
--------------------
|
||||
uart0: serial@02530c00 {
|
||||
compatible = "ns16550a";
|
||||
...
|
||||
power-domains = <&k2g_pds K2G_DEV_UART0>;
|
||||
};
|
||||
@@ -653,7 +653,9 @@ M: Thor Thayer <thor.thayer@linux.intel.com>
|
||||
S: Maintained
|
||||
F: drivers/gpio/gpio-altera-a10sr.c
|
||||
F: drivers/mfd/altera-a10sr.c
|
||||
F: drivers/reset/reset-a10sr.c
|
||||
F: include/linux/mfd/altera-a10sr.h
|
||||
F: include/dt-bindings/reset/altr,rst-mgr-a10sr.h
|
||||
|
||||
ALTERA TRIPLE SPEED ETHERNET DRIVER
|
||||
M: Vince Bridgers <vbridger@opensource.altera.com>
|
||||
@@ -1282,6 +1284,7 @@ F: arch/arm/mach-mxs/
|
||||
F: arch/arm/boot/dts/imx*
|
||||
F: arch/arm/configs/imx*_defconfig
|
||||
F: drivers/clk/imx/
|
||||
F: drivers/soc/imx/
|
||||
F: include/soc/imx/
|
||||
|
||||
ARM/FREESCALE VYBRID ARM ARCHITECTURE
|
||||
@@ -12604,6 +12607,9 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
|
||||
F: drivers/firmware/ti_sci*
|
||||
F: include/linux/soc/ti/ti_sci_protocol.h
|
||||
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
|
||||
F: include/dt-bindings/genpd/k2g.h
|
||||
F: drivers/soc/ti/ti_sci_pm_domains.c
|
||||
|
||||
THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
|
||||
M: Hans Verkuil <hverkuil@xs4all.nl>
|
||||
|
||||
@@ -1,6 +1,3 @@
|
||||
config ICST
|
||||
bool
|
||||
|
||||
config SA1111
|
||||
bool
|
||||
select DMABOUNCE if !ARCH_PXA
|
||||
|
||||
@@ -4,7 +4,6 @@
|
||||
|
||||
obj-y += firmware.o
|
||||
|
||||
obj-$(CONFIG_ICST) += icst.o
|
||||
obj-$(CONFIG_SA1111) += sa1111.o
|
||||
obj-$(CONFIG_DMABOUNCE) += dmabounce.o
|
||||
obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
|
||||
|
||||
@@ -10,26 +10,17 @@
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/irqchip/arm-gic.h>
|
||||
#include "common.h"
|
||||
#include "hardware.h"
|
||||
|
||||
#define GPC_CNTR 0x000
|
||||
#define GPC_IMR1 0x008
|
||||
#define GPC_PGC_GPU_PDN 0x260
|
||||
#define GPC_PGC_GPU_PUPSCR 0x264
|
||||
#define GPC_PGC_GPU_PDNSCR 0x268
|
||||
#define GPC_PGC_CPU_PDN 0x2a0
|
||||
#define GPC_PGC_CPU_PUPSCR 0x2a4
|
||||
#define GPC_PGC_CPU_PDNSCR 0x2a8
|
||||
@@ -39,18 +30,6 @@
|
||||
#define IMR_NUM 4
|
||||
#define GPC_MAX_IRQS (IMR_NUM * 32)
|
||||
|
||||
#define GPU_VPU_PUP_REQ BIT(1)
|
||||
#define GPU_VPU_PDN_REQ BIT(0)
|
||||
|
||||
#define GPC_CLK_MAX 6
|
||||
|
||||
struct pu_domain {
|
||||
struct generic_pm_domain base;
|
||||
struct regulator *reg;
|
||||
struct clk *clk[GPC_CLK_MAX];
|
||||
int num_clks;
|
||||
};
|
||||
|
||||
static void __iomem *gpc_base;
|
||||
static u32 gpc_wake_irqs[IMR_NUM];
|
||||
static u32 gpc_saved_imrs[IMR_NUM];
|
||||
@@ -296,199 +275,3 @@ void __init imx_gpc_check_dt(void)
|
||||
gpc_base = of_iomap(np, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
int iso, iso2sw;
|
||||
u32 val;
|
||||
|
||||
/* Read ISO and ISO2SW power down delays */
|
||||
val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
|
||||
iso = val & 0x3f;
|
||||
iso2sw = (val >> 8) & 0x3f;
|
||||
|
||||
/* Gate off PU domain when GPU/VPU when powered down */
|
||||
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
|
||||
|
||||
/* Request GPC to power down GPU/VPU */
|
||||
val = readl_relaxed(gpc_base + GPC_CNTR);
|
||||
val |= GPU_VPU_PDN_REQ;
|
||||
writel_relaxed(val, gpc_base + GPC_CNTR);
|
||||
|
||||
/* Wait ISO + ISO2SW IPG clock cycles */
|
||||
ndelay((iso + iso2sw) * 1000 / 66);
|
||||
}
|
||||
|
||||
static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
|
||||
|
||||
_imx6q_pm_pu_power_off(genpd);
|
||||
|
||||
if (pu->reg)
|
||||
regulator_disable(pu->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
|
||||
{
|
||||
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
|
||||
int i, ret, sw, sw2iso;
|
||||
u32 val;
|
||||
|
||||
if (pu->reg)
|
||||
ret = regulator_enable(pu->reg);
|
||||
if (pu->reg && ret) {
|
||||
pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Enable reset clocks for all devices in the PU domain */
|
||||
for (i = 0; i < pu->num_clks; i++)
|
||||
clk_prepare_enable(pu->clk[i]);
|
||||
|
||||
/* Gate off PU domain when GPU/VPU when powered down */
|
||||
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
|
||||
|
||||
/* Read ISO and ISO2SW power down delays */
|
||||
val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
|
||||
sw = val & 0x3f;
|
||||
sw2iso = (val >> 8) & 0x3f;
|
||||
|
||||
/* Request GPC to power up GPU/VPU */
|
||||
val = readl_relaxed(gpc_base + GPC_CNTR);
|
||||
val |= GPU_VPU_PUP_REQ;
|
||||
writel_relaxed(val, gpc_base + GPC_CNTR);
|
||||
|
||||
/* Wait ISO + ISO2SW IPG clock cycles */
|
||||
ndelay((sw + sw2iso) * 1000 / 66);
|
||||
|
||||
/* Disable reset clocks for all devices in the PU domain */
|
||||
for (i = 0; i < pu->num_clks; i++)
|
||||
clk_disable_unprepare(pu->clk[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct generic_pm_domain imx6q_arm_domain = {
|
||||
.name = "ARM",
|
||||
};
|
||||
|
||||
static struct pu_domain imx6q_pu_domain = {
|
||||
.base = {
|
||||
.name = "PU",
|
||||
.power_off = imx6q_pm_pu_power_off,
|
||||
.power_on = imx6q_pm_pu_power_on,
|
||||
},
|
||||
};
|
||||
|
||||
static struct generic_pm_domain imx6sl_display_domain = {
|
||||
.name = "DISPLAY",
|
||||
};
|
||||
|
||||
static struct generic_pm_domain *imx_gpc_domains[] = {
|
||||
&imx6q_arm_domain,
|
||||
&imx6q_pu_domain.base,
|
||||
&imx6sl_display_domain,
|
||||
};
|
||||
|
||||
static struct genpd_onecell_data imx_gpc_onecell_data = {
|
||||
.domains = imx_gpc_domains,
|
||||
.num_domains = ARRAY_SIZE(imx_gpc_domains),
|
||||
};
|
||||
|
||||
static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
|
||||
{
|
||||
struct clk *clk;
|
||||
int i, ret;
|
||||
|
||||
imx6q_pu_domain.reg = pu_reg;
|
||||
|
||||
for (i = 0; ; i++) {
|
||||
clk = of_clk_get(dev->of_node, i);
|
||||
if (IS_ERR(clk))
|
||||
break;
|
||||
if (i >= GPC_CLK_MAX) {
|
||||
dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
|
||||
goto clk_err;
|
||||
}
|
||||
imx6q_pu_domain.clk[i] = clk;
|
||||
}
|
||||
imx6q_pu_domain.num_clks = i;
|
||||
|
||||
/* Enable power always in case bootloader disabled it. */
|
||||
imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
|
||||
return 0;
|
||||
|
||||
imx6q_pu_domain.base.states = devm_kzalloc(dev,
|
||||
sizeof(*imx6q_pu_domain.base.states),
|
||||
GFP_KERNEL);
|
||||
if (!imx6q_pu_domain.base.states)
|
||||
return -ENOMEM;
|
||||
|
||||
imx6q_pu_domain.base.states[0].power_off_latency_ns = 25000;
|
||||
imx6q_pu_domain.base.states[0].power_on_latency_ns = 2000000;
|
||||
imx6q_pu_domain.base.state_count = 1;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
|
||||
pm_genpd_init(imx_gpc_domains[i], NULL, false);
|
||||
|
||||
ret = of_genpd_add_provider_onecell(dev->of_node,
|
||||
&imx_gpc_onecell_data);
|
||||
if (ret)
|
||||
goto power_off;
|
||||
|
||||
return 0;
|
||||
|
||||
power_off:
|
||||
imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
|
||||
clk_err:
|
||||
while (i--)
|
||||
clk_put(imx6q_pu_domain.clk[i]);
|
||||
imx6q_pu_domain.reg = NULL;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int imx_gpc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regulator *pu_reg;
|
||||
int ret;
|
||||
|
||||
/* bail out if DT too old and doesn't provide the necessary info */
|
||||
if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
|
||||
return 0;
|
||||
|
||||
pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
|
||||
if (PTR_ERR(pu_reg) == -ENODEV)
|
||||
pu_reg = NULL;
|
||||
if (IS_ERR(pu_reg)) {
|
||||
ret = PTR_ERR(pu_reg);
|
||||
dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return imx_gpc_genpd_init(&pdev->dev, pu_reg);
|
||||
}
|
||||
|
||||
static const struct of_device_id imx_gpc_dt_ids[] = {
|
||||
{ .compatible = "fsl,imx6q-gpc" },
|
||||
{ .compatible = "fsl,imx6sl-gpc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver imx_gpc_driver = {
|
||||
.driver = {
|
||||
.name = "imx-gpc",
|
||||
.of_match_table = imx_gpc_dt_ids,
|
||||
},
|
||||
.probe = imx_gpc_probe,
|
||||
};
|
||||
|
||||
static int __init imx_pgc_init(void)
|
||||
{
|
||||
return platform_driver_register(&imx_gpc_driver);
|
||||
}
|
||||
subsys_initcall(imx_pgc_init);
|
||||
|
||||
@@ -10,6 +10,7 @@ config ARCH_KEYSTONE
|
||||
select ARCH_SUPPORTS_BIG_ENDIAN
|
||||
select ZONE_DMA if ARM_LPAE
|
||||
select PINCTRL
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
help
|
||||
Support for boards based on the Texas Instruments Keystone family of
|
||||
SoCs.
|
||||
|
||||
@@ -32,7 +32,9 @@ static struct pm_clk_notifier_block platform_domain_notifier = {
|
||||
};
|
||||
|
||||
static const struct of_device_id of_keystone_table[] = {
|
||||
{.compatible = "ti,keystone"},
|
||||
{.compatible = "ti,k2hk"},
|
||||
{.compatible = "ti,k2e"},
|
||||
{.compatible = "ti,k2l"},
|
||||
{ /* end of list */ },
|
||||
};
|
||||
|
||||
|
||||
@@ -2,7 +2,6 @@ asflags-y += -march=armv7-a
|
||||
|
||||
obj-y += io.o
|
||||
obj-y += irq.o
|
||||
obj-y += flowctrl.o
|
||||
obj-y += pm.o
|
||||
obj-y += reset.o
|
||||
obj-y += reset-handler.o
|
||||
|
||||
@@ -26,12 +26,13 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <soc/tegra/flowctrl.h>
|
||||
|
||||
#include <asm/cpuidle.h>
|
||||
#include <asm/smp_plat.h>
|
||||
#include <asm/suspend.h>
|
||||
|
||||
#include "cpuidle.h"
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
#include "irq.h"
|
||||
#include "pm.h"
|
||||
|
||||
@@ -21,6 +21,7 @@
|
||||
#include <linux/jiffies.h>
|
||||
#include <linux/smp.h>
|
||||
|
||||
#include <soc/tegra/flowctrl.h>
|
||||
#include <soc/tegra/fuse.h>
|
||||
#include <soc/tegra/pmc.h>
|
||||
|
||||
@@ -30,7 +31,6 @@
|
||||
#include <asm/smp_scu.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
#include "reset.h"
|
||||
|
||||
|
||||
@@ -27,6 +27,7 @@
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/suspend.h>
|
||||
|
||||
#include <soc/tegra/flowctrl.h>
|
||||
#include <soc/tegra/fuse.h>
|
||||
#include <soc/tegra/pm.h>
|
||||
#include <soc/tegra/pmc.h>
|
||||
@@ -38,7 +39,6 @@
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
#include "pm.h"
|
||||
#include "reset.h"
|
||||
|
||||
@@ -17,12 +17,12 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <soc/tegra/flowctrl.h>
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
#include "reset.h"
|
||||
#include "sleep.h"
|
||||
|
||||
@@ -20,6 +20,8 @@
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <soc/tegra/flowctrl.h>
|
||||
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/proc-fns.h>
|
||||
#include <asm/cp15.h>
|
||||
@@ -27,7 +29,6 @@
|
||||
|
||||
#include "irammap.h"
|
||||
#include "sleep.h"
|
||||
#include "flowctrl.h"
|
||||
|
||||
#define EMC_CFG 0xc
|
||||
#define EMC_ADR_CFG 0x10
|
||||
|
||||
@@ -16,13 +16,13 @@
|
||||
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#include <soc/tegra/flowctrl.h>
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
#include <asm/asm-offsets.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
#include "flowctrl.h"
|
||||
#include "irammap.h"
|
||||
#include "sleep.h"
|
||||
|
||||
|
||||
@@ -30,8 +30,6 @@
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include "iomap.h"
|
||||
|
||||
#include "flowctrl.h"
|
||||
#include "sleep.h"
|
||||
|
||||
#define CLK_RESET_CCLK_BURST 0x20
|
||||
|
||||
@@ -48,7 +48,6 @@
|
||||
#include "board.h"
|
||||
#include "common.h"
|
||||
#include "cpuidle.h"
|
||||
#include "flowctrl.h"
|
||||
#include "iomap.h"
|
||||
#include "irq.h"
|
||||
#include "pm.h"
|
||||
@@ -75,7 +74,6 @@ static void __init tegra_init_early(void)
|
||||
{
|
||||
of_register_trusted_foundations();
|
||||
tegra_cpu_reset_handler_init();
|
||||
tegra_flowctrl_init();
|
||||
}
|
||||
|
||||
static void __init tegra_dt_init_irq(void)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user