mirror of
https://github.com/linux-msm/debugcc.git
synced 2026-02-25 13:12:32 -08:00
cf5664f7c4
Enforcing a primary+leaf configuration does not walk for all the cases. Some clocks (msm8996 CPU) have more muxes to be powered on. Other (MCCC) do not require GCC at all. Make clock measurement more versatile by reworking GCC + optional leaf into a chain of muxes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
263 lines
9.2 KiB
C
263 lines
9.2 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/* Copyright (c) 2022, Linaro Limited */
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#include <sys/mman.h>
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#include <err.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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static struct gcc_mux gcc = {
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.mux = {
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.phys = 0x100000,
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.size = 0xb0000,
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.measure = measure_gcc,
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.enable_reg = 0x62000,
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.enable_mask = BIT(16),
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.mux_reg = 0x62000,
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.mux_mask = 0x3ff,
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.div_reg = 0x62000,
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.div_mask = 0xf,
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.div_val = 4,
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},
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.xo_div4_reg = 0x43008,
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.debug_ctl_reg = 0x62004,
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.debug_status_reg = 0x62008,
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};
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static struct debug_mux mm_cc = {
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.phys = 0xc8c0000,
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.size = 0x40000,
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.block_name = "mm",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0x22,
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.enable_reg = 0x900,
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.enable_mask = BIT(16),
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.mux_reg = 0x900,
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.mux_mask = 0x3ff,
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};
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static struct debug_mux gpu_cc = {
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.phys = 0x5065000,
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.size = 0x9000,
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.block_name = "gpu",
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.measure = measure_leaf,
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.parent = &gcc.mux,
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.parent_mux_val = 0x13d,
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.enable_reg = 0x120,
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.enable_mask = BIT(16),
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.mux_reg = 0x120,
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.mux_mask = 0x3ff,
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};
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static struct measure_clk msm8998_clocks[] = {
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// { "debug_cpu_clk", &gcc.mux, 0xc0 },
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{ "snoc_clk", &gcc.mux, 0x0 },
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{ "cnoc_clk", &gcc.mux, 0xe },
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{ "bimc_clk", &gcc.mux, 0x14e },
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{ "gcc_mmss_sys_noc_axi_clk", &gcc.mux, 0x1f },
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{ "gcc_mmss_noc_cfg_ahb_clk", &gcc.mux, 0x20 },
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{ "gcc_usb30_master_clk", &gcc.mux, 0x3e },
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{ "gcc_usb30_sleep_clk", &gcc.mux, 0x3f },
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{ "gcc_usb30_mock_utmi_clk", &gcc.mux, 0x40 },
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{ "gcc_usb3_phy_aux_clk", &gcc.mux, 0x41 },
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{ "gcc_usb3_phy_pipe_clk", &gcc.mux, 0x42 },
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{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x46 },
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{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x47 },
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{ "gcc_sdcc4_apps_clk", &gcc.mux, 0x48 },
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{ "gcc_sdcc4_ahb_clk", &gcc.mux, 0x49 },
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{ "gcc_blsp1_ahb_clk", &gcc.mux, 0x4a },
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{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 0x4c },
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{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 0x4d },
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{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 0x4e },
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{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 0x50 },
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{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 0x51 },
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{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 0x52 },
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{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 0x54 },
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{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 0x55 },
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{ "gcc_blsp1_uart3_apps_clk", &gcc.mux, 0x56 },
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{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 0x58 },
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{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 0x59 },
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{ "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 0x5a },
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{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 0x5b },
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{ "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 0x5c },
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{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 0x5d },
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{ "gcc_blsp2_ahb_clk", &gcc.mux, 0x5e },
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{ "gcc_blsp2_qup1_spi_apps_clk", &gcc.mux, 0x60 },
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{ "gcc_blsp2_qup1_i2c_apps_clk", &gcc.mux, 0x61 },
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{ "gcc_blsp2_uart1_apps_clk", &gcc.mux, 0x62 },
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{ "gcc_blsp2_qup2_spi_apps_clk", &gcc.mux, 0x64 },
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{ "gcc_blsp2_qup2_i2c_apps_clk", &gcc.mux, 0x65 },
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{ "gcc_blsp2_uart2_apps_clk", &gcc.mux, 0x66 },
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{ "gcc_blsp2_qup3_spi_apps_clk", &gcc.mux, 0x68 },
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{ "gcc_blsp2_qup3_i2c_apps_clk", &gcc.mux, 0x69 },
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{ "gcc_blsp2_uart3_apps_clk", &gcc.mux, 0x6a },
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{ "gcc_blsp2_qup4_spi_apps_clk", &gcc.mux, 0x6c },
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{ "gcc_blsp2_qup4_i2c_apps_clk", &gcc.mux, 0x6d },
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{ "gcc_blsp2_qup5_spi_apps_clk", &gcc.mux, 0x6e },
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{ "gcc_blsp2_qup5_i2c_apps_clk", &gcc.mux, 0x6f },
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{ "gcc_blsp2_qup6_spi_apps_clk", &gcc.mux, 0x70 },
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{ "gcc_blsp2_qup6_i2c_apps_clk", &gcc.mux, 0x71 },
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{ "gcc_pdm_ahb_clk", &gcc.mux, 0x72 },
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{ "gcc_pdm2_clk", &gcc.mux, 0x74},
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{ "gcc_prng_ahb_clk", &gcc.mux, 0x75 },
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{ "gcc_tsif_ahb_clk", &gcc.mux, 0x76 },
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{ "gcc_tsif_ref_clk", &gcc.mux, 0x77 },
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{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x7a },
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{ "ce1_clk", &gcc.mux, 0x97 },
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{ "gcc_ce1_axi_m_clk", &gcc.mux, 0x98 },
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{ "gcc_ce1_ahb_m_clk", &gcc.mux, 0x99 },
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{ "measure_only_bimc_hmss_axi_clk", &gcc.mux, 0xbb },
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{ "gcc_bimc_gfx_clk", &gcc.mux, 0xac },
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{ "gcc_hmss_rbcpr_clk", &gcc.mux, 0xbc },
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{ "gcc_gp1_clk", &gcc.mux, 0xdf },
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{ "gcc_gp2_clk", &gcc.mux, 0xe0 },
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{ "gcc_gp3_clk", &gcc.mux, 0xe1 },
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{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0xe2 },
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{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0xe3 },
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{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0xe4 },
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{ "gcc_pcie_0_aux_clk", &gcc.mux, 0xe5 },
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{ "gcc_pcie_0_pipe_clk", &gcc.mux, 0xe6 },
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{ "gcc_pcie_phy_aux_clk", &gcc.mux, 0xe8 },
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{ "gcc_ufs_axi_clk", &gcc.mux, 0xea },
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{ "gcc_ufs_ahb_clk", &gcc.mux, 0xeb },
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{ "gcc_ufs_tx_symbol_0_clk", &gcc.mux, 0xec },
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{ "gcc_ufs_rx_symbol_0_clk", &gcc.mux, 0xed },
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{ "gcc_ufs_rx_symbol_1_clk", &gcc.mux, 0x162 },
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{ "gcc_ufs_unipro_core_clk", &gcc.mux, 0xf0 },
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{ "gcc_ufs_ice_core_clk", &gcc.mux, 0xf1 },
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{ "gcc_dcc_ahb_clk", &gcc.mux, 0x119 },
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{ "ipa_clk", &gcc.mux, 0x11b },
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{ "gcc_mss_cfg_ahb_clk", &gcc.mux, 0x11f },
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{ "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 0x124 },
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{ "gcc_mss_mnoc_bimc_axi_clk", &gcc.mux, 0x120 },
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{ "gcc_mss_snoc_axi_clk", &gcc.mux, 0x123 },
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{ "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x13b },
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{ "gcc_gpu_bimc_gfx_clk", &gcc.mux, 0x13f },
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{ "gcc_qspi_ahb_clk", &gcc.mux, 0x156 },
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{ "gcc_qspi_ref_clk", &gcc.mux, 0x157 },
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{ "mmss_mnoc_ahb_clk", &mm_cc, 0x1 },
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{ "mmss_misc_ahb_clk", &mm_cc, 0x3 },
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{ "mmss_vmem_maxi_clk", &mm_cc, 0x9 },
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{ "mmss_vmem_ahb_clk", &mm_cc, 0xa },
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{ "mmss_bimc_smmu_ahb_clk", &mm_cc, 0xc },
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{ "mmss_bimc_smmu_axi_clk", &mm_cc, 0xd },
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{ "mmss_video_core_clk", &mm_cc, 0xe },
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{ "mmss_video_axi_clk", &mm_cc, 0xf },
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{ "mmss_video_maxi_clk", &mm_cc, 0x10 },
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{ "mmss_video_ahb_clk", &mm_cc, 0x11 },
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{ "mmss_mdss_rot_clk", &mm_cc, 0x12 },
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{ "mmss_snoc_dvm_axi_clk", &mm_cc, 0x13 },
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{ "mmss_mdss_mdp_clk", &mm_cc, 0x14 },
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{ "mmss_mdss_mdp_lut_clk", &mm_cc, 0x15 },
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{ "mmss_mdss_pclk0_clk", &mm_cc, 0x16 },
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{ "mmss_mdss_pclk1_clk", &mm_cc, 0x17 },
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{ "mmss_mdss_extpclk_clk", &mm_cc, 0x18 },
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{ "mmss_video_subcore0_clk", &mm_cc, 0x1a },
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{ "mmss_video_subcore1_clk", &mm_cc, 0x1b },
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{ "mmss_mdss_vsync_clk", &mm_cc, 0x1c },
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{ "mmss_mdss_hdmi_clk", &mm_cc, 0x1d },
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{ "mmss_mdss_byte0_clk", &mm_cc, 0x1e },
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{ "mmss_mdss_byte1_clk", &mm_cc, 0x1f },
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{ "mmss_mdss_esc0_clk", &mm_cc, 0x20 },
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{ "mmss_mdss_esc1_clk", &mm_cc, 0x21 },
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{ "mmss_mdss_ahb_clk", &mm_cc, 0x22 },
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{ "mmss_mdss_hdmi_dp_ahb_clk", &mm_cc, 0x23 },
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{ "mmss_mdss_axi_clk", &mm_cc, 0x24 },
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{ "mmss_camss_top_ahb_clk", &mm_cc, 0x25 },
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{ "mmss_camss_micro_ahb_clk", &mm_cc, 0x26 },
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{ "mmss_camss_gp0_clk", &mm_cc, 0x27 },
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{ "mmss_camss_gp1_clk", &mm_cc, 0x28 },
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{ "mmss_camss_mclk0_clk", &mm_cc, 0x29 },
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{ "mmss_camss_mclk1_clk", &mm_cc, 0x2a },
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{ "mmss_camss_mclk2_clk", &mm_cc, 0x2b },
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{ "mmss_camss_mclk3_clk", &mm_cc, 0x2c },
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{ "mmss_camss_cci_clk", &mm_cc, 0x2d },
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{ "mmss_camss_cci_ahb_clk", &mm_cc, 0x2e },
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{ "mmss_camss_csi0phytimer_clk", &mm_cc, 0x2f },
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{ "mmss_camss_csi1phytimer_clk", &mm_cc, 0x30 },
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{ "mmss_camss_csi2phytimer_clk", &mm_cc, 0x31 },
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{ "mmss_camss_jpeg0_clk", &mm_cc, 0x32 },
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{ "mmss_camss_ispif_ahb_clk", &mm_cc, 0x33 },
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{ "mmss_camss_jpeg_ahb_clk", &mm_cc, 0x35 },
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{ "mmss_camss_jpeg_axi_clk", &mm_cc, 0x36 },
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{ "mmss_camss_ahb_clk", &mm_cc, 0x37 },
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{ "mmss_camss_vfe0_clk", &mm_cc, 0x38 },
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{ "mmss_camss_vfe1_clk", &mm_cc, 0x39 },
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{ "mmss_camss_cpp_clk", &mm_cc, 0x3a },
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{ "mmss_camss_cpp_ahb_clk", &mm_cc, 0x3b },
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{ "mmss_camss_csi_vfe0_clk", &mm_cc, 0x3f },
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{ "mmss_camss_csi_vfe1_clk", &mm_cc, 0x40 },
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{ "mmss_camss_csi0_clk", &mm_cc, 0x41 },
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{ "mmss_camss_csi0_ahb_clk", &mm_cc, 0x42 },
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{ "mmss_camss_csiphy0_clk", &mm_cc, 0x43 },
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{ "mmss_camss_csi0rdi_clk", &mm_cc, 0x44 },
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{ "mmss_camss_csi0pix_clk", &mm_cc, 0x45 },
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{ "mmss_camss_csi1_clk", &mm_cc, 0x46 },
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{ "mmss_camss_csi1_ahb_clk", &mm_cc, 0x47 },
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{ "mmss_camss_csi1rdi_clk", &mm_cc, 0x49 },
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{ "mmss_camss_csi1pix_clk", &mm_cc, 0x4a },
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{ "mmss_camss_csi2_clk", &mm_cc, 0x4b },
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{ "mmss_camss_csi2_ahb_clk", &mm_cc, 0x4c },
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{ "mmss_camss_csi2rdi_clk", &mm_cc, 0x4e },
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{ "mmss_camss_csi2pix_clk", &mm_cc, 0x4f },
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{ "mmss_camss_csi3_clk", &mm_cc, 0x50 },
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{ "mmss_camss_csi3_ahb_clk", &mm_cc, 0x51 },
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{ "mmss_camss_csi3rdi_clk", &mm_cc, 0x53 },
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{ "mmss_camss_csi3pix_clk", &mm_cc, 0x54 },
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{ "mmss_mnoc_maxi_clk", &mm_cc, 0x70 },
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{ "mmss_camss_vfe0_stream_clk", &mm_cc, 0x71 },
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{ "mmss_camss_vfe1_stream_clk", &mm_cc, 0x72 },
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{ "mmss_camss_cpp_vbif_ahb_clk", &mm_cc, 0x73 },
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{ "mmss_misc_cxo_clk", &mm_cc, 0x77 },
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{ "mmss_camss_cpp_axi_clk", &mm_cc, 0x7a },
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{ "mmss_camss_csiphy1_clk", &mm_cc, 0x85 },
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{ "mmss_camss_vfe0_ahb_clk", &mm_cc, 0x86 },
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{ "mmss_camss_vfe1_ahb_clk", &mm_cc, 0x87 },
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{ "mmss_camss_csiphy2_clk", &mm_cc, 0x88 },
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{ "mmss_fd_core_clk", &mm_cc, 0x89 },
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{ "mmss_fd_core_uar_clk", &mm_cc, 0x8a },
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{ "mmss_fd_ahb_clk", &mm_cc, 0x8c },
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{ "mmss_camss_cphy_csid0_clk", &mm_cc, 0x8d },
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{ "mmss_camss_cphy_csid1_clk", &mm_cc, 0x8e },
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{ "mmss_camss_cphy_csid2_clk", &mm_cc, 0x8f },
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{ "mmss_camss_cphy_csid3_clk", &mm_cc, 0x90 },
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{ "mmss_mdss_dp_link_clk", &mm_cc, 0x98 },
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{ "mmss_mdss_dp_link_intf_clk", &mm_cc, 0x99 },
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{ "mmss_mdss_dp_crypto_clk", &mm_cc, 0x9a },
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{ "mmss_mdss_dp_pixel_clk", &mm_cc, 0x9b },
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{ "mmss_mdss_dp_aux_clk", &mm_cc, 0x9c },
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{ "mmss_mdss_dp_gtc_clk", &mm_cc, 0x9d },
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{ "mmss_mdss_byte0_intf_clk", &mm_cc, 0xad },
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{ "mmss_mdss_byte1_intf_clk", &mm_cc, 0xae },
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{ "gpucc_rbcpr_clk", &gpu_cc, 0x3 },
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{ "gpucc_rbbmtimer_clk", &gpu_cc, 0x5 },
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{ "gpucc_gfx3d_isense_clk", &gpu_cc, 0xa },
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{}
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};
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struct debugcc_platform msm8998_debugcc = {
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"msm8998",
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msm8998_clocks,
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};
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