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debugcc: Rework clock muxes into a chain structure

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Enforcing a primary+leaf configuration does not walk for all the cases.
Some clocks (msm8996 CPU) have more muxes to be powered on. Other (MCCC)
do not require GCC at all. Make clock measurement more versatile by
reworking GCC + optional leaf into a chain of muxes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Dmitry Baryshkov
2023-06-16 14:34:24 +03:00
parent 132a037a08
commit cf5664f7c4
18 changed files with 3962 additions and 3728 deletions
Download Patch File Download Diff File Expand all files Collapse all files

131
debugcc.c
View File

@@ -34,6 +34,7 @@
#include <fcntl.h>
#include <getopt.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
@@ -42,33 +43,23 @@
#include "debugcc.h"
static uint32_t readl(void *ptr)
{
return *((volatile uint32_t*)ptr);
}
static void writel(uint32_t val, void *ptr)
{
*((volatile uint32_t*)ptr) = val;
}
static unsigned int measure_ticks(struct debug_mux *gcc, unsigned int ticks)
static unsigned int measure_ticks(struct gcc_mux *gcc, unsigned int ticks)
{
uint32_t val;
writel(ticks, gcc->base + gcc->debug_ctl_reg);
writel(ticks, gcc->mux.base + gcc->debug_ctl_reg);
do {
val = readl(gcc->base + gcc->debug_status_reg);
val = readl(gcc->mux.base + gcc->debug_status_reg);
} while (val & BIT(25));
writel(ticks | BIT(20), gcc->base + gcc->debug_ctl_reg);
writel(ticks | BIT(20), gcc->mux.base + gcc->debug_ctl_reg);
do {
val = readl(gcc->base + gcc->debug_status_reg);
val = readl(gcc->mux.base + gcc->debug_status_reg);
} while (!(val & BIT(25)));
val &= 0x1ffffff;
writel(ticks, gcc->base + gcc->debug_ctl_reg);
writel(ticks, gcc->mux.base + gcc->debug_ctl_reg);
return val;
}
@@ -92,6 +83,9 @@ static void mux_prepare_enable(struct debug_mux *mux, int selector)
}
mux_enable(mux);
if (mux->parent)
mux_prepare_enable(mux->parent, mux->parent_mux_val);
}
void mux_enable(struct debug_mux *mux)
@@ -103,17 +97,14 @@ void mux_enable(struct debug_mux *mux)
val |= mux->enable_mask;
writel(val, mux->base + mux->enable_reg);
}
if (mux->premeasure)
mux->premeasure(mux);
}
void mux_disable(struct debug_mux *mux)
{
uint32_t val;
if (mux->postmeasure)
mux->postmeasure(mux);
if (mux->parent)
mux_disable(mux->parent);
if (mux->enable_mask) {
val = readl(mux->base + mux->enable_reg);
@@ -122,35 +113,21 @@ void mux_disable(struct debug_mux *mux)
}
}
static bool leaf_enabled(struct debug_mux *mux, struct debug_mux *leaf)
{
uint32_t val;
/* If no AHB clock is specified, we assume it's clocked */
if (!leaf || !leaf->ahb_mask)
return true;
val = readl(mux->base + leaf->ahb_reg);
val &= leaf->ahb_mask;
/* CLK_OFF will be set if block is not clocked, so inverse */
return !val;
}
static unsigned long measure_default(const struct measure_clk *clk)
unsigned long measure_gcc(const struct measure_clk *clk,
const struct debug_mux *mux)
{
unsigned long raw_count_short;
unsigned long raw_count_full;
struct debug_mux *gcc = clk->primary;
struct gcc_mux *gcc = container_of(mux, struct gcc_mux, mux);
unsigned long xo_div4;
xo_div4 = readl(gcc->base + gcc->xo_div4_reg);
writel(xo_div4 | 1, gcc->base + gcc->xo_div4_reg);
xo_div4 = readl(mux->base + gcc->xo_div4_reg);
writel(xo_div4 | 1, mux->base + gcc->xo_div4_reg);
raw_count_short = measure_ticks(gcc, 0x1000);
raw_count_full = measure_ticks(gcc, 0x10000);
writel(xo_div4, gcc->base + gcc->xo_div4_reg);
writel(xo_div4, mux->base + gcc->xo_div4_reg);
if (raw_count_full == raw_count_short) {
return 0;
@@ -159,49 +136,49 @@ static unsigned long measure_default(const struct measure_clk *clk)
raw_count_full = ((raw_count_full * 10) + 15) * 4800000;
raw_count_full = raw_count_full / ((0x10000 * 10) + 35);
if (clk->leaf && clk->leaf->div_val)
raw_count_full *= clk->leaf->div_val;
if (clk->primary->div_val)
raw_count_full *= clk->primary->div_val;
if (clk->fixed_div)
raw_count_full *= clk->fixed_div;
if (mux->div_val)
raw_count_full *= mux->div_val;
return raw_count_full;
}
unsigned long measure_mccc(const struct measure_clk *clk)
unsigned long measure_leaf(const struct measure_clk *clk,
const struct debug_mux *mux)
{
unsigned long count;
if (!mux->parent) {
printf("No parent in measure_leaf, mux '%s'\n", mux->block_name ? : "gcc");
return 0;
}
count = mux->parent->measure(clk, mux->parent);
if (mux->div_val)
count *= mux->div_val;
return count;
}
unsigned long measure_mccc(const struct measure_clk *clk,
const struct debug_mux *mux)
{
/* MCCC is always on, just read the rate and return. */
return 1000000000000ULL / readl(clk->leaf->base + clk->leaf_mux);
return 1000000000000ULL / readl(clk->clk_mux->base + clk->mux);
}
static void measure(const struct measure_clk *clk)
{
unsigned long clk_rate;
struct debug_mux *gcc = clk->primary;
if (!leaf_enabled(gcc, clk->leaf)) {
printf("%50s: skipping\n", clk->name);
return;
}
mux_prepare_enable(clk->clk_mux, clk->mux);
if (clk->leaf)
mux_prepare_enable(clk->leaf, clk->leaf_mux);
clk_rate = clk->clk_mux->measure(clk, clk->clk_mux);
mux_prepare_enable(clk->primary, clk->mux);
if (clk->fixed_div)
clk_rate *= clk->fixed_div;
if (clk->leaf && clk->leaf->measure)
clk_rate = clk->leaf->measure(clk);
else
clk_rate = measure_default(clk);
mux_disable(clk->primary);
if (clk->leaf)
mux_disable(clk->leaf);
mux_disable(clk->clk_mux);
if (clk_rate == 0) {
printf("%50s: off\n", clk->name);
@@ -265,8 +242,8 @@ static const struct measure_clk *find_clock(const struct debugcc_platform *platf
static bool clock_from_block(const struct measure_clk *clk, const char *block_name)
{
return !block_name ||
(!clk->leaf && !strcmp(block_name, CORE_CC_BLOCK)) ||
(clk->leaf && clk->leaf->block_name && !strcmp(block_name, clk->leaf->block_name));
(!clk->clk_mux && !strcmp(block_name, CORE_CC_BLOCK)) ||
(clk->clk_mux && clk->clk_mux->block_name && !strcmp(block_name, clk->clk_mux->block_name));
}
static void list_clocks_block(const struct debugcc_platform *platform, const char *block_name)
@@ -277,8 +254,8 @@ static void list_clocks_block(const struct debugcc_platform *platform, const cha
if (!clock_from_block(clk, block_name))
continue;
if (clk->leaf && clk->leaf->block_name)
printf("%-40s %s\n", clk->name, clk->leaf->block_name);
if (clk->clk_mux && clk->clk_mux->block_name)
printf("%-40s %s\n", clk->name, clk->clk_mux->block_name);
else
printf("%s\n", clk->name);
}
@@ -296,7 +273,7 @@ int mmap_mux(int devmem, struct debug_mux *mux)
return -1;
}
return 0;
return mmap_mux(devmem, mux->parent);
}
/**
@@ -312,11 +289,7 @@ static int mmap_hardware(int devmem, const struct debugcc_platform *platform)
int ret;
for (clk = platform->clocks; clk->name; clk++) {
ret = mmap_mux(devmem, clk->primary);
if (ret < 0)
return ret;
ret = mmap_mux(devmem, clk->leaf);
ret = mmap_mux(devmem, clk->clk_mux);
if (ret < 0)
return ret;
}

45
debugcc.h
View File

@@ -43,6 +43,9 @@ struct debug_mux {
const char *block_name;
size_t size;
struct debug_mux *parent;
unsigned long parent_mux_val;
unsigned int enable_reg;
unsigned int enable_mask;
@@ -55,25 +58,22 @@ struct debug_mux {
unsigned int div_mask;
unsigned int div_val;
unsigned long (*measure)(const struct measure_clk *clk,
const struct debug_mux *mux);
};
struct gcc_mux {
struct debug_mux mux;
unsigned int xo_div4_reg;
unsigned int debug_ctl_reg;
unsigned int debug_status_reg;
unsigned int ahb_reg;
unsigned int ahb_mask;
void (*premeasure)(struct debug_mux *mux);
unsigned long (*measure)(const struct measure_clk *clk);
void (*postmeasure)(struct debug_mux *mux);
};
struct measure_clk {
char *name;
struct debug_mux *primary;
int mux;
struct debug_mux *leaf;
int leaf_mux;
struct debug_mux *clk_mux;
unsigned long mux;
unsigned int fixed_div;
};
@@ -84,10 +84,29 @@ struct debugcc_platform {
int (*premap)(int devmem);
};
#define container_of(ptr, type, member) \
((type *) ((char *)(ptr) - offsetof(type, member)))
static inline uint32_t readl(void *ptr)
{
return *((volatile uint32_t*)ptr);
}
static inline void writel(uint32_t val, void *ptr)
{
*((volatile uint32_t*)ptr) = val;
}
int mmap_mux(int devmem, struct debug_mux *mux);
void mux_enable(struct debug_mux *mux);
void mux_disable(struct debug_mux *mux);
unsigned long measure_mccc(const struct measure_clk *clk);
unsigned long measure_gcc(const struct measure_clk *clk,
const struct debug_mux *mux);
unsigned long measure_leaf(const struct measure_clk *clk,
const struct debug_mux *mux);
unsigned long measure_mccc(const struct measure_clk *clk,
const struct debug_mux *mux);
extern const struct debugcc_platform *platforms[];

242
msm8936.c
View File

@@ -49,22 +49,24 @@
#define GCC_CLOCK_FREQ_MEASURE_STATUS 0x74008
#define GCC_XO_DIV4_CBCR 0x30034
static struct debug_mux gcc;
static struct gcc_mux gcc = {
.mux = {
.phys = GCC_BASE,
.size = GCC_SIZE,
static struct debug_mux gcc = {
.phys = GCC_BASE,
.size = GCC_SIZE,
.measure = measure_gcc,
.enable_reg = GCC_DEBUG_CLK_CTL,
.enable_mask = BIT(16),
.enable_reg = GCC_DEBUG_CLK_CTL,
.enable_mask = BIT(16),
.mux_reg = GCC_DEBUG_CLK_CTL,
.mux_mask = 0x1ff,
.mux_reg = GCC_DEBUG_CLK_CTL,
.mux_mask = 0x1ff,
.div_reg = GCC_DEBUG_CLK_CTL,
.div_shift = 12,
.div_mask = 0xf << 12,
.div_val = 4,
.div_reg = GCC_DEBUG_CLK_CTL,
.div_shift = 12,
.div_mask = 0xf << 12,
.div_val = 4,
},
.xo_div4_reg = GCC_XO_DIV4_CBCR,
.debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL,
@@ -72,114 +74,114 @@ static struct debug_mux gcc = {
};
static struct measure_clk msm8936_clocks[] = {
{ "gcc_gp1_clk", &gcc, 16 },
{ "gcc_gp2_clk", &gcc, 17 },
{ "gcc_gp3_clk", &gcc, 18 },
{ "gcc_bimc_gfx_clk", &gcc, 45 },
{ "gcc_mss_cfg_ahb_clk", &gcc, 48 },
{ "gcc_mss_q6_bimc_axi_clk", &gcc, 49 },
{ "gcc_apss_tcu_clk", &gcc, 80 },
{ "gcc_mdp_tbu_clk", &gcc, 81 },
{ "gcc_gfx_tbu_clk", &gcc, 82 },
{ "gcc_gfx_tcu_clk", &gcc, 83 },
{ "gcc_venus_tbu_clk", &gcc, 84 },
{ "gcc_gtcu_ahb_clk", &gcc, 88 },
{ "gcc_vfe_tbu_clk", &gcc, 90 },
{ "gcc_smmu_cfg_clk", &gcc, 91 },
{ "gcc_jpeg_tbu_clk", &gcc, 92 },
{ "gcc_usb_hs_system_clk", &gcc, 96 },
{ "gcc_usb_hs_ahb_clk", &gcc, 97 },
{ "gcc_usb_fs_ahb_clk", &gcc, 241 },
{ "gcc_usb_fs_ic_clk", &gcc, 244 },
{ "gcc_usb2a_phy_sleep_clk", &gcc, 99 },
{ "gcc_sdcc1_apps_clk", &gcc, 104 },
{ "gcc_sdcc1_ahb_clk", &gcc, 105 },
{ "gcc_sdcc2_apps_clk", &gcc, 112 },
{ "gcc_sdcc2_ahb_clk", &gcc, 113 },
{ "gcc_blsp1_ahb_clk", &gcc, 136 },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138 },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139 },
{ "gcc_blsp1_uart1_apps_clk", &gcc, 140 },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142 },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 144 },
{ "gcc_blsp1_uart2_apps_clk", &gcc, 145 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc, 147 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 148 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc, 152 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 153 },
{ "gcc_blsp1_qup5_spi_apps_clk", &gcc, 156 },
{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc, 157 },
{ "gcc_blsp1_qup6_spi_apps_clk", &gcc, 161 },
{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc, 162 },
{ "gcc_camss_ahb_clk", &gcc, 168 },
{ "gcc_camss_top_ahb_clk", &gcc, 169 },
{ "gcc_camss_micro_ahb_clk", &gcc, 170 },
{ "gcc_camss_gp0_clk", &gcc, 171 },
{ "gcc_camss_gp1_clk", &gcc, 172 },
{ "gcc_camss_mclk0_clk", &gcc, 173 },
{ "gcc_camss_mclk1_clk", &gcc, 174 },
{ "gcc_camss_mclk2_clk", &gcc, 445 },
{ "gcc_camss_cci_clk", &gcc, 175 },
{ "gcc_camss_cci_ahb_clk", &gcc, 176 },
{ "gcc_camss_csi0phytimer_clk", &gcc, 177 },
{ "gcc_camss_csi1phytimer_clk", &gcc, 178 },
{ "gcc_camss_jpeg0_clk", &gcc, 179 },
{ "gcc_camss_jpeg_ahb_clk", &gcc, 180 },
{ "gcc_camss_jpeg_axi_clk", &gcc, 181 },
{ "gcc_camss_vfe0_clk", &gcc, 184 },
{ "gcc_camss_cpp_clk", &gcc, 185 },
{ "gcc_camss_cpp_ahb_clk", &gcc, 186 },
{ "gcc_camss_vfe_ahb_clk", &gcc, 187 },
{ "gcc_camss_vfe_axi_clk", &gcc, 188 },
{ "gcc_camss_csi_vfe0_clk", &gcc, 191 },
{ "gcc_camss_csi0_clk", &gcc, 192 },
{ "gcc_camss_csi0_ahb_clk", &gcc, 193 },
{ "gcc_camss_csi0phy_clk", &gcc, 194 },
{ "gcc_camss_csi0rdi_clk", &gcc, 195 },
{ "gcc_camss_csi0pix_clk", &gcc, 196 },
{ "gcc_camss_csi1_clk", &gcc, 197 },
{ "gcc_camss_csi1_ahb_clk", &gcc, 198 },
{ "gcc_camss_csi1phy_clk", &gcc, 199 },
{ "gcc_camss_csi2_clk", &gcc, 227 },
{ "gcc_camss_csi2_ahb_clk", &gcc, 228 },
{ "gcc_camss_csi2phy_clk", &gcc, 229 },
{ "gcc_camss_csi2rdi_clk", &gcc, 230 },
{ "gcc_camss_csi2pix_clk", &gcc, 231 },
{ "gcc_pdm_ahb_clk", &gcc, 208 },
{ "gcc_pdm2_clk", &gcc, 210 },
{ "gcc_prng_ahb_clk", &gcc, 216 },
{ "gcc_camss_csi1rdi_clk", &gcc, 224 },
{ "gcc_camss_csi1pix_clk", &gcc, 225 },
{ "gcc_camss_ispif_ahb_clk", &gcc, 226 },
{ "gcc_boot_rom_ahb_clk", &gcc, 248 },
{ "gcc_crypto_clk", &gcc, 312 },
{ "gcc_crypto_axi_clk", &gcc, 313 },
{ "gcc_crypto_ahb_clk", &gcc, 314 },
{ "gcc_oxili_timer_clk", &gcc, 489 },
{ "gcc_oxili_gfx3d_clk", &gcc, 490 },
{ "gcc_oxili_ahb_clk", &gcc, 491 },
{ "gcc_oxili_gmem_clk", &gcc, 496 },
{ "gcc_venus0_vcodec0_clk", &gcc, 497 },
{ "gcc_venus0_core0_vcodec0_clk", &gcc, 440 },
{ "gcc_venus0_core1_vcodec0_clk", &gcc, 441 },
{ "gcc_venus0_axi_clk", &gcc, 498 },
{ "gcc_venus0_ahb_clk", &gcc, 499 },
{ "gcc_mdss_ahb_clk", &gcc, 502 },
{ "gcc_mdss_axi_clk", &gcc, 503 },
{ "gcc_mdss_pclk0_clk", &gcc, 504 },
{ "gcc_mdss_pclk1_clk", &gcc, 442 },
{ "gcc_mdss_mdp_clk", &gcc, 505 },
{ "gcc_mdss_vsync_clk", &gcc, 507 },
{ "gcc_mdss_byte0_clk", &gcc, 508 },
{ "gcc_mdss_byte1_clk", &gcc, 443 },
{ "gcc_mdss_esc0_clk", &gcc, 509 },
{ "gcc_mdss_esc1_clk", &gcc, 444 },
{ "gcc_bimc_clk", &gcc, 340 },
{ "gcc_bimc_gpu_clk", &gcc, 343 },
{ "gcc_bimc_ddr_ch0_clk", &gcc, 346 },
{ "gcc_cpp_tbu_clk", &gcc, 233 },
{ "gcc_mdp_rt_tbu_clk", &gcc, 238 },
{ "wcnss_m_clk", &gcc, 408 },
{ "gcc_gp1_clk", &gcc.mux, 16 },
{ "gcc_gp2_clk", &gcc.mux, 17 },
{ "gcc_gp3_clk", &gcc.mux, 18 },
{ "gcc_bimc_gfx_clk", &gcc.mux, 45 },
{ "gcc_mss_cfg_ahb_clk", &gcc.mux, 48 },
{ "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 49 },
{ "gcc_apss_tcu_clk", &gcc.mux, 80 },
{ "gcc_mdp_tbu_clk", &gcc.mux, 81 },
{ "gcc_gfx_tbu_clk", &gcc.mux, 82 },
{ "gcc_gfx_tcu_clk", &gcc.mux, 83 },
{ "gcc_venus_tbu_clk", &gcc.mux, 84 },
{ "gcc_gtcu_ahb_clk", &gcc.mux, 88 },
{ "gcc_vfe_tbu_clk", &gcc.mux, 90 },
{ "gcc_smmu_cfg_clk", &gcc.mux, 91 },
{ "gcc_jpeg_tbu_clk", &gcc.mux, 92 },
{ "gcc_usb_hs_system_clk", &gcc.mux, 96 },
{ "gcc_usb_hs_ahb_clk", &gcc.mux, 97 },
{ "gcc_usb_fs_ahb_clk", &gcc.mux, 241 },
{ "gcc_usb_fs_ic_clk", &gcc.mux, 244 },
{ "gcc_usb2a_phy_sleep_clk", &gcc.mux, 99 },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 104 },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 105 },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 112 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 113 },
{ "gcc_blsp1_ahb_clk", &gcc.mux, 136 },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 138 },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 139 },
{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 140 },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 142 },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 144 },
{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 145 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 147 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 148 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 152 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 153 },
{ "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 156 },
{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 157 },
{ "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 161 },
{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 162 },
{ "gcc_camss_ahb_clk", &gcc.mux, 168 },
{ "gcc_camss_top_ahb_clk", &gcc.mux, 169 },
{ "gcc_camss_micro_ahb_clk", &gcc.mux, 170 },
{ "gcc_camss_gp0_clk", &gcc.mux, 171 },
{ "gcc_camss_gp1_clk", &gcc.mux, 172 },
{ "gcc_camss_mclk0_clk", &gcc.mux, 173 },
{ "gcc_camss_mclk1_clk", &gcc.mux, 174 },
{ "gcc_camss_mclk2_clk", &gcc.mux, 445 },
{ "gcc_camss_cci_clk", &gcc.mux, 175 },
{ "gcc_camss_cci_ahb_clk", &gcc.mux, 176 },
{ "gcc_camss_csi0phytimer_clk", &gcc.mux, 177 },
{ "gcc_camss_csi1phytimer_clk", &gcc.mux, 178 },
{ "gcc_camss_jpeg0_clk", &gcc.mux, 179 },
{ "gcc_camss_jpeg_ahb_clk", &gcc.mux, 180 },
{ "gcc_camss_jpeg_axi_clk", &gcc.mux, 181 },
{ "gcc_camss_vfe0_clk", &gcc.mux, 184 },
{ "gcc_camss_cpp_clk", &gcc.mux, 185 },
{ "gcc_camss_cpp_ahb_clk", &gcc.mux, 186 },
{ "gcc_camss_vfe_ahb_clk", &gcc.mux, 187 },
{ "gcc_camss_vfe_axi_clk", &gcc.mux, 188 },
{ "gcc_camss_csi_vfe0_clk", &gcc.mux, 191 },
{ "gcc_camss_csi0_clk", &gcc.mux, 192 },
{ "gcc_camss_csi0_ahb_clk", &gcc.mux, 193 },
{ "gcc_camss_csi0phy_clk", &gcc.mux, 194 },
{ "gcc_camss_csi0rdi_clk", &gcc.mux, 195 },
{ "gcc_camss_csi0pix_clk", &gcc.mux, 196 },
{ "gcc_camss_csi1_clk", &gcc.mux, 197 },
{ "gcc_camss_csi1_ahb_clk", &gcc.mux, 198 },
{ "gcc_camss_csi1phy_clk", &gcc.mux, 199 },
{ "gcc_camss_csi2_clk", &gcc.mux, 227 },
{ "gcc_camss_csi2_ahb_clk", &gcc.mux, 228 },
{ "gcc_camss_csi2phy_clk", &gcc.mux, 229 },
{ "gcc_camss_csi2rdi_clk", &gcc.mux, 230 },
{ "gcc_camss_csi2pix_clk", &gcc.mux, 231 },
{ "gcc_pdm_ahb_clk", &gcc.mux, 208 },
{ "gcc_pdm2_clk", &gcc.mux, 210 },
{ "gcc_prng_ahb_clk", &gcc.mux, 216 },
{ "gcc_camss_csi1rdi_clk", &gcc.mux, 224 },
{ "gcc_camss_csi1pix_clk", &gcc.mux, 225 },
{ "gcc_camss_ispif_ahb_clk", &gcc.mux, 226 },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 248 },
{ "gcc_crypto_clk", &gcc.mux, 312 },
{ "gcc_crypto_axi_clk", &gcc.mux, 313 },
{ "gcc_crypto_ahb_clk", &gcc.mux, 314 },
{ "gcc_oxili_timer_clk", &gcc.mux, 489 },
{ "gcc_oxili_gfx3d_clk", &gcc.mux, 490 },
{ "gcc_oxili_ahb_clk", &gcc.mux, 491 },
{ "gcc_oxili_gmem_clk", &gcc.mux, 496 },
{ "gcc_venus0_vcodec0_clk", &gcc.mux, 497 },
{ "gcc_venus0_core0_vcodec0_clk", &gcc.mux, 440 },
{ "gcc_venus0_core1_vcodec0_clk", &gcc.mux, 441 },
{ "gcc_venus0_axi_clk", &gcc.mux, 498 },
{ "gcc_venus0_ahb_clk", &gcc.mux, 499 },
{ "gcc_mdss_ahb_clk", &gcc.mux, 502 },
{ "gcc_mdss_axi_clk", &gcc.mux, 503 },
{ "gcc_mdss_pclk0_clk", &gcc.mux, 504 },
{ "gcc_mdss_pclk1_clk", &gcc.mux, 442 },
{ "gcc_mdss_mdp_clk", &gcc.mux, 505 },
{ "gcc_mdss_vsync_clk", &gcc.mux, 507 },
{ "gcc_mdss_byte0_clk", &gcc.mux, 508 },
{ "gcc_mdss_byte1_clk", &gcc.mux, 443 },
{ "gcc_mdss_esc0_clk", &gcc.mux, 509 },
{ "gcc_mdss_esc1_clk", &gcc.mux, 444 },
{ "gcc_bimc_clk", &gcc.mux, 340 },
{ "gcc_bimc_gpu_clk", &gcc.mux, 343 },
{ "gcc_bimc_ddr_ch0_clk", &gcc.mux, 346 },
{ "gcc_cpp_tbu_clk", &gcc.mux, 233 },
{ "gcc_mdp_rt_tbu_clk", &gcc.mux, 238 },
{ "wcnss_m_clk", &gcc.mux, 408 },
{},
};

368
msm8994.c
View File

@@ -12,20 +12,24 @@
#include "debugcc.h"
static struct debug_mux gcc = {
.phys = 0xfc400000,
.size = 0x2000,
static struct gcc_mux gcc = {
.mux = {
.phys = 0xfc400000,
.size = 0x2000,
.enable_reg = 0x1880,
.enable_mask = BIT(16),
.measure = measure_gcc,
.mux_reg = 0x1880,
.mux_mask = 0x3ff,
.enable_reg = 0x1880,
.enable_mask = BIT(16),
.div_reg = 0x1880,
.div_shift = 12,
.div_mask = 0xf << 12,
.div_val = 4,
.mux_reg = 0x1880,
.mux_mask = 0x3ff,
.div_reg = 0x1880,
.div_shift = 12,
.div_mask = 0xf << 12,
.div_val = 4,
},
.xo_div4_reg = 0x10c8,
.debug_ctl_reg = 0x1884,
@@ -37,6 +41,10 @@ static struct debug_mux mmcc = {
.size = 0x5200,
.block_name = "mm",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x2b,
.enable_reg = 0x900,
.enable_mask = BIT(16),
@@ -45,175 +53,175 @@ static struct debug_mux mmcc = {
};
static struct measure_clk msm8994_clocks[] = {
// { "debug_cpu_clk", &gcc, 0x16a },
// { "debug_mmss_clk", &gcc, 0x2b },
// { "debug_rpm_clk", &gcc, 0xffff },
{ "gcc_sys_noc_usb3_axi_clk", &gcc, 0x6 },
{ "gcc_mss_q6_bimc_axi_clk", &gcc, 0x31 },
{ "gcc_usb30_master_clk", &gcc, 0x50 },
{ "gcc_usb30_sleep_clk", &gcc, 0x51 },
{ "gcc_usb30_mock_utmi_clk", &gcc, 0x52 },
{ "gcc_usb3_phy_aux_clk", &gcc, 0x53 },
{ "gcc_usb3_phy_pipe_clk", &gcc, 0x54 },
{ "gcc_sys_noc_ufs_axi_clk", &gcc, 0x58 },
{ "gcc_usb_hs_system_clk", &gcc, 0x60 },
{ "gcc_usb_hs_ahb_clk", &gcc, 0x61 },
{ "gcc_usb2_hs_phy_sleep_clk", &gcc, 0x63 },
{ "gcc_usb_phy_cfg_ahb2phy_clk", &gcc, 0x64 },
{ "gcc_sdcc1_apps_clk", &gcc, 0x68 },
{ "gcc_sdcc1_ahb_clk", &gcc, 0x69 },
{ "gcc_sdcc2_apps_clk", &gcc, 0x70 },
{ "gcc_sdcc2_ahb_clk", &gcc, 0x71 },
{ "gcc_sdcc3_apps_clk", &gcc, 0x78 },
{ "gcc_sdcc3_ahb_clk", &gcc, 0x79 },
{ "gcc_sdcc4_apps_clk", &gcc, 0x80 },
{ "gcc_sdcc4_ahb_clk", &gcc, 0x81 },
{ "gcc_blsp1_ahb_clk", &gcc, 0x88 },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc, 0x8a },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 0x8b },
{ "gcc_blsp1_uart1_apps_clk", &gcc, 0x8c },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc, 0x8e },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 0x90 },
{ "gcc_blsp1_uart2_apps_clk", &gcc, 0x91 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc, 0x93 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 0x94 },
{ "gcc_blsp1_uart3_apps_clk", &gcc, 0x95 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc, 0x98 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 0x99 },
{ "gcc_blsp1_uart4_apps_clk", &gcc, 0x9a },
{ "gcc_blsp1_qup5_spi_apps_clk", &gcc, 0x9c },
{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc, 0x9d },
{ "gcc_blsp1_uart5_apps_clk", &gcc, 0x9e },
{ "gcc_blsp1_qup6_spi_apps_clk", &gcc, 0xa1 },
{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc, 0xa2 },
{ "gcc_blsp1_uart6_apps_clk", &gcc, 0xa3 },
{ "gcc_blsp2_ahb_clk", &gcc, 0xa8 },
{ "gcc_blsp2_qup1_spi_apps_clk", &gcc, 0xaa },
{ "gcc_blsp2_qup1_i2c_apps_clk", &gcc, 0xab },
{ "gcc_blsp2_uart1_apps_clk", &gcc, 0xac },
{ "gcc_blsp2_qup2_spi_apps_clk", &gcc, 0xae },
{ "gcc_blsp2_qup2_i2c_apps_clk", &gcc, 0xb0 },
{ "gcc_blsp2_uart2_apps_clk", &gcc, 0xb1 },
{ "gcc_blsp2_qup3_spi_apps_clk", &gcc, 0xb3 },
{ "gcc_blsp2_qup3_i2c_apps_clk", &gcc, 0xb4 },
{ "gcc_blsp2_uart3_apps_clk", &gcc, 0xb5 },
{ "gcc_blsp2_qup4_spi_apps_clk", &gcc, 0xb8 },
{ "gcc_blsp2_qup4_i2c_apps_clk", &gcc, 0xb9 },
{ "gcc_blsp2_uart4_apps_clk", &gcc, 0xba },
{ "gcc_blsp2_qup5_spi_apps_clk", &gcc, 0xbc },
{ "gcc_blsp2_qup5_i2c_apps_clk", &gcc, 0xbd },
{ "gcc_blsp2_uart5_apps_clk", &gcc, 0xbe },
{ "gcc_blsp2_qup6_spi_apps_clk", &gcc, 0xc1 },
{ "gcc_blsp2_qup6_i2c_apps_clk", &gcc, 0xc2 },
{ "gcc_blsp2_uart6_apps_clk", &gcc, 0xc3 },
{ "gcc_pdm_ahb_clk", &gcc, 0xd0 },
{ "gcc_pdm2_clk", &gcc, 0xd2 },
{ "gcc_prng_ahb_clk", &gcc, 0xd8 },
{ "gcc_bam_dma_ahb_clk", &gcc, 0xe0 },
{ "gcc_tsif_ahb_clk", &gcc, 0xe8 },
{ "gcc_tsif_ref_clk", &gcc, 0xe9 },
{ "gcc_boot_rom_ahb_clk", &gcc, 0xf8 },
{ "gcc_lpass_q6_axi_clk", &gcc, 0x160 },
{ "gcc_pcie_0_slv_axi_clk", &gcc, 0x1e8 },
{ "gcc_pcie_0_mstr_axi_clk", &gcc, 0x1e9 },
{ "gcc_pcie_0_cfg_ahb_clk", &gcc, 0x1ea },
{ "gcc_pcie_0_aux_clk", &gcc, 0x1eb },
{ "gcc_pcie_0_pipe_clk", &gcc, 0x1ec },
{ "gcc_pcie_1_slv_axi_clk", &gcc, 0x1f0 },
{ "gcc_pcie_1_mstr_axi_clk", &gcc, 0x1f1 },
{ "gcc_pcie_1_cfg_ahb_clk", &gcc, 0x1f2 },
{ "gcc_pcie_1_aux_clk", &gcc, 0x1f3 },
{ "gcc_pcie_1_pipe_clk", &gcc, 0x1f4 },
{ "gcc_ufs_axi_clk", &gcc, 0x230 },
{ "gcc_ufs_ahb_clk", &gcc, 0x231 },
{ "gcc_ufs_tx_cfg_clk", &gcc, 0x232 },
{ "gcc_ufs_rx_cfg_clk", &gcc, 0x233 },
{ "gcc_ufs_tx_symbol_0_clk", &gcc, 0x234 },
{ "gcc_ufs_tx_symbol_1_clk", &gcc, 0x235 },
{ "gcc_ufs_rx_symbol_0_clk", &gcc, 0x236 },
{ "gcc_ufs_rx_symbol_1_clk", &gcc, 0x237 },
{ "mmsscc_mmssnoc_ahb", &gcc, 0x2b, &mmcc, 0x1 },
{ "oxili_gfx3d_clk", &gcc, 0x2b, &mmcc, 0xd },
{ "mmss_misc_ahb_clk", &gcc, 0x2b, &mmcc, 0x3 },
{ "mmss_mmssnoc_axi_clk", &gcc, 0x2b, &mmcc, 0x4 },
{ "mmss_s0_axi_clk", &gcc, 0x2b, &mmcc, 0x5 },
{ "ocmemcx_ocmemnoc_clk", &gcc, 0x2b, &mmcc, 0x9 },
{ "oxilicx_ahb_clk", &gcc, 0x2b, &mmcc, 0xc },
{ "venus0_vcodec0_clk", &gcc, 0x2b, &mmcc, 0xe },
{ "venus0_axi_clk", &gcc, 0x2b, &mmcc, 0xf },
{ "venus0_ocmemnoc_clk", &gcc, 0x2b, &mmcc, 0x10 },
{ "venus0_ahb_clk", &gcc, 0x2b, &mmcc, 0x11 },
{ "mdss_mdp_clk", &gcc, 0x2b, &mmcc, 0x14 },
{ "mdss_pclk0_clk", &gcc, 0x2b, &mmcc, 0x16 },
{ "mdss_pclk1_clk", &gcc, 0x2b, &mmcc, 0x17 },
{ "mdss_extpclk_clk", &gcc, 0x2b, &mmcc, 0x18 },
{ "venus0_core0_vcodec_clk", &gcc, 0x2b, &mmcc, 0x1a },
{ "venus0_core1_vcodec_clk", &gcc, 0x2b, &mmcc, 0x1b },
{ "mdss_vsync_clk", &gcc, 0x2b, &mmcc, 0x1c },
{ "mdss_hdmi_clk", &gcc, 0x2b, &mmcc, 0x1d },
{ "mdss_byte0_clk", &gcc, 0x2b, &mmcc, 0x1e },
{ "mdss_byte1_clk", &gcc, 0x2b, &mmcc, 0x1f },
{ "mdss_esc0_clk", &gcc, 0x2b, &mmcc, 0x20 },
{ "mdss_esc1_clk", &gcc, 0x2b, &mmcc, 0x21 },
{ "mdss_ahb_clk", &gcc, 0x2b, &mmcc, 0x22 },
{ "mdss_hdmi_ahb_clk", &gcc, 0x2b, &mmcc, 0x23 },
{ "mdss_axi_clk", &gcc, 0x2b, &mmcc, 0x24 },
{ "camss_top_ahb_clk", &gcc, 0x2b, &mmcc, 0x25 },
{ "camss_micro_ahb_clk", &gcc, 0x2b, &mmcc, 0x26 },
{ "camss_gp0_clk", &gcc, 0x2b, &mmcc, 0x27 },
{ "camss_gp1_clk", &gcc, 0x2b, &mmcc, 0x28 },
{ "camss_mclk0_clk", &gcc, 0x2b, &mmcc, 0x29 },
{ "camss_mclk1_clk", &gcc, 0x2b, &mmcc, 0x2a },
{ "camss_mclk2_clk", &gcc, 0x2b, &mmcc, 0x2b },
{ "camss_mclk3_clk", &gcc, 0x2b, &mmcc, 0x2c },
{ "camss_cci_cci_clk", &gcc, 0x2b, &mmcc, 0x2d },
{ "camss_cci_cci_ahb_clk", &gcc, 0x2b, &mmcc, 0x2e },
{ "camss_phy0_csi0phytimer_clk", &gcc, 0x2b, &mmcc, 0x2f },
{ "camss_phy1_csi1phytimer_clk", &gcc, 0x2b, &mmcc, 0x30 },
{ "camss_phy2_csi2phytimer_clk", &gcc, 0x2b, &mmcc, 0x31 },
{ "camss_jpeg_jpeg0_clk", &gcc, 0x2b, &mmcc, 0x32 },
{ "camss_jpeg_jpeg1_clk", &gcc, 0x2b, &mmcc, 0x33 },
{ "camss_jpeg_jpeg2_clk", &gcc, 0x2b, &mmcc, 0x34 },
{ "camss_jpeg_jpeg_ahb_clk", &gcc, 0x2b, &mmcc, 0x35 },
{ "camss_jpeg_jpeg_axi_clk", &gcc, 0x2b, &mmcc, 0x36 },
{ "camss_ahb_clk", &gcc, 0x2b, &mmcc, 0x37 },
{ "camss_vfe_vfe0_clk", &gcc, 0x2b, &mmcc, 0x38 },
{ "camss_vfe_vfe1_clk", &gcc, 0x2b, &mmcc, 0x39 },
{ "camss_vfe_cpp_clk", &gcc, 0x2b, &mmcc, 0x3a },
{ "camss_vfe_cpp_ahb_clk", &gcc, 0x2b, &mmcc, 0x3b },
{ "camss_vfe_vfe_ahb_clk", &gcc, 0x2b, &mmcc, 0x3c },
{ "camss_vfe_vfe_axi_clk", &gcc, 0x2b, &mmcc, 0x3d },
{ "oxili_rbbmtimer_clk", &gcc, 0x2b, &mmcc, 0x3e },
{ "camss_csi_vfe0_clk", &gcc, 0x2b, &mmcc, 0x3f },
{ "camss_csi_vfe1_clk", &gcc, 0x2b, &mmcc, 0x40 },
{ "camss_csi0_clk", &gcc, 0x2b, &mmcc, 0x41 },
{ "camss_csi0_ahb_clk", &gcc, 0x2b, &mmcc, 0x42 },
{ "camss_csi0phy_clk", &gcc, 0x2b, &mmcc, 0x43 },
{ "camss_csi0rdi_clk", &gcc, 0x2b, &mmcc, 0x44 },
{ "camss_csi0pix_clk", &gcc, 0x2b, &mmcc, 0x45 },
{ "camss_csi1_clk", &gcc, 0x2b, &mmcc, 0x46 },
{ "camss_csi1_ahb_clk", &gcc, 0x2b, &mmcc, 0x47 },
{ "camss_csi1phy_clk", &gcc, 0x2b, &mmcc, 0x48 },
{ "camss_csi1rdi_clk", &gcc, 0x2b, &mmcc, 0x49 },
{ "camss_csi1pix_clk", &gcc, 0x2b, &mmcc, 0x4a },
{ "camss_csi2_clk", &gcc, 0x2b, &mmcc, 0x4b },
{ "camss_csi2_ahb_clk", &gcc, 0x2b, &mmcc, 0x4c },
{ "camss_csi2phy_clk", &gcc, 0x2b, &mmcc, 0x4d },
{ "camss_csi2rdi_clk", &gcc, 0x2b, &mmcc, 0x4e },
{ "camss_csi2pix_clk", &gcc, 0x2b, &mmcc, 0x4f },
{ "camss_csi3_clk", &gcc, 0x2b, &mmcc, 0x50 },
{ "camss_csi3_ahb_clk", &gcc, 0x2b, &mmcc, 0x51 },
{ "camss_csi3phy_clk", &gcc, 0x2b, &mmcc, 0x52 },
{ "camss_csi3rdi_clk", &gcc, 0x2b, &mmcc, 0x53 },
{ "camss_csi3pix_clk", &gcc, 0x2b, &mmcc, 0x54 },
{ "camss_ispif_ahb_clk", &gcc, 0x2b, &mmcc, 0x55 },
{ "venus0_core2_vcodec_clk", &gcc, 0x2b, &mmcc, 0x79 },
{ "camss_vfe_cpp_axi_clk", &gcc, 0x2b, &mmcc, 0x7a },
{ "camss_jpeg_dma_clk", &gcc, 0x2b, &mmcc, 0x7b },
{ "fd_core_clk", &gcc, 0x2b, &mmcc, 0x89 },
{ "fd_core_uar_clk", &gcc, 0x2b, &mmcc, 0x8a },
{ "fd_axi_clk", &gcc, 0x2b, &mmcc, 0x8b },
{ "fd_ahb_clk", &gcc, 0x2b, &mmcc, 0x8c },
// { "debug_cpu_clk", &gcc.mux, 0x16a },
{ "gcc_sys_noc_usb3_axi_clk", &gcc.mux, 0x6 },
{ "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 0x31 },
{ "gcc_usb30_master_clk", &gcc.mux, 0x50 },
{ "gcc_usb30_sleep_clk", &gcc.mux, 0x51 },
{ "gcc_usb30_mock_utmi_clk", &gcc.mux, 0x52 },
{ "gcc_usb3_phy_aux_clk", &gcc.mux, 0x53 },
{ "gcc_usb3_phy_pipe_clk", &gcc.mux, 0x54 },
{ "gcc_sys_noc_ufs_axi_clk", &gcc.mux, 0x58 },
{ "gcc_usb_hs_system_clk", &gcc.mux, 0x60 },
{ "gcc_usb_hs_ahb_clk", &gcc.mux, 0x61 },
{ "gcc_usb2_hs_phy_sleep_clk", &gcc.mux, 0x63 },
{ "gcc_usb_phy_cfg_ahb2phy_clk", &gcc.mux, 0x64 },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0x68 },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0x69 },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x70 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x71 },
{ "gcc_sdcc3_apps_clk", &gcc.mux, 0x78 },
{ "gcc_sdcc3_ahb_clk", &gcc.mux, 0x79 },
{ "gcc_sdcc4_apps_clk", &gcc.mux, 0x80 },
{ "gcc_sdcc4_ahb_clk", &gcc.mux, 0x81 },
{ "gcc_blsp1_ahb_clk", &gcc.mux, 0x88 },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 0x8a },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 0x8b },
{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 0x8c },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 0x8e },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 0x90 },
{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 0x91 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 0x93 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 0x94 },
{ "gcc_blsp1_uart3_apps_clk", &gcc.mux, 0x95 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 0x98 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 0x99 },
{ "gcc_blsp1_uart4_apps_clk", &gcc.mux, 0x9a },
{ "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 0x9c },
{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 0x9d },
{ "gcc_blsp1_uart5_apps_clk", &gcc.mux, 0x9e },
{ "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 0xa1 },
{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 0xa2 },
{ "gcc_blsp1_uart6_apps_clk", &gcc.mux, 0xa3 },
{ "gcc_blsp2_ahb_clk", &gcc.mux, 0xa8 },
{ "gcc_blsp2_qup1_spi_apps_clk", &gcc.mux, 0xaa },
{ "gcc_blsp2_qup1_i2c_apps_clk", &gcc.mux, 0xab },
{ "gcc_blsp2_uart1_apps_clk", &gcc.mux, 0xac },
{ "gcc_blsp2_qup2_spi_apps_clk", &gcc.mux, 0xae },
{ "gcc_blsp2_qup2_i2c_apps_clk", &gcc.mux, 0xb0 },
{ "gcc_blsp2_uart2_apps_clk", &gcc.mux, 0xb1 },
{ "gcc_blsp2_qup3_spi_apps_clk", &gcc.mux, 0xb3 },
{ "gcc_blsp2_qup3_i2c_apps_clk", &gcc.mux, 0xb4 },
{ "gcc_blsp2_uart3_apps_clk", &gcc.mux, 0xb5 },
{ "gcc_blsp2_qup4_spi_apps_clk", &gcc.mux, 0xb8 },
{ "gcc_blsp2_qup4_i2c_apps_clk", &gcc.mux, 0xb9 },
{ "gcc_blsp2_uart4_apps_clk", &gcc.mux, 0xba },
{ "gcc_blsp2_qup5_spi_apps_clk", &gcc.mux, 0xbc },
{ "gcc_blsp2_qup5_i2c_apps_clk", &gcc.mux, 0xbd },
{ "gcc_blsp2_uart5_apps_clk", &gcc.mux, 0xbe },
{ "gcc_blsp2_qup6_spi_apps_clk", &gcc.mux, 0xc1 },
{ "gcc_blsp2_qup6_i2c_apps_clk", &gcc.mux, 0xc2 },
{ "gcc_blsp2_uart6_apps_clk", &gcc.mux, 0xc3 },
{ "gcc_pdm_ahb_clk", &gcc.mux, 0xd0 },
{ "gcc_pdm2_clk", &gcc.mux, 0xd2 },
{ "gcc_prng_ahb_clk", &gcc.mux, 0xd8 },
{ "gcc_bam_dma_ahb_clk", &gcc.mux, 0xe0 },
{ "gcc_tsif_ahb_clk", &gcc.mux, 0xe8 },
{ "gcc_tsif_ref_clk", &gcc.mux, 0xe9 },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0xf8 },
{ "gcc_lpass_q6_axi_clk", &gcc.mux, 0x160 },
{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0x1e8 },
{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0x1e9 },
{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0x1ea },
{ "gcc_pcie_0_aux_clk", &gcc.mux, 0x1eb },
{ "gcc_pcie_0_pipe_clk", &gcc.mux, 0x1ec },
{ "gcc_pcie_1_slv_axi_clk", &gcc.mux, 0x1f0 },
{ "gcc_pcie_1_mstr_axi_clk", &gcc.mux, 0x1f1 },
{ "gcc_pcie_1_cfg_ahb_clk", &gcc.mux, 0x1f2 },
{ "gcc_pcie_1_aux_clk", &gcc.mux, 0x1f3 },
{ "gcc_pcie_1_pipe_clk", &gcc.mux, 0x1f4 },
{ "gcc_ufs_axi_clk", &gcc.mux, 0x230 },
{ "gcc_ufs_ahb_clk", &gcc.mux, 0x231 },
{ "gcc_ufs_tx_cfg_clk", &gcc.mux, 0x232 },
{ "gcc_ufs_rx_cfg_clk", &gcc.mux, 0x233 },
{ "gcc_ufs_tx_symbol_0_clk", &gcc.mux, 0x234 },
{ "gcc_ufs_tx_symbol_1_clk", &gcc.mux, 0x235 },
{ "gcc_ufs_rx_symbol_0_clk", &gcc.mux, 0x236 },
{ "gcc_ufs_rx_symbol_1_clk", &gcc.mux, 0x237 },
{ "mmsscc_mmssnoc_ahb", &mmcc, 0x1 },
{ "oxili_gfx3d_clk", &mmcc, 0xd },
{ "mmss_misc_ahb_clk", &mmcc, 0x3 },
{ "mmss_mmssnoc_axi_clk", &mmcc, 0x4 },
{ "mmss_s0_axi_clk", &mmcc, 0x5 },
{ "ocmemcx_ocmemnoc_clk", &mmcc, 0x9 },
{ "oxilicx_ahb_clk", &mmcc, 0xc },
{ "venus0_vcodec0_clk", &mmcc, 0xe },
{ "venus0_axi_clk", &mmcc, 0xf },
{ "venus0_ocmemnoc_clk", &mmcc, 0x10 },
{ "venus0_ahb_clk", &mmcc, 0x11 },
{ "mdss_mdp_clk", &mmcc, 0x14 },
{ "mdss_pclk0_clk", &mmcc, 0x16 },
{ "mdss_pclk1_clk", &mmcc, 0x17 },
{ "mdss_extpclk_clk", &mmcc, 0x18 },
{ "venus0_core0_vcodec_clk", &mmcc, 0x1a },
{ "venus0_core1_vcodec_clk", &mmcc, 0x1b },
{ "mdss_vsync_clk", &mmcc, 0x1c },
{ "mdss_hdmi_clk", &mmcc, 0x1d },
{ "mdss_byte0_clk", &mmcc, 0x1e },
{ "mdss_byte1_clk", &mmcc, 0x1f },
{ "mdss_esc0_clk", &mmcc, 0x20 },
{ "mdss_esc1_clk", &mmcc, 0x21 },
{ "mdss_ahb_clk", &mmcc, 0x22 },
{ "mdss_hdmi_ahb_clk", &mmcc, 0x23 },
{ "mdss_axi_clk", &mmcc, 0x24 },
{ "camss_top_ahb_clk", &mmcc, 0x25 },
{ "camss_micro_ahb_clk", &mmcc, 0x26 },
{ "camss_gp0_clk", &mmcc, 0x27 },
{ "camss_gp1_clk", &mmcc, 0x28 },
{ "camss_mclk0_clk", &mmcc, 0x29 },
{ "camss_mclk1_clk", &mmcc, 0x2a },
{ "camss_mclk2_clk", &mmcc, 0x2b },
{ "camss_mclk3_clk", &mmcc, 0x2c },
{ "camss_cci_cci_clk", &mmcc, 0x2d },
{ "camss_cci_cci_ahb_clk", &mmcc, 0x2e },
{ "camss_phy0_csi0phytimer_clk", &mmcc, 0x2f },
{ "camss_phy1_csi1phytimer_clk", &mmcc, 0x30 },
{ "camss_phy2_csi2phytimer_clk", &mmcc, 0x31 },
{ "camss_jpeg_jpeg0_clk", &mmcc, 0x32 },
{ "camss_jpeg_jpeg1_clk", &mmcc, 0x33 },
{ "camss_jpeg_jpeg2_clk", &mmcc, 0x34 },
{ "camss_jpeg_jpeg_ahb_clk", &mmcc, 0x35 },
{ "camss_jpeg_jpeg_axi_clk", &mmcc, 0x36 },
{ "camss_ahb_clk", &mmcc, 0x37 },
{ "camss_vfe_vfe0_clk", &mmcc, 0x38 },
{ "camss_vfe_vfe1_clk", &mmcc, 0x39 },
{ "camss_vfe_cpp_clk", &mmcc, 0x3a },
{ "camss_vfe_cpp_ahb_clk", &mmcc, 0x3b },
{ "camss_vfe_vfe_ahb_clk", &mmcc, 0x3c },
{ "camss_vfe_vfe_axi_clk", &mmcc, 0x3d },
{ "oxili_rbbmtimer_clk", &mmcc, 0x3e },
{ "camss_csi_vfe0_clk", &mmcc, 0x3f },
{ "camss_csi_vfe1_clk", &mmcc, 0x40 },
{ "camss_csi0_clk", &mmcc, 0x41 },
{ "camss_csi0_ahb_clk", &mmcc, 0x42 },
{ "camss_csi0phy_clk", &mmcc, 0x43 },
{ "camss_csi0rdi_clk", &mmcc, 0x44 },
{ "camss_csi0pix_clk", &mmcc, 0x45 },
{ "camss_csi1_clk", &mmcc, 0x46 },
{ "camss_csi1_ahb_clk", &mmcc, 0x47 },
{ "camss_csi1phy_clk", &mmcc, 0x48 },
{ "camss_csi1rdi_clk", &mmcc, 0x49 },
{ "camss_csi1pix_clk", &mmcc, 0x4a },
{ "camss_csi2_clk", &mmcc, 0x4b },
{ "camss_csi2_ahb_clk", &mmcc, 0x4c },
{ "camss_csi2phy_clk", &mmcc, 0x4d },
{ "camss_csi2rdi_clk", &mmcc, 0x4e },
{ "camss_csi2pix_clk", &mmcc, 0x4f },
{ "camss_csi3_clk", &mmcc, 0x50 },
{ "camss_csi3_ahb_clk", &mmcc, 0x51 },
{ "camss_csi3phy_clk", &mmcc, 0x52 },
{ "camss_csi3rdi_clk", &mmcc, 0x53 },
{ "camss_csi3pix_clk", &mmcc, 0x54 },
{ "camss_ispif_ahb_clk", &mmcc, 0x55 },
{ "venus0_core2_vcodec_clk", &mmcc, 0x79 },
{ "camss_vfe_cpp_axi_clk", &mmcc, 0x7a },
{ "camss_jpeg_dma_clk", &mmcc, 0x7b },
{ "fd_core_clk", &mmcc, 0x89 },
{ "fd_core_uar_clk", &mmcc, 0x8a },
{ "fd_axi_clk", &mmcc, 0x8b },
{ "fd_ahb_clk", &mmcc, 0x8c },
{}
};

527
msm8996.c
View File

File diff suppressed because it is too large Load Diff

399
msm8998.c
View File

@@ -12,19 +12,23 @@
#include "debugcc.h"
static struct debug_mux gcc = {
.phys = 0x100000,
.size = 0xb0000,
static struct gcc_mux gcc = {
.mux = {
.phys = 0x100000,
.size = 0xb0000,
.enable_reg = 0x62000,
.enable_mask = BIT(16),
.measure = measure_gcc,
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.enable_reg = 0x62000,
.enable_mask = BIT(16),
.div_reg = 0x62000,
.div_mask = 0xf,
.div_val = 4,
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.div_reg = 0x62000,
.div_mask = 0xf,
.div_val = 4,
},
.xo_div4_reg = 0x43008,
.debug_ctl_reg = 0x62004,
@@ -36,6 +40,10 @@ static struct debug_mux mm_cc = {
.size = 0x40000,
.block_name = "mm",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x22,
.enable_reg = 0x900,
.enable_mask = BIT(16),
@@ -48,6 +56,10 @@ static struct debug_mux gpu_cc = {
.size = 0x9000,
.block_name = "gpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x13d,
.enable_reg = 0x120,
.enable_mask = BIT(16),
@@ -56,194 +68,191 @@ static struct debug_mux gpu_cc = {
};
static struct measure_clk msm8998_clocks[] = {
// { "gpu_gcc_debug_clk", &gcc, 0x13d },
// { "gfx_gcc_debug_clk", &gcc, 0x13d },
// { "debug_mmss_clk", &gcc, 0x22 },
// { "debug_cpu_clk", &gcc, 0xc0 },
// { "debug_cpu_clk", &gcc.mux, 0xc0 },
{ "snoc_clk", &gcc, 0x0 },
{ "cnoc_clk", &gcc, 0xe },
{ "bimc_clk", &gcc, 0x14e },
{ "gcc_mmss_sys_noc_axi_clk", &gcc, 0x1f },
{ "gcc_mmss_noc_cfg_ahb_clk", &gcc, 0x20 },
{ "gcc_usb30_master_clk", &gcc, 0x3e },
{ "gcc_usb30_sleep_clk", &gcc, 0x3f },
{ "gcc_usb30_mock_utmi_clk", &gcc, 0x40 },
{ "gcc_usb3_phy_aux_clk", &gcc, 0x41 },
{ "gcc_usb3_phy_pipe_clk", &gcc, 0x42 },
{ "gcc_sdcc2_apps_clk", &gcc, 0x46 },
{ "gcc_sdcc2_ahb_clk", &gcc, 0x47 },
{ "gcc_sdcc4_apps_clk", &gcc, 0x48 },
{ "gcc_sdcc4_ahb_clk", &gcc, 0x49 },
{ "gcc_blsp1_ahb_clk", &gcc, 0x4a },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc, 0x4c },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 0x4d },
{ "gcc_blsp1_uart1_apps_clk", &gcc, 0x4e },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc, 0x50 },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 0x51 },
{ "gcc_blsp1_uart2_apps_clk", &gcc, 0x52 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc, 0x54 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 0x55 },
{ "gcc_blsp1_uart3_apps_clk", &gcc, 0x56 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc, 0x58 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 0x59 },
{ "gcc_blsp1_qup5_spi_apps_clk", &gcc, 0x5a },
{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc, 0x5b },
{ "gcc_blsp1_qup6_spi_apps_clk", &gcc, 0x5c },
{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc, 0x5d },
{ "gcc_blsp2_ahb_clk", &gcc, 0x5e },
{ "gcc_blsp2_qup1_spi_apps_clk", &gcc, 0x60 },
{ "gcc_blsp2_qup1_i2c_apps_clk", &gcc, 0x61 },
{ "gcc_blsp2_uart1_apps_clk", &gcc, 0x62 },
{ "gcc_blsp2_qup2_spi_apps_clk", &gcc, 0x64 },
{ "gcc_blsp2_qup2_i2c_apps_clk", &gcc, 0x65 },
{ "gcc_blsp2_uart2_apps_clk", &gcc, 0x66 },
{ "gcc_blsp2_qup3_spi_apps_clk", &gcc, 0x68 },
{ "gcc_blsp2_qup3_i2c_apps_clk", &gcc, 0x69 },
{ "gcc_blsp2_uart3_apps_clk", &gcc, 0x6a },
{ "gcc_blsp2_qup4_spi_apps_clk", &gcc, 0x6c },
{ "gcc_blsp2_qup4_i2c_apps_clk", &gcc, 0x6d },
{ "gcc_blsp2_qup5_spi_apps_clk", &gcc, 0x6e },
{ "gcc_blsp2_qup5_i2c_apps_clk", &gcc, 0x6f },
{ "gcc_blsp2_qup6_spi_apps_clk", &gcc, 0x70 },
{ "gcc_blsp2_qup6_i2c_apps_clk", &gcc, 0x71 },
{ "gcc_pdm_ahb_clk", &gcc, 0x72 },
{ "gcc_pdm2_clk", &gcc, 0x74},
{ "gcc_prng_ahb_clk", &gcc, 0x75 },
{ "gcc_tsif_ahb_clk", &gcc, 0x76 },
{ "gcc_tsif_ref_clk", &gcc, 0x77 },
{ "gcc_boot_rom_ahb_clk", &gcc, 0x7a },
{ "ce1_clk", &gcc, 0x97 },
{ "gcc_ce1_axi_m_clk", &gcc, 0x98 },
{ "gcc_ce1_ahb_m_clk", &gcc, 0x99 },
{ "measure_only_bimc_hmss_axi_clk", &gcc, 0xbb },
{ "gcc_bimc_gfx_clk", &gcc, 0xac },
{ "gcc_hmss_rbcpr_clk", &gcc, 0xbc },
{ "gcc_gp1_clk", &gcc, 0xdf },
{ "gcc_gp2_clk", &gcc, 0xe0 },
{ "gcc_gp3_clk", &gcc, 0xe1 },
{ "gcc_pcie_0_slv_axi_clk", &gcc, 0xe2 },
{ "gcc_pcie_0_mstr_axi_clk", &gcc, 0xe3 },
{ "gcc_pcie_0_cfg_ahb_clk", &gcc, 0xe4 },
{ "gcc_pcie_0_aux_clk", &gcc, 0xe5 },
{ "gcc_pcie_0_pipe_clk", &gcc, 0xe6 },
{ "gcc_pcie_phy_aux_clk", &gcc, 0xe8 },
{ "gcc_ufs_axi_clk", &gcc, 0xea },
{ "gcc_ufs_ahb_clk", &gcc, 0xeb },
{ "gcc_ufs_tx_symbol_0_clk", &gcc, 0xec },
{ "gcc_ufs_rx_symbol_0_clk", &gcc, 0xed },
{ "gcc_ufs_rx_symbol_1_clk", &gcc, 0x162 },
{ "gcc_ufs_unipro_core_clk", &gcc, 0xf0 },
{ "gcc_ufs_ice_core_clk", &gcc, 0xf1 },
{ "gcc_dcc_ahb_clk", &gcc, 0x119 },
{ "ipa_clk", &gcc, 0x11b },
{ "gcc_mss_cfg_ahb_clk", &gcc, 0x11f },
{ "gcc_mss_q6_bimc_axi_clk", &gcc, 0x124 },
{ "gcc_mss_mnoc_bimc_axi_clk", &gcc, 0x120 },
{ "gcc_mss_snoc_axi_clk", &gcc, 0x123 },
{ "gcc_gpu_cfg_ahb_clk", &gcc, 0x13b },
{ "gcc_gpu_bimc_gfx_clk", &gcc, 0x13f },
{ "gcc_qspi_ahb_clk", &gcc, 0x156 },
{ "gcc_qspi_ref_clk", &gcc, 0x157 },
{ "snoc_clk", &gcc.mux, 0x0 },
{ "cnoc_clk", &gcc.mux, 0xe },
{ "bimc_clk", &gcc.mux, 0x14e },
{ "gcc_mmss_sys_noc_axi_clk", &gcc.mux, 0x1f },
{ "gcc_mmss_noc_cfg_ahb_clk", &gcc.mux, 0x20 },
{ "gcc_usb30_master_clk", &gcc.mux, 0x3e },
{ "gcc_usb30_sleep_clk", &gcc.mux, 0x3f },
{ "gcc_usb30_mock_utmi_clk", &gcc.mux, 0x40 },
{ "gcc_usb3_phy_aux_clk", &gcc.mux, 0x41 },
{ "gcc_usb3_phy_pipe_clk", &gcc.mux, 0x42 },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x46 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x47 },
{ "gcc_sdcc4_apps_clk", &gcc.mux, 0x48 },
{ "gcc_sdcc4_ahb_clk", &gcc.mux, 0x49 },
{ "gcc_blsp1_ahb_clk", &gcc.mux, 0x4a },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 0x4c },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 0x4d },
{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 0x4e },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 0x50 },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 0x51 },
{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 0x52 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 0x54 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 0x55 },
{ "gcc_blsp1_uart3_apps_clk", &gcc.mux, 0x56 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 0x58 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 0x59 },
{ "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 0x5a },
{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 0x5b },
{ "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 0x5c },
{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 0x5d },
{ "gcc_blsp2_ahb_clk", &gcc.mux, 0x5e },
{ "gcc_blsp2_qup1_spi_apps_clk", &gcc.mux, 0x60 },
{ "gcc_blsp2_qup1_i2c_apps_clk", &gcc.mux, 0x61 },
{ "gcc_blsp2_uart1_apps_clk", &gcc.mux, 0x62 },
{ "gcc_blsp2_qup2_spi_apps_clk", &gcc.mux, 0x64 },
{ "gcc_blsp2_qup2_i2c_apps_clk", &gcc.mux, 0x65 },
{ "gcc_blsp2_uart2_apps_clk", &gcc.mux, 0x66 },
{ "gcc_blsp2_qup3_spi_apps_clk", &gcc.mux, 0x68 },
{ "gcc_blsp2_qup3_i2c_apps_clk", &gcc.mux, 0x69 },
{ "gcc_blsp2_uart3_apps_clk", &gcc.mux, 0x6a },
{ "gcc_blsp2_qup4_spi_apps_clk", &gcc.mux, 0x6c },
{ "gcc_blsp2_qup4_i2c_apps_clk", &gcc.mux, 0x6d },
{ "gcc_blsp2_qup5_spi_apps_clk", &gcc.mux, 0x6e },
{ "gcc_blsp2_qup5_i2c_apps_clk", &gcc.mux, 0x6f },
{ "gcc_blsp2_qup6_spi_apps_clk", &gcc.mux, 0x70 },
{ "gcc_blsp2_qup6_i2c_apps_clk", &gcc.mux, 0x71 },
{ "gcc_pdm_ahb_clk", &gcc.mux, 0x72 },
{ "gcc_pdm2_clk", &gcc.mux, 0x74},
{ "gcc_prng_ahb_clk", &gcc.mux, 0x75 },
{ "gcc_tsif_ahb_clk", &gcc.mux, 0x76 },
{ "gcc_tsif_ref_clk", &gcc.mux, 0x77 },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x7a },
{ "ce1_clk", &gcc.mux, 0x97 },
{ "gcc_ce1_axi_m_clk", &gcc.mux, 0x98 },
{ "gcc_ce1_ahb_m_clk", &gcc.mux, 0x99 },
{ "measure_only_bimc_hmss_axi_clk", &gcc.mux, 0xbb },
{ "gcc_bimc_gfx_clk", &gcc.mux, 0xac },
{ "gcc_hmss_rbcpr_clk", &gcc.mux, 0xbc },
{ "gcc_gp1_clk", &gcc.mux, 0xdf },
{ "gcc_gp2_clk", &gcc.mux, 0xe0 },
{ "gcc_gp3_clk", &gcc.mux, 0xe1 },
{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 0xe2 },
{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 0xe3 },
{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 0xe4 },
{ "gcc_pcie_0_aux_clk", &gcc.mux, 0xe5 },
{ "gcc_pcie_0_pipe_clk", &gcc.mux, 0xe6 },
{ "gcc_pcie_phy_aux_clk", &gcc.mux, 0xe8 },
{ "gcc_ufs_axi_clk", &gcc.mux, 0xea },
{ "gcc_ufs_ahb_clk", &gcc.mux, 0xeb },
{ "gcc_ufs_tx_symbol_0_clk", &gcc.mux, 0xec },
{ "gcc_ufs_rx_symbol_0_clk", &gcc.mux, 0xed },
{ "gcc_ufs_rx_symbol_1_clk", &gcc.mux, 0x162 },
{ "gcc_ufs_unipro_core_clk", &gcc.mux, 0xf0 },
{ "gcc_ufs_ice_core_clk", &gcc.mux, 0xf1 },
{ "gcc_dcc_ahb_clk", &gcc.mux, 0x119 },
{ "ipa_clk", &gcc.mux, 0x11b },
{ "gcc_mss_cfg_ahb_clk", &gcc.mux, 0x11f },
{ "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 0x124 },
{ "gcc_mss_mnoc_bimc_axi_clk", &gcc.mux, 0x120 },
{ "gcc_mss_snoc_axi_clk", &gcc.mux, 0x123 },
{ "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x13b },
{ "gcc_gpu_bimc_gfx_clk", &gcc.mux, 0x13f },
{ "gcc_qspi_ahb_clk", &gcc.mux, 0x156 },
{ "gcc_qspi_ref_clk", &gcc.mux, 0x157 },
{ "mmss_mnoc_ahb_clk", &gcc, 0x22, &mm_cc, 0x1 },
{ "mmss_misc_ahb_clk", &gcc, 0x22, &mm_cc, 0x3 },
{ "mmss_vmem_maxi_clk", &gcc, 0x22, &mm_cc, 0x9 },
{ "mmss_vmem_ahb_clk", &gcc, 0x22, &mm_cc, 0xa },
{ "mmss_bimc_smmu_ahb_clk", &gcc, 0x22, &mm_cc, 0xc },
{ "mmss_bimc_smmu_axi_clk", &gcc, 0x22, &mm_cc, 0xd },
{ "mmss_video_core_clk", &gcc, 0x22, &mm_cc, 0xe },
{ "mmss_video_axi_clk", &gcc, 0x22, &mm_cc, 0xf },
{ "mmss_video_maxi_clk", &gcc, 0x22, &mm_cc, 0x10 },
{ "mmss_video_ahb_clk", &gcc, 0x22, &mm_cc, 0x11 },
{ "mmss_mdss_rot_clk", &gcc, 0x22, &mm_cc, 0x12 },
{ "mmss_snoc_dvm_axi_clk", &gcc, 0x22, &mm_cc, 0x13 },
{ "mmss_mdss_mdp_clk", &gcc, 0x22, &mm_cc, 0x14 },
{ "mmss_mdss_mdp_lut_clk", &gcc, 0x22, &mm_cc, 0x15 },
{ "mmss_mdss_pclk0_clk", &gcc, 0x22, &mm_cc, 0x16 },
{ "mmss_mdss_pclk1_clk", &gcc, 0x22, &mm_cc, 0x17 },
{ "mmss_mdss_extpclk_clk", &gcc, 0x22, &mm_cc, 0x18 },
{ "mmss_video_subcore0_clk", &gcc, 0x22, &mm_cc, 0x1a },
{ "mmss_video_subcore1_clk", &gcc, 0x22, &mm_cc, 0x1b },
{ "mmss_mdss_vsync_clk", &gcc, 0x22, &mm_cc, 0x1c },
{ "mmss_mdss_hdmi_clk", &gcc, 0x22, &mm_cc, 0x1d },
{ "mmss_mdss_byte0_clk", &gcc, 0x22, &mm_cc, 0x1e },
{ "mmss_mdss_byte1_clk", &gcc, 0x22, &mm_cc, 0x1f },
{ "mmss_mdss_esc0_clk", &gcc, 0x22, &mm_cc, 0x20 },
{ "mmss_mdss_esc1_clk", &gcc, 0x22, &mm_cc, 0x21 },
{ "mmss_mdss_ahb_clk", &gcc, 0x22, &mm_cc, 0x22 },
{ "mmss_mdss_hdmi_dp_ahb_clk", &gcc, 0x22, &mm_cc, 0x23 },
{ "mmss_mdss_axi_clk", &gcc, 0x22, &mm_cc, 0x24 },
{ "mmss_camss_top_ahb_clk", &gcc, 0x22, &mm_cc, 0x25 },
{ "mmss_camss_micro_ahb_clk", &gcc, 0x22, &mm_cc, 0x26 },
{ "mmss_camss_gp0_clk", &gcc, 0x22, &mm_cc, 0x27 },
{ "mmss_camss_gp1_clk", &gcc, 0x22, &mm_cc, 0x28 },
{ "mmss_camss_mclk0_clk", &gcc, 0x22, &mm_cc, 0x29 },
{ "mmss_camss_mclk1_clk", &gcc, 0x22, &mm_cc, 0x2a },
{ "mmss_camss_mclk2_clk", &gcc, 0x22, &mm_cc, 0x2b },
{ "mmss_camss_mclk3_clk", &gcc, 0x22, &mm_cc, 0x2c },
{ "mmss_camss_cci_clk", &gcc, 0x22, &mm_cc, 0x2d },
{ "mmss_camss_cci_ahb_clk", &gcc, 0x22, &mm_cc, 0x2e },
{ "mmss_camss_csi0phytimer_clk", &gcc, 0x22, &mm_cc, 0x2f },
{ "mmss_camss_csi1phytimer_clk", &gcc, 0x22, &mm_cc, 0x30 },
{ "mmss_camss_csi2phytimer_clk", &gcc, 0x22, &mm_cc, 0x31 },
{ "mmss_camss_jpeg0_clk", &gcc, 0x22, &mm_cc, 0x32 },
{ "mmss_camss_ispif_ahb_clk", &gcc, 0x22, &mm_cc, 0x33 },
{ "mmss_camss_jpeg_ahb_clk", &gcc, 0x22, &mm_cc, 0x35 },
{ "mmss_camss_jpeg_axi_clk", &gcc, 0x22, &mm_cc, 0x36 },
{ "mmss_camss_ahb_clk", &gcc, 0x22, &mm_cc, 0x37 },
{ "mmss_camss_vfe0_clk", &gcc, 0x22, &mm_cc, 0x38 },
{ "mmss_camss_vfe1_clk", &gcc, 0x22, &mm_cc, 0x39 },
{ "mmss_camss_cpp_clk", &gcc, 0x22, &mm_cc, 0x3a },
{ "mmss_camss_cpp_ahb_clk", &gcc, 0x22, &mm_cc, 0x3b },
{ "mmss_camss_csi_vfe0_clk", &gcc, 0x22, &mm_cc, 0x3f },
{ "mmss_camss_csi_vfe1_clk", &gcc, 0x22, &mm_cc, 0x40 },
{ "mmss_camss_csi0_clk", &gcc, 0x22, &mm_cc, 0x41 },
{ "mmss_camss_csi0_ahb_clk", &gcc, 0x22, &mm_cc, 0x42 },
{ "mmss_camss_csiphy0_clk", &gcc, 0x22, &mm_cc, 0x43 },
{ "mmss_camss_csi0rdi_clk", &gcc, 0x22, &mm_cc, 0x44 },
{ "mmss_camss_csi0pix_clk", &gcc, 0x22, &mm_cc, 0x45 },
{ "mmss_camss_csi1_clk", &gcc, 0x22, &mm_cc, 0x46 },
{ "mmss_camss_csi1_ahb_clk", &gcc, 0x22, &mm_cc, 0x47 },
{ "mmss_camss_csi1rdi_clk", &gcc, 0x22, &mm_cc, 0x49 },
{ "mmss_camss_csi1pix_clk", &gcc, 0x22, &mm_cc, 0x4a },
{ "mmss_camss_csi2_clk", &gcc, 0x22, &mm_cc, 0x4b },
{ "mmss_camss_csi2_ahb_clk", &gcc, 0x22, &mm_cc, 0x4c },
{ "mmss_camss_csi2rdi_clk", &gcc, 0x22, &mm_cc, 0x4e },
{ "mmss_camss_csi2pix_clk", &gcc, 0x22, &mm_cc, 0x4f },
{ "mmss_camss_csi3_clk", &gcc, 0x22, &mm_cc, 0x50 },
{ "mmss_camss_csi3_ahb_clk", &gcc, 0x22, &mm_cc, 0x51 },
{ "mmss_camss_csi3rdi_clk", &gcc, 0x22, &mm_cc, 0x53 },
{ "mmss_camss_csi3pix_clk", &gcc, 0x22, &mm_cc, 0x54 },
{ "mmss_mnoc_maxi_clk", &gcc, 0x22, &mm_cc, 0x70 },
{ "mmss_camss_vfe0_stream_clk", &gcc, 0x22, &mm_cc, 0x71 },
{ "mmss_camss_vfe1_stream_clk", &gcc, 0x22, &mm_cc, 0x72 },
{ "mmss_camss_cpp_vbif_ahb_clk", &gcc, 0x22, &mm_cc, 0x73 },
{ "mmss_misc_cxo_clk", &gcc, 0x22, &mm_cc, 0x77 },
{ "mmss_camss_cpp_axi_clk", &gcc, 0x22, &mm_cc, 0x7a },
{ "mmss_camss_csiphy1_clk", &gcc, 0x22, &mm_cc, 0x85 },
{ "mmss_camss_vfe0_ahb_clk", &gcc, 0x22, &mm_cc, 0x86 },
{ "mmss_camss_vfe1_ahb_clk", &gcc, 0x22, &mm_cc, 0x87 },
{ "mmss_camss_csiphy2_clk", &gcc, 0x22, &mm_cc, 0x88 },
{ "mmss_fd_core_clk", &gcc, 0x22, &mm_cc, 0x89 },
{ "mmss_fd_core_uar_clk", &gcc, 0x22, &mm_cc, 0x8a },
{ "mmss_fd_ahb_clk", &gcc, 0x22, &mm_cc, 0x8c },
{ "mmss_camss_cphy_csid0_clk", &gcc, 0x22, &mm_cc, 0x8d },
{ "mmss_camss_cphy_csid1_clk", &gcc, 0x22, &mm_cc, 0x8e },
{ "mmss_camss_cphy_csid2_clk", &gcc, 0x22, &mm_cc, 0x8f },
{ "mmss_camss_cphy_csid3_clk", &gcc, 0x22, &mm_cc, 0x90 },
{ "mmss_mdss_dp_link_clk", &gcc, 0x22, &mm_cc, 0x98 },
{ "mmss_mdss_dp_link_intf_clk", &gcc, 0x22, &mm_cc, 0x99 },
{ "mmss_mdss_dp_crypto_clk", &gcc, 0x22, &mm_cc, 0x9a },
{ "mmss_mdss_dp_pixel_clk", &gcc, 0x22, &mm_cc, 0x9b },
{ "mmss_mdss_dp_aux_clk", &gcc, 0x22, &mm_cc, 0x9c },
{ "mmss_mdss_dp_gtc_clk", &gcc, 0x22, &mm_cc, 0x9d },
{ "mmss_mdss_byte0_intf_clk", &gcc, 0x22, &mm_cc, 0xad },
{ "mmss_mdss_byte1_intf_clk", &gcc, 0x22, &mm_cc, 0xae },
{ "mmss_mnoc_ahb_clk", &mm_cc, 0x1 },
{ "mmss_misc_ahb_clk", &mm_cc, 0x3 },
{ "mmss_vmem_maxi_clk", &mm_cc, 0x9 },
{ "mmss_vmem_ahb_clk", &mm_cc, 0xa },
{ "mmss_bimc_smmu_ahb_clk", &mm_cc, 0xc },
{ "mmss_bimc_smmu_axi_clk", &mm_cc, 0xd },
{ "mmss_video_core_clk", &mm_cc, 0xe },
{ "mmss_video_axi_clk", &mm_cc, 0xf },
{ "mmss_video_maxi_clk", &mm_cc, 0x10 },
{ "mmss_video_ahb_clk", &mm_cc, 0x11 },
{ "mmss_mdss_rot_clk", &mm_cc, 0x12 },
{ "mmss_snoc_dvm_axi_clk", &mm_cc, 0x13 },
{ "mmss_mdss_mdp_clk", &mm_cc, 0x14 },
{ "mmss_mdss_mdp_lut_clk", &mm_cc, 0x15 },
{ "mmss_mdss_pclk0_clk", &mm_cc, 0x16 },
{ "mmss_mdss_pclk1_clk", &mm_cc, 0x17 },
{ "mmss_mdss_extpclk_clk", &mm_cc, 0x18 },
{ "mmss_video_subcore0_clk", &mm_cc, 0x1a },
{ "mmss_video_subcore1_clk", &mm_cc, 0x1b },
{ "mmss_mdss_vsync_clk", &mm_cc, 0x1c },
{ "mmss_mdss_hdmi_clk", &mm_cc, 0x1d },
{ "mmss_mdss_byte0_clk", &mm_cc, 0x1e },
{ "mmss_mdss_byte1_clk", &mm_cc, 0x1f },
{ "mmss_mdss_esc0_clk", &mm_cc, 0x20 },
{ "mmss_mdss_esc1_clk", &mm_cc, 0x21 },
{ "mmss_mdss_ahb_clk", &mm_cc, 0x22 },
{ "mmss_mdss_hdmi_dp_ahb_clk", &mm_cc, 0x23 },
{ "mmss_mdss_axi_clk", &mm_cc, 0x24 },
{ "mmss_camss_top_ahb_clk", &mm_cc, 0x25 },
{ "mmss_camss_micro_ahb_clk", &mm_cc, 0x26 },
{ "mmss_camss_gp0_clk", &mm_cc, 0x27 },
{ "mmss_camss_gp1_clk", &mm_cc, 0x28 },
{ "mmss_camss_mclk0_clk", &mm_cc, 0x29 },
{ "mmss_camss_mclk1_clk", &mm_cc, 0x2a },
{ "mmss_camss_mclk2_clk", &mm_cc, 0x2b },
{ "mmss_camss_mclk3_clk", &mm_cc, 0x2c },
{ "mmss_camss_cci_clk", &mm_cc, 0x2d },
{ "mmss_camss_cci_ahb_clk", &mm_cc, 0x2e },
{ "mmss_camss_csi0phytimer_clk", &mm_cc, 0x2f },
{ "mmss_camss_csi1phytimer_clk", &mm_cc, 0x30 },
{ "mmss_camss_csi2phytimer_clk", &mm_cc, 0x31 },
{ "mmss_camss_jpeg0_clk", &mm_cc, 0x32 },
{ "mmss_camss_ispif_ahb_clk", &mm_cc, 0x33 },
{ "mmss_camss_jpeg_ahb_clk", &mm_cc, 0x35 },
{ "mmss_camss_jpeg_axi_clk", &mm_cc, 0x36 },
{ "mmss_camss_ahb_clk", &mm_cc, 0x37 },
{ "mmss_camss_vfe0_clk", &mm_cc, 0x38 },
{ "mmss_camss_vfe1_clk", &mm_cc, 0x39 },
{ "mmss_camss_cpp_clk", &mm_cc, 0x3a },
{ "mmss_camss_cpp_ahb_clk", &mm_cc, 0x3b },
{ "mmss_camss_csi_vfe0_clk", &mm_cc, 0x3f },
{ "mmss_camss_csi_vfe1_clk", &mm_cc, 0x40 },
{ "mmss_camss_csi0_clk", &mm_cc, 0x41 },
{ "mmss_camss_csi0_ahb_clk", &mm_cc, 0x42 },
{ "mmss_camss_csiphy0_clk", &mm_cc, 0x43 },
{ "mmss_camss_csi0rdi_clk", &mm_cc, 0x44 },
{ "mmss_camss_csi0pix_clk", &mm_cc, 0x45 },
{ "mmss_camss_csi1_clk", &mm_cc, 0x46 },
{ "mmss_camss_csi1_ahb_clk", &mm_cc, 0x47 },
{ "mmss_camss_csi1rdi_clk", &mm_cc, 0x49 },
{ "mmss_camss_csi1pix_clk", &mm_cc, 0x4a },
{ "mmss_camss_csi2_clk", &mm_cc, 0x4b },
{ "mmss_camss_csi2_ahb_clk", &mm_cc, 0x4c },
{ "mmss_camss_csi2rdi_clk", &mm_cc, 0x4e },
{ "mmss_camss_csi2pix_clk", &mm_cc, 0x4f },
{ "mmss_camss_csi3_clk", &mm_cc, 0x50 },
{ "mmss_camss_csi3_ahb_clk", &mm_cc, 0x51 },
{ "mmss_camss_csi3rdi_clk", &mm_cc, 0x53 },
{ "mmss_camss_csi3pix_clk", &mm_cc, 0x54 },
{ "mmss_mnoc_maxi_clk", &mm_cc, 0x70 },
{ "mmss_camss_vfe0_stream_clk", &mm_cc, 0x71 },
{ "mmss_camss_vfe1_stream_clk", &mm_cc, 0x72 },
{ "mmss_camss_cpp_vbif_ahb_clk", &mm_cc, 0x73 },
{ "mmss_misc_cxo_clk", &mm_cc, 0x77 },
{ "mmss_camss_cpp_axi_clk", &mm_cc, 0x7a },
{ "mmss_camss_csiphy1_clk", &mm_cc, 0x85 },
{ "mmss_camss_vfe0_ahb_clk", &mm_cc, 0x86 },
{ "mmss_camss_vfe1_ahb_clk", &mm_cc, 0x87 },
{ "mmss_camss_csiphy2_clk", &mm_cc, 0x88 },
{ "mmss_fd_core_clk", &mm_cc, 0x89 },
{ "mmss_fd_core_uar_clk", &mm_cc, 0x8a },
{ "mmss_fd_ahb_clk", &mm_cc, 0x8c },
{ "mmss_camss_cphy_csid0_clk", &mm_cc, 0x8d },
{ "mmss_camss_cphy_csid1_clk", &mm_cc, 0x8e },
{ "mmss_camss_cphy_csid2_clk", &mm_cc, 0x8f },
{ "mmss_camss_cphy_csid3_clk", &mm_cc, 0x90 },
{ "mmss_mdss_dp_link_clk", &mm_cc, 0x98 },
{ "mmss_mdss_dp_link_intf_clk", &mm_cc, 0x99 },
{ "mmss_mdss_dp_crypto_clk", &mm_cc, 0x9a },
{ "mmss_mdss_dp_pixel_clk", &mm_cc, 0x9b },
{ "mmss_mdss_dp_aux_clk", &mm_cc, 0x9c },
{ "mmss_mdss_dp_gtc_clk", &mm_cc, 0x9d },
{ "mmss_mdss_byte0_intf_clk", &mm_cc, 0xad },
{ "mmss_mdss_byte1_intf_clk", &mm_cc, 0xae },
{ "gpucc_rbcpr_clk", &gcc, 0x13d, &gpu_cc, 0x3 },
{ "gpucc_rbbmtimer_clk", &gcc, 0x13d, &gpu_cc, 0x5 },
{ "gpucc_gfx3d_isense_clk", &gcc, 0x13d, &gpu_cc, 0xa },
{ "gpucc_rbcpr_clk", &gpu_cc, 0x3 },
{ "gpucc_rbbmtimer_clk", &gpu_cc, 0x5 },
{ "gpucc_gfx3d_isense_clk", &gpu_cc, 0xa },
{}
};

288
qcs404.c
View File

@@ -33,6 +33,7 @@
#include <errno.h>
#include <fcntl.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
@@ -49,147 +50,190 @@
#define GCC_CLOCK_FREQ_MEASURE_STATUS 0x74008
#define GCC_XO_DIV4_CBCR 0x30034
static struct debug_mux gcc;
struct turing_mux {
struct debug_mux mux;
static struct debug_mux gcc = {
.phys = GCC_BASE,
.size = GCC_SIZE,
unsigned int ahb_reg;
unsigned int ahb_mask;
};
.enable_reg = GCC_DEBUG_CLK_CTL,
.enable_mask = BIT(16),
unsigned long measure_turing(const struct measure_clk *clk,
const struct debug_mux *mux);
.mux_reg = GCC_DEBUG_CLK_CTL,
.mux_mask = 0x1ff,
static struct gcc_mux gcc = {
.mux = {
.phys = GCC_BASE,
.size = GCC_SIZE,
.div_reg = GCC_DEBUG_CLK_CTL,
.div_shift = 12,
.div_mask = 0xf << 12,
.div_val = 4,
.measure = measure_gcc,
.enable_reg = GCC_DEBUG_CLK_CTL,
.enable_mask = BIT(16),
.mux_reg = GCC_DEBUG_CLK_CTL,
.mux_mask = 0x1ff,
.div_reg = GCC_DEBUG_CLK_CTL,
.div_shift = 12,
.div_mask = 0xf << 12,
.div_val = 4,
},
.xo_div4_reg = GCC_XO_DIV4_CBCR,
.debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL,
.debug_status_reg = GCC_CLOCK_FREQ_MEASURE_STATUS,
};
static struct debug_mux turing = {
.phys = 0x800000,
.size = 0x30000,
static struct turing_mux turing = {
.mux = {
.phys = 0x800000,
.size = 0x30000,
.enable_reg = 0x22008,
.enable_mask = BIT(0),
.measure = measure_turing,
.parent = &gcc.mux,
.parent_mux_val = 50,
.mux_reg = 0x22000,
.mux_mask = 0xffff,
.enable_reg = 0x22008,
.enable_mask = BIT(0),
.div_mask = 0,
.mux_reg = 0x22000,
.mux_mask = 0xffff,
},
.ahb_reg = 0x5e004,
.ahb_mask = BIT(31),
};
static bool leaf_enabled(struct turing_mux *leaf)
{
uint32_t val;
/* If no AHB clock is specified, we assume it's clocked */
if (!leaf || !leaf->ahb_mask)
return true;
/* we know that the parent is GCC, we read AHB reg from GCC */
val = readl(leaf->mux.parent->base + leaf->ahb_reg);
val &= leaf->ahb_mask;
/* CLK_OFF will be set if block is not clocked, so inverse */
return !val;
}
unsigned long measure_turing(const struct measure_clk *clk,
const struct debug_mux *mux)
{
struct turing_mux *turing = container_of(mux, struct turing_mux, mux);
if (!leaf_enabled(turing))
return 0;
return measure_leaf(clk, mux);
}
static struct measure_clk qcs404_clocks[] = {
{ "snoc_clk", &gcc, 0 },
{ "gcc_sys_noc_usb3_clk", &gcc, 1 },
{ "pnoc_clk", &gcc, 8 },
{ "gcc_pcnoc_usb2_clk", &gcc, 9 },
{ "gcc_pcnoc_usb3_clk", &gcc, 10 },
{ "gcc_gp1_clk", &gcc, 16 },
{ "gcc_gp2_clk", &gcc, 17 },
{ "gcc_gp3_clk", &gcc, 18 },
{ "gcc_bimc_gfx_clk", &gcc, 45 },
{ "aon_clk_src", &gcc, 50, &turing, 1},
{ "turing_wrapper_aon_clk", &gcc, 50, &turing, 2},
{ "turing_wrapper_cnoc_sway_aon_clk", &gcc, 50, &turing, 3},
{ "turing_wrapper_qos_ahbs_aon_clk", &gcc, 50, &turing, 4},
{ "q6ss_ahbm_aon_clk", &gcc, 50, &turing, 5},
{ "q6ss_ahbs_aon_clk", &gcc, 50, &turing, 6},
{ "turing_wrapper_bus_timeout_aon_clk", &gcc, 50, &turing, 7},
{ "turing_wrapper_rscc_aon_clk", &gcc, 50, &turing, 8},
{ "q6ss_alt_reset_aon_clk", &gcc, 50, &turing, 10},
{ "qos_fixed_lat_counter_clk_src", &gcc, 50, &turing, 11},
{ "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &gcc, 50, &turing, 12},
{ "turing_wrapper_qos_danger_fixed_lat_counter_clk", &gcc, 50, &turing, 13},
{ "q6_xo_clk_src", &gcc, 50, &turing, 14},
{ "qos_xo_clk_src", &gcc, 50, &turing, 15},
{ "turing_wrapper_qos_xo_lat_counter_clk", &gcc, 50, &turing, 16},
{ "bcr_slp_clk_src", &gcc, 50, &turing, 19},
{ "q6ss_bcr_slp_clk", &gcc, 50, &turing, 20},
{ "turing_wrapper_cnoc_ahbs_clk", &gcc, 50, &turing, 28},
{ "q6ss_q6_axim_clk", &gcc, 50, &turing, 29},
{ "q6ss_sleep_clk_src", &gcc, 50, &turing, 33},
{ "qdsp6ss_xo_clk", &gcc, 50, &turing, 36},
{ "qdsp6ss_sleep_clk", &gcc, 50, &turing, 37},
{ "q6ss_dbg_in_clk", &gcc, 50, &turing, 39},
{ "gcc_usb_hs_system_clk", &gcc, 96 },
{ "gcc_usb_hs_inactivity_timers_clk", &gcc, 98 },
{ "gcc_usb2a_phy_sleep_clk", &gcc, 99 },
{ "gcc_usb_hs_phy_cfg_ahb_clk", &gcc, 100 },
{ "gcc_usb20_mock_utmi_clk", &gcc, 101 },
{ "gcc_sdcc1_apps_clk", &gcc, 104 },
{ "gcc_sdcc1_ahb_clk", &gcc, 105 },
{ "gcc_sdcc1_ice_core_clk", &gcc, 106 },
{ "gcc_sdcc2_apps_clk", &gcc, 112 },
{ "gcc_sdcc2_ahb_clk", &gcc, 113 },
{ "gcc_usb30_master_clk", &gcc, 120 },
{ "gcc_usb30_sleep_clk", &gcc, 121 },
{ "gcc_usb30_mock_utmi_clk", &gcc, 122 },
{ "gcc_usb3_phy_pipe_clk", &gcc, 123 },
{ "gcc_usb3_phy_aux_clk", &gcc, 124 },
{ "gcc_eth_axi_clk", &gcc, 128 },
{ "gcc_eth_rgmii_clk", &gcc, 129 },
{ "gcc_eth_slave_ahb_clk", &gcc, 130 },
{ "gcc_eth_ptp_clk", &gcc, 131 },
{ "gcc_blsp1_ahb_clk", &gcc, 136 },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138 },
{ "wcnss_m_clk", &gcc, 138 },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139 },
{ "gcc_blsp1_uart1_apps_clk", &gcc, 140 },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142 },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 143 },
{ "gcc_blsp1_uart2_apps_clk", &gcc, 144 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc, 146 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 147 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc, 148 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 149 },
{ "gcc_blsp1_uart3_apps_clk", &gcc, 150 },
{ "gcc_blsp1_qup0_spi_apps_clk", &gcc, 152 },
{ "gcc_blsp1_qup0_i2c_apps_clk", &gcc, 153 },
{ "gcc_blsp1_uart0_apps_clk", &gcc, 154 },
{ "gcc_blsp2_ahb_clk", &gcc, 160 },
{ "gcc_blsp2_qup0_i2c_apps_clk", &gcc, 162 },
{ "gcc_blsp2_qup0_spi_apps_clk", &gcc, 163 },
{ "gcc_blsp2_uart0_apps_clk", &gcc, 164 },
{ "gcc_pcie_0_slv_axi_clk", &gcc, 168 },
{ "gcc_pcie_0_mstr_axi_clk", &gcc, 169 },
{ "gcc_pcie_0_cfg_ahb_clk", &gcc, 170 },
{ "gcc_pcie_0_aux_clk", &gcc, 171 },
{ "gcc_pcie_0_pipe_clk", &gcc, 172 },
//{ "pcie0_pipe_clk", &gcc, 173, 1 },
{ "qpic_clk", &gcc, 192 },
{ "gcc_pdm_ahb_clk", &gcc, 208 },
{ "gcc_pdm2_clk", &gcc, 210 },
{ "gcc_pwm0_xo512_clk", &gcc, 211 },
{ "gcc_pwm1_xo512_clk", &gcc, 212 },
{ "gcc_pwm2_xo512_clk", &gcc, 213 },
{ "gcc_prng_ahb_clk", &gcc, 216 },
{ "gcc_geni_ir_s_clk", &gcc, 238 },
{ "gcc_boot_rom_ahb_clk", &gcc, 248 },
{ "ce1_clk", &gcc, 312 },
{ "bimc_clk", &gcc, 346 },
//{ "bimc_fsm_ddr_clk", &gcc, 350, 1 },
{ "gcc_apss_ahb_clk", &gcc, 360 },
{ "gcc_dcc_clk", &gcc, 441 },
{ "gcc_oxili_gfx3d_clk", &gcc, 490 },
{ "gcc_oxili_ahb_clk", &gcc, 491 },
{ "gcc_mdss_hdmi_pclk_clk", &gcc, 497 },
{ "gcc_mdss_hdmi_app_clk", &gcc, 498 },
{ "gcc_mdss_ahb_clk", &gcc, 502 },
{ "gcc_mdss_axi_clk", &gcc, 503 },
{ "gcc_mdss_pclk0_clk", &gcc, 504 },
{ "gcc_mdss_mdp_clk", &gcc, 505 },
{ "gcc_mdss_vsync_clk", &gcc, 507 },
{ "gcc_mdss_byte0_clk", &gcc, 508 },
{ "gcc_mdss_esc0_clk", &gcc, 509 },
{ "snoc_clk", &gcc.mux, 0 },
{ "gcc_sys_noc_usb3_clk", &gcc.mux, 1 },
{ "pnoc_clk", &gcc.mux, 8 },
{ "gcc_pcnoc_usb2_clk", &gcc.mux, 9 },
{ "gcc_pcnoc_usb3_clk", &gcc.mux, 10 },
{ "gcc_gp1_clk", &gcc.mux, 16 },
{ "gcc_gp2_clk", &gcc.mux, 17 },
{ "gcc_gp3_clk", &gcc.mux, 18 },
{ "gcc_bimc_gfx_clk", &gcc.mux, 45 },
{ "aon_clk_src", &turing.mux, 1},
{ "turing_wrapper_aon_clk", &turing.mux, 2},
{ "turing_wrapper_cnoc_sway_aon_clk", &turing.mux, 3},
{ "turing_wrapper_qos_ahbs_aon_clk", &turing.mux, 4},
{ "q6ss_ahbm_aon_clk", &turing.mux, 5},
{ "q6ss_ahbs_aon_clk", &turing.mux, 6},
{ "turing_wrapper_bus_timeout_aon_clk", &turing.mux, 7},
{ "turing_wrapper_rscc_aon_clk", &turing.mux, 8},
{ "q6ss_alt_reset_aon_clk", &turing.mux, 10},
{ "qos_fixed_lat_counter_clk_src", &turing.mux, 11},
{ "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &turing.mux, 12},
{ "turing_wrapper_qos_danger_fixed_lat_counter_clk", &turing.mux, 13},
{ "q6_xo_clk_src", &turing.mux, 14},
{ "qos_xo_clk_src", &turing.mux, 15},
{ "turing_wrapper_qos_xo_lat_counter_clk", &turing.mux, 16},
{ "bcr_slp_clk_src", &turing.mux, 19},
{ "q6ss_bcr_slp_clk", &turing.mux, 20},
{ "turing_wrapper_cnoc_ahbs_clk", &turing.mux, 28},
{ "q6ss_q6_axim_clk", &turing.mux, 29},
{ "q6ss_sleep_clk_src", &turing.mux, 33},
{ "qdsp6ss_xo_clk", &turing.mux, 36},
{ "qdsp6ss_sleep_clk", &turing.mux, 37},
{ "q6ss_dbg_in_clk", &turing.mux, 39},
{ "gcc_usb_hs_system_clk", &gcc.mux, 96 },
{ "gcc_usb_hs_inactivity_timers_clk", &gcc.mux, 98 },
{ "gcc_usb2a_phy_sleep_clk", &gcc.mux, 99 },
{ "gcc_usb_hs_phy_cfg_ahb_clk", &gcc.mux, 100 },
{ "gcc_usb20_mock_utmi_clk", &gcc.mux, 101 },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 104 },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 105 },
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 106 },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 112 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 113 },
{ "gcc_usb30_master_clk", &gcc.mux, 120 },
{ "gcc_usb30_sleep_clk", &gcc.mux, 121 },
{ "gcc_usb30_mock_utmi_clk", &gcc.mux, 122 },
{ "gcc_usb3_phy_pipe_clk", &gcc.mux, 123 },
{ "gcc_usb3_phy_aux_clk", &gcc.mux, 124 },
{ "gcc_eth_axi_clk", &gcc.mux, 128 },
{ "gcc_eth_rgmii_clk", &gcc.mux, 129 },
{ "gcc_eth_slave_ahb_clk", &gcc.mux, 130 },
{ "gcc_eth_ptp_clk", &gcc.mux, 131 },
{ "gcc_blsp1_ahb_clk", &gcc.mux, 136 },
{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 138 },
{ "wcnss_m_clk", &gcc.mux, 138 },
{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 139 },
{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 140 },
{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 142 },
{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 143 },
{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 144 },
{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 146 },
{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 147 },
{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 148 },
{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 149 },
{ "gcc_blsp1_uart3_apps_clk", &gcc.mux, 150 },
{ "gcc_blsp1_qup0_spi_apps_clk", &gcc.mux, 152 },
{ "gcc_blsp1_qup0_i2c_apps_clk", &gcc.mux, 153 },
{ "gcc_blsp1_uart0_apps_clk", &gcc.mux, 154 },
{ "gcc_blsp2_ahb_clk", &gcc.mux, 160 },
{ "gcc_blsp2_qup0_i2c_apps_clk", &gcc.mux, 162 },
{ "gcc_blsp2_qup0_spi_apps_clk", &gcc.mux, 163 },
{ "gcc_blsp2_uart0_apps_clk", &gcc.mux, 164 },
{ "gcc_pcie_0_slv_axi_clk", &gcc.mux, 168 },
{ "gcc_pcie_0_mstr_axi_clk", &gcc.mux, 169 },
{ "gcc_pcie_0_cfg_ahb_clk", &gcc.mux, 170 },
{ "gcc_pcie_0_aux_clk", &gcc.mux, 171 },
{ "gcc_pcie_0_pipe_clk", &gcc.mux, 172 },
//{ "pcie0_pipe_clk", &gcc.mux, 173, 1 },
{ "qpic_clk", &gcc.mux, 192 },
{ "gcc_pdm_ahb_clk", &gcc.mux, 208 },
{ "gcc_pdm2_clk", &gcc.mux, 210 },
{ "gcc_pwm0_xo512_clk", &gcc.mux, 211 },
{ "gcc_pwm1_xo512_clk", &gcc.mux, 212 },
{ "gcc_pwm2_xo512_clk", &gcc.mux, 213 },
{ "gcc_prng_ahb_clk", &gcc.mux, 216 },
{ "gcc_geni_ir_s_clk", &gcc.mux, 238 },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 248 },
{ "ce1_clk", &gcc.mux, 312 },
{ "bimc_clk", &gcc.mux, 346 },
//{ "bimc_fsm_ddr_clk", &gcc.mux, 350, 1 },
{ "gcc_apss_ahb_clk", &gcc.mux, 360 },
{ "gcc_dcc_clk", &gcc.mux, 441 },
{ "gcc_oxili_gfx3d_clk", &gcc.mux, 490 },
{ "gcc_oxili_ahb_clk", &gcc.mux, 491 },
{ "gcc_mdss_hdmi_pclk_clk", &gcc.mux, 497 },
{ "gcc_mdss_hdmi_app_clk", &gcc.mux, 498 },
{ "gcc_mdss_ahb_clk", &gcc.mux, 502 },
{ "gcc_mdss_axi_clk", &gcc.mux, 503 },
{ "gcc_mdss_pclk0_clk", &gcc.mux, 504 },
{ "gcc_mdss_mdp_clk", &gcc.mux, 505 },
{ "gcc_mdss_vsync_clk", &gcc.mux, 507 },
{ "gcc_mdss_byte0_clk", &gcc.mux, 508 },
{ "gcc_mdss_esc0_clk", &gcc.mux, 509 },
{}
};

688
sc8280xp.c
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File diff suppressed because it is too large Load Diff

536
sdm845.c
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File diff suppressed because it is too large Load Diff

301
sm6115.c
View File

@@ -12,11 +12,38 @@
#include "debugcc.h"
static struct gcc_mux gcc = {
.mux = {
.phys = 0x1400000,
.size = 0x1f0000,
.measure = measure_gcc,
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.div_reg = 0x30000,
.div_mask = 0xf,
.div_val = 4,
},
.xo_div4_reg = 0x28008,
.debug_ctl_reg = 0x62038,
.debug_status_reg = 0x6203c,
};
static struct debug_mux cpu_cc = {
.phys = 0xf111000,
.size = 0x1000,
.block_name = "cpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0xaf,
.enable_reg = 0x1c,
.enable_mask = BIT(0),
@@ -34,6 +61,10 @@ static struct debug_mux disp_cc = {
.size = 0x20000,
.block_name = "disp",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x42,
.enable_reg = 0x500c,
.enable_mask = BIT(0),
@@ -45,30 +76,15 @@ static struct debug_mux disp_cc = {
.div_val = 4,
};
static struct debug_mux gcc = {
.phys = 0x1400000,
.size = 0x1f0000,
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.div_reg = 0x30000,
.div_mask = 0xf,
.div_val = 4,
.xo_div4_reg = 0x28008,
.debug_ctl_reg = 0x62038,
.debug_status_reg = 0x6203c,
};
static struct debug_mux gpu_cc = {
.phys = 0x5990000,
.size = 0x9000,
.block_name = "gpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0xe7,
.enable_reg = 0x1100,
.enable_mask = BIT(0),
@@ -81,131 +97,128 @@ static struct debug_mux gpu_cc = {
};
static struct measure_clk sm6115_clocks[] = {
{ "perfcl_clk", &gcc, 0xaf, &cpu_cc, 0x1 },
{ "pwrcl_clk", &gcc, 0xaf, &cpu_cc, 0x0 },
//{ "cpu_cc_debug_mux", &gcc, 0xaf },
//{ "disp_cc_debug_mux", &gcc, 0x42 },
{ "gcc_ahb2phy_csi_clk", &gcc, 0x63 },
{ "gcc_ahb2phy_usb_clk", &gcc, 0x64 },
{ "gcc_bimc_gpu_axi_clk", &gcc, 0x90 },
{ "gcc_boot_rom_ahb_clk", &gcc, 0x76 },
{ "gcc_cam_throttle_nrt_clk", &gcc, 0x4c },
{ "gcc_cam_throttle_rt_clk", &gcc, 0x4b },
{ "gcc_camera_ahb_clk", &gcc, 0x37 },
{ "gcc_camera_xo_clk", &gcc, 0x3f },
{ "gcc_camss_axi_clk", &gcc, 0x136 },
{ "gcc_camss_camnoc_atb_clk", &gcc, 0x138 },
{ "gcc_camss_camnoc_nts_xo_clk", &gcc, 0x139 },
{ "gcc_camss_cci_0_clk", &gcc, 0x134 },
{ "gcc_camss_cphy_0_clk", &gcc, 0x128 },
{ "gcc_camss_cphy_1_clk", &gcc, 0x129 },
{ "gcc_camss_cphy_2_clk", &gcc, 0x12a },
{ "gcc_camss_csi0phytimer_clk", &gcc, 0x11a },
{ "gcc_camss_csi1phytimer_clk", &gcc, 0x11b },
{ "gcc_camss_csi2phytimer_clk", &gcc, 0x11c },
{ "gcc_camss_mclk0_clk", &gcc, 0x11d },
{ "gcc_camss_mclk1_clk", &gcc, 0x11e },
{ "gcc_camss_mclk2_clk", &gcc, 0x11f },
{ "gcc_camss_mclk3_clk", &gcc, 0x120 },
{ "gcc_camss_nrt_axi_clk", &gcc, 0x13a },
{ "gcc_camss_ope_ahb_clk", &gcc, 0x133 },
{ "gcc_camss_ope_clk", &gcc, 0x131 },
{ "gcc_camss_rt_axi_clk", &gcc, 0x13c },
{ "gcc_camss_tfe_0_clk", &gcc, 0x121 },
{ "gcc_camss_tfe_0_cphy_rx_clk", &gcc, 0x125 },
{ "gcc_camss_tfe_0_csid_clk", &gcc, 0x12b },
{ "gcc_camss_tfe_1_clk", &gcc, 0x122 },
{ "gcc_camss_tfe_1_cphy_rx_clk", &gcc, 0x126 },
{ "gcc_camss_tfe_1_csid_clk", &gcc, 0x12d },
{ "gcc_camss_tfe_2_clk", &gcc, 0x123 },
{ "gcc_camss_tfe_2_cphy_rx_clk", &gcc, 0x127 },
{ "gcc_camss_tfe_2_csid_clk", &gcc, 0x12f },
{ "gcc_camss_top_ahb_clk", &gcc, 0x135 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1d },
{ "gcc_cpuss_gnoc_clk", &gcc, 0xaa },
{ "gcc_disp_ahb_clk", &gcc, 0x38 },
{ "gcc_disp_gpll0_div_clk_src", &gcc, 0x47 },
{ "gcc_disp_hf_axi_clk", &gcc, 0x3d },
{ "gcc_disp_throttle_core_clk", &gcc, 0x49 },
{ "gcc_disp_xo_clk", &gcc, 0x40 },
{ "gcc_gp1_clk", &gcc, 0xba },
{ "gcc_gp2_clk", &gcc, 0xbb },
{ "gcc_gp3_clk", &gcc, 0xbc },
{ "gcc_gpu_cfg_ahb_clk", &gcc, 0xe5 },
{ "gcc_gpu_gpll0_clk_src", &gcc, 0xeb },
{ "gcc_gpu_gpll0_div_clk_src", &gcc, 0xec },
{ "gcc_gpu_memnoc_gfx_clk", &gcc, 0xe8 },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0xea },
{ "gcc_gpu_throttle_core_clk", &gcc, 0xef },
{ "gcc_pdm2_clk", &gcc, 0x73 },
{ "gcc_pdm_ahb_clk", &gcc, 0x71 },
{ "gcc_pdm_xo4_clk", &gcc, 0x72 },
{ "gcc_prng_ahb_clk", &gcc, 0x74 },
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x3a },
{ "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x48 },
{ "gcc_qmip_disp_ahb_clk", &gcc, 0x3b },
{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc, 0xed },
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x39 },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6a },
{ "gcc_qupv3_wrap0_core_clk", &gcc, 0x69 },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x67 },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x68 },
{ "gcc_sdcc1_ahb_clk", &gcc, 0xf3 },
{ "gcc_sdcc1_apps_clk", &gcc, 0xf2 },
{ "gcc_sdcc1_ice_core_clk", &gcc, 0xf4 },
{ "gcc_sdcc2_ahb_clk", &gcc, 0x66 },
{ "gcc_sdcc2_apps_clk", &gcc, 0x65 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 },
{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc, 0x19 },
{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc, 0x18 },
{ "gcc_ufs_phy_ahb_clk", &gcc, 0x111 },
{ "gcc_ufs_phy_axi_clk", &gcc, 0x110 },
{ "gcc_ufs_phy_ice_core_clk", &gcc, 0x117 },
{ "gcc_ufs_phy_phy_aux_clk", &gcc, 0x118 },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x113 },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x112 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc, 0x116 },
{ "gcc_usb30_prim_master_clk", &gcc, 0x5c },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5e },
{ "gcc_usb30_prim_sleep_clk", &gcc, 0x5d },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5f },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x60 },
{ "gcc_vcodec0_axi_clk", &gcc, 0x142 },
{ "gcc_venus_ahb_clk", &gcc, 0x143 },
{ "gcc_venus_ctl_axi_clk", &gcc, 0x141 },
{ "gcc_video_ahb_clk", &gcc, 0x36 },
{ "gcc_video_axi0_clk", &gcc, 0x3c },
{ "gcc_video_throttle_core_clk", &gcc, 0x4a },
{ "gcc_video_vcodec0_sys_clk", &gcc, 0x13f },
{ "gcc_video_venus_ctl_clk", &gcc, 0x13d },
{ "gcc_video_xo_clk", &gcc, 0x3e },
//{ "gpu_cc_debug_mux", &gcc, 0xe7 },
//{ "mc_cc_debug_mux", &gcc, 0x9e },
{ "measure_only_cnoc_clk", &gcc, 0x1a },
{ "measure_only_ipa_2x_clk", &gcc, 0xc6 },
{ "measure_only_snoc_clk", &gcc, 0x7 },
{ "disp_cc_mdss_ahb_clk", &gcc, 0x42, &disp_cc, 0x1a },
{ "disp_cc_mdss_byte0_clk", &gcc, 0x42, &disp_cc, 0x12 },
{ "disp_cc_mdss_byte0_intf_clk", &gcc, 0x42, &disp_cc, 0x13 },
{ "disp_cc_mdss_esc0_clk", &gcc, 0x42, &disp_cc, 0x14 },
{ "disp_cc_mdss_mdp_clk", &gcc, 0x42, &disp_cc, 0xe },
{ "disp_cc_mdss_mdp_lut_clk", &gcc, 0x42, &disp_cc, 0x10 },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x42, &disp_cc, 0x1b },
{ "disp_cc_mdss_pclk0_clk", &gcc, 0x42, &disp_cc, 0xd },
{ "disp_cc_mdss_rot_clk", &gcc, 0x42, &disp_cc, 0xf },
{ "disp_cc_mdss_vsync_clk", &gcc, 0x42, &disp_cc, 0x11 },
{ "disp_cc_sleep_clk", &gcc, 0x42, &disp_cc, 0x24 },
{ "disp_cc_xo_clk", &gcc, 0x42, &disp_cc, 0x23 },
{ "gpu_cc_ahb_clk", &gcc, 0xe7, &gpu_cc, 0x10 },
{ "gpu_cc_crc_ahb_clk", &gcc, 0xe7, &gpu_cc, 0x11 },
{ "gpu_cc_cx_gfx3d_clk", &gcc, 0xe7, &gpu_cc, 0x1a },
{ "gpu_cc_cx_gmu_clk", &gcc, 0xe7, &gpu_cc, 0x18 },
{ "gpu_cc_cx_snoc_dvm_clk", &gcc, 0xe7, &gpu_cc, 0x15 },
{ "gpu_cc_cxo_aon_clk", &gcc, 0xe7, &gpu_cc, 0xa },
{ "gpu_cc_cxo_clk", &gcc, 0xe7, &gpu_cc, 0x19 },
{ "gpu_cc_gx_cxo_clk", &gcc, 0xe7, &gpu_cc, 0xe },
{ "gpu_cc_gx_gfx3d_clk", &gcc, 0xe7, &gpu_cc, 0xb },
{ "gpu_cc_sleep_clk", &gcc, 0xe7, &gpu_cc, 0x16 },
//{ "mc_cc_debug_mux", &gcc.mux, 0x9e },
{ "perfcl_clk", &cpu_cc, 0x1 },
{ "pwrcl_clk", &cpu_cc, 0x0 },
{ "gcc_ahb2phy_csi_clk", &gcc.mux, 0x63 },
{ "gcc_ahb2phy_usb_clk", &gcc.mux, 0x64 },
{ "gcc_bimc_gpu_axi_clk", &gcc.mux, 0x90 },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x76 },
{ "gcc_cam_throttle_nrt_clk", &gcc.mux, 0x4c },
{ "gcc_cam_throttle_rt_clk", &gcc.mux, 0x4b },
{ "gcc_camera_ahb_clk", &gcc.mux, 0x37 },
{ "gcc_camera_xo_clk", &gcc.mux, 0x3f },
{ "gcc_camss_axi_clk", &gcc.mux, 0x136 },
{ "gcc_camss_camnoc_atb_clk", &gcc.mux, 0x138 },
{ "gcc_camss_camnoc_nts_xo_clk", &gcc.mux, 0x139 },
{ "gcc_camss_cci_0_clk", &gcc.mux, 0x134 },
{ "gcc_camss_cphy_0_clk", &gcc.mux, 0x128 },
{ "gcc_camss_cphy_1_clk", &gcc.mux, 0x129 },
{ "gcc_camss_cphy_2_clk", &gcc.mux, 0x12a },
{ "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x11a },
{ "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x11b },
{ "gcc_camss_csi2phytimer_clk", &gcc.mux, 0x11c },
{ "gcc_camss_mclk0_clk", &gcc.mux, 0x11d },
{ "gcc_camss_mclk1_clk", &gcc.mux, 0x11e },
{ "gcc_camss_mclk2_clk", &gcc.mux, 0x11f },
{ "gcc_camss_mclk3_clk", &gcc.mux, 0x120 },
{ "gcc_camss_nrt_axi_clk", &gcc.mux, 0x13a },
{ "gcc_camss_ope_ahb_clk", &gcc.mux, 0x133 },
{ "gcc_camss_ope_clk", &gcc.mux, 0x131 },
{ "gcc_camss_rt_axi_clk", &gcc.mux, 0x13c },
{ "gcc_camss_tfe_0_clk", &gcc.mux, 0x121 },
{ "gcc_camss_tfe_0_cphy_rx_clk", &gcc.mux, 0x125 },
{ "gcc_camss_tfe_0_csid_clk", &gcc.mux, 0x12b },
{ "gcc_camss_tfe_1_clk", &gcc.mux, 0x122 },
{ "gcc_camss_tfe_1_cphy_rx_clk", &gcc.mux, 0x126 },
{ "gcc_camss_tfe_1_csid_clk", &gcc.mux, 0x12d },
{ "gcc_camss_tfe_2_clk", &gcc.mux, 0x123 },
{ "gcc_camss_tfe_2_cphy_rx_clk", &gcc.mux, 0x127 },
{ "gcc_camss_tfe_2_csid_clk", &gcc.mux, 0x12f },
{ "gcc_camss_top_ahb_clk", &gcc.mux, 0x135 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1d },
{ "gcc_cpuss_gnoc_clk", &gcc.mux, 0xaa },
{ "gcc_disp_ahb_clk", &gcc.mux, 0x38 },
{ "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x47 },
{ "gcc_disp_hf_axi_clk", &gcc.mux, 0x3d },
{ "gcc_disp_throttle_core_clk", &gcc.mux, 0x49 },
{ "gcc_disp_xo_clk", &gcc.mux, 0x40 },
{ "gcc_gp1_clk", &gcc.mux, 0xba },
{ "gcc_gp2_clk", &gcc.mux, 0xbb },
{ "gcc_gp3_clk", &gcc.mux, 0xbc },
{ "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xe5 },
{ "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xeb },
{ "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0xec },
{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xe8 },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xea },
{ "gcc_gpu_throttle_core_clk", &gcc.mux, 0xef },
{ "gcc_pdm2_clk", &gcc.mux, 0x73 },
{ "gcc_pdm_ahb_clk", &gcc.mux, 0x71 },
{ "gcc_pdm_xo4_clk", &gcc.mux, 0x72 },
{ "gcc_prng_ahb_clk", &gcc.mux, 0x74 },
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x3a },
{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x48 },
{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3b },
{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0xed },
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x39 },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x6a },
{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x69 },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x67 },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x68 },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0xf3 },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0xf2 },
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0xf4 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x66 },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x65 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 },
{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc.mux, 0x19 },
{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x18 },
{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x111 },
{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0x110 },
{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x117 },
{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x118 },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x113 },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x112 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x116 },
{ "gcc_usb30_prim_master_clk", &gcc.mux, 0x5c },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x5e },
{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5d },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x5f },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x60 },
{ "gcc_vcodec0_axi_clk", &gcc.mux, 0x142 },
{ "gcc_venus_ahb_clk", &gcc.mux, 0x143 },
{ "gcc_venus_ctl_axi_clk", &gcc.mux, 0x141 },
{ "gcc_video_ahb_clk", &gcc.mux, 0x36 },
{ "gcc_video_axi0_clk", &gcc.mux, 0x3c },
{ "gcc_video_throttle_core_clk", &gcc.mux, 0x4a },
{ "gcc_video_vcodec0_sys_clk", &gcc.mux, 0x13f },
{ "gcc_video_venus_ctl_clk", &gcc.mux, 0x13d },
{ "gcc_video_xo_clk", &gcc.mux, 0x3e },
{ "measure_only_cnoc_clk", &gcc.mux, 0x1a },
{ "measure_only_ipa_2x_clk", &gcc.mux, 0xc6 },
{ "measure_only_snoc_clk", &gcc.mux, 0x7 },
{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x1a },
{ "disp_cc_mdss_byte0_clk", &disp_cc, 0x12 },
{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x13 },
{ "disp_cc_mdss_esc0_clk", &disp_cc, 0x14 },
{ "disp_cc_mdss_mdp_clk", &disp_cc, 0xe },
{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x10 },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x1b },
{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0xd },
{ "disp_cc_mdss_rot_clk", &disp_cc, 0xf },
{ "disp_cc_mdss_vsync_clk", &disp_cc, 0x11 },
{ "disp_cc_sleep_clk", &disp_cc, 0x24 },
{ "disp_cc_xo_clk", &disp_cc, 0x23 },
{ "gpu_cc_ahb_clk", &gpu_cc, 0x10 },
{ "gpu_cc_crc_ahb_clk", &gpu_cc, 0x11 },
{ "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a },
{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x18 },
{ "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x15 },
{ "gpu_cc_cxo_aon_clk", &gpu_cc, 0xa },
{ "gpu_cc_cxo_clk", &gpu_cc, 0x19 },
{ "gpu_cc_gx_cxo_clk", &gpu_cc, 0xe },
{ "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xb },
{ "gpu_cc_sleep_clk", &gpu_cc, 0x16 },
{}
};

444
sm6125.c
View File

@@ -12,11 +12,36 @@
#include "debugcc.h"
static struct gcc_mux gcc = {
.mux = {
.phys = 0x1400000,
.size = 0x1f0000,
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.div_reg = 0x30000,
.div_mask = 0xf,
.div_val = 1,
},
.xo_div4_reg = 0x28008,
.debug_ctl_reg = 0x62038,
.debug_status_reg = 0x6203c,
};
static struct debug_mux cpu_cc = {
.phys = 0xf111000,
.size = 0x1000,
.block_name = "cpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0xab,
.enable_reg = 0x1c,
.enable_mask = BIT(0),
@@ -30,30 +55,15 @@ static struct debug_mux cpu_cc = {
.div_val = 8,
};
static struct debug_mux gcc = {
.phys = 0x1400000,
.size = 0x1f0000,
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.div_reg = 0x30000,
.div_mask = 0xf,
.div_val = 1,
.xo_div4_reg = 0x28008,
.debug_ctl_reg = 0x62038,
.debug_status_reg = 0x6203c,
};
static struct debug_mux disp_cc = {
.phys = 0x5f00000,
.size = 0x20000,
.block_name = "disp",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x41,
.enable_reg = 0x500c,
.enable_mask = BIT(0),
@@ -70,6 +80,10 @@ static struct debug_mux gpu_cc = {
.size = 0x9000,
.block_name = "gpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0xdd,
.enable_reg = 0x1100,
.enable_mask = BIT(0),
@@ -86,6 +100,10 @@ static struct debug_mux video_cc = {
.size = 0x10000,
.block_name = "video",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x42,
.enable_reg = 0x1100,
.enable_mask = BIT(0),
@@ -98,203 +116,203 @@ static struct debug_mux video_cc = {
};
static struct measure_clk sm6125_clocks[] = {
{ "perfcl_clk", &gcc, 0xab, &cpu_cc, 0x1 },
{ "pwrcl_clk", &gcc, 0xab, &cpu_cc, 0x0 },
{ "snoc_clk", &gcc, 0x7 },
{ "bimc_clk", &gcc, 0x97 },
{ "pnoc_clk", &gcc, 0x11 },
{ "gcc_ahb2phy_csi_clk", &gcc, 0x5f },
{ "gcc_ahb2phy_usb_clk", &gcc, 0x60 },
{ "gcc_apc_vs_clk", &gcc, 0xbf },
{ "gcc_boot_rom_ahb_clk", &gcc, 0x72 },
{ "gcc_camera_ahb_clk", &gcc, 0x36 },
{ "gcc_camera_xo_clk", &gcc, 0x3e },
{ "gcc_camss_cci_ahb_clk", &gcc, 0x11f },
{ "gcc_camss_cci_clk", &gcc, 0x11e },
{ "gcc_camss_cphy_csid0_clk", &gcc, 0x13a },
{ "gcc_camss_cphy_csid1_clk", &gcc, 0x140 },
{ "gcc_camss_cphy_csid2_clk", &gcc, 0x145 },
{ "gcc_camss_cphy_csid3_clk", &gcc, 0x14b },
{ "gcc_camss_cpp_ahb_clk", &gcc, 0x154 },
{ "gcc_camss_cpp_axi_clk", &gcc, 0x156 },
{ "gcc_camss_cpp_clk", &gcc, 0x153 },
{ "gcc_camss_cpp_tsctr_clk", &gcc, 0x158 },
{ "gcc_camss_cpp_vbif_ahb_clk", &gcc, 0x155 },
{ "gcc_camss_csi0_ahb_clk", &gcc, 0x13b },
{ "gcc_camss_csi0_clk", &gcc, 0x139 },
{ "gcc_camss_csi0phytimer_clk", &gcc, 0x120 },
{ "gcc_camss_csi0pix_clk", &gcc, 0x13d },
{ "gcc_camss_csi0rdi_clk", &gcc, 0x13c },
{ "gcc_camss_csi1_ahb_clk", &gcc, 0x141 },
{ "gcc_camss_csi1_clk", &gcc, 0x13f },
{ "gcc_camss_csi1phytimer_clk", &gcc, 0x121 },
{ "gcc_camss_csi1pix_clk", &gcc, 0x143 },
{ "gcc_camss_csi1rdi_clk", &gcc, 0x142 },
{ "gcc_camss_csi2_ahb_clk", &gcc, 0x146 },
{ "gcc_camss_csi2_clk", &gcc, 0x144 },
{ "gcc_camss_csi2phytimer_clk", &gcc, 0x122 },
{ "gcc_camss_csi2pix_clk", &gcc, 0x148 },
{ "gcc_camss_csi2rdi_clk", &gcc, 0x147 },
{ "gcc_camss_csi3_ahb_clk", &gcc, 0x14c },
{ "gcc_camss_csi3_clk", &gcc, 0x14a },
{ "gcc_camss_csi3pix_clk", &gcc, 0x14e },
{ "gcc_camss_csi3rdi_clk", &gcc, 0x14d },
{ "gcc_camss_csi_vfe0_clk", &gcc, 0x12e },
{ "gcc_camss_csi_vfe1_clk", &gcc, 0x12f },
{ "gcc_camss_csiphy0_clk", &gcc, 0x135 },
{ "gcc_camss_csiphy1_clk", &gcc, 0x136 },
{ "gcc_camss_csiphy2_clk", &gcc, 0x137 },
{ "gcc_camss_csiphy3_clk", &gcc, 0x138 },
{ "gcc_camss_gp0_clk", &gcc, 0x118 },
{ "gcc_camss_gp1_clk", &gcc, 0x119 },
{ "gcc_camss_ispif_ahb_clk", &gcc, 0x134 },
{ "gcc_camss_jpeg_ahb_clk", &gcc, 0x124 },
{ "gcc_camss_jpeg_axi_clk", &gcc, 0x125 },
{ "gcc_camss_jpeg_clk", &gcc, 0x123 },
{ "gcc_camss_jpeg_tsctr_clk", &gcc, 0x127 },
{ "gcc_camss_mclk0_clk", &gcc, 0x11a },
{ "gcc_camss_mclk1_clk", &gcc, 0x11b },
{ "gcc_camss_mclk2_clk", &gcc, 0x11c },
{ "gcc_camss_mclk3_clk", &gcc, 0x11d },
{ "gcc_camss_micro_ahb_clk", &gcc, 0x152 },
{ "gcc_camss_throttle_nrt_axi_clk", &gcc, 0x150 },
{ "gcc_camss_throttle_rt_axi_clk", &gcc, 0x151 },
{ "gcc_camss_top_ahb_clk", &gcc, 0x14f },
{ "gcc_camss_vfe0_ahb_clk", &gcc, 0x12a },
{ "gcc_camss_vfe0_clk", &gcc, 0x128 },
{ "gcc_camss_vfe0_stream_clk", &gcc, 0x129 },
{ "gcc_camss_vfe1_ahb_clk", &gcc, 0x12d },
{ "gcc_camss_vfe1_clk", &gcc, 0x12b },
{ "gcc_camss_vfe1_stream_clk", &gcc, 0x12c },
{ "gcc_camss_vfe_tsctr_clk", &gcc, 0x133 },
{ "gcc_camss_vfe_vbif_ahb_clk", &gcc, 0x130 },
{ "gcc_camss_vfe_vbif_axi_clk", &gcc, 0x131 },
{ "gcc_ce1_ahb_clk", &gcc, 0x82 },
{ "gcc_ce1_axi_clk", &gcc, 0x81 },
{ "gcc_ce1_clk", &gcc, 0x80 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1d },
{ "gcc_cpuss_ahb_clk", &gcc, 0xa5 },
{ "gcc_cpuss_gnoc_clk", &gcc, 0xa6 },
{ "gcc_cpuss_throttle_core_clk", &gcc, 0xae },
{ "gcc_cpuss_throttle_xo_clk", &gcc, 0xad },
{ "gcc_disp_ahb_clk", &gcc, 0x37 },
{ "gcc_disp_gpll0_div_clk_src", &gcc, 0x46 },
{ "gcc_disp_hf_axi_clk", &gcc, 0x3c },
{ "gcc_disp_throttle_core_clk", &gcc, 0x48 },
{ "gcc_disp_xo_clk", &gcc, 0x3f },
{ "gcc_gp1_clk", &gcc, 0xb6 },
{ "gcc_gp2_clk", &gcc, 0xb7 },
{ "gcc_gp3_clk", &gcc, 0xb8 },
{ "gcc_gpu_cfg_ahb_clk", &gcc, 0xdb },
{ "gcc_gpu_gpll0_clk_src", &gcc, 0xe1 },
{ "gcc_gpu_gpll0_div_clk_src", &gcc, 0xe2 },
{ "gcc_gpu_memnoc_gfx_clk", &gcc, 0xde },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0xe0 },
{ "gcc_gpu_throttle_core_clk", &gcc, 0xe5 },
{ "gcc_gpu_throttle_xo_clk", &gcc, 0xe4 },
{ "gcc_mss_vs_clk", &gcc, 0xbe },
{ "gcc_pdm2_clk", &gcc, 0x6f },
{ "gcc_pdm_ahb_clk", &gcc, 0x6d },
{ "gcc_pdm_xo4_clk", &gcc, 0x6e },
{ "gcc_prng_ahb_clk", &gcc, 0x70 },
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x39 },
{ "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x47 },
{ "gcc_qmip_cpuss_cfg_ahb_clk", &gcc, 0xac },
{ "gcc_qmip_disp_ahb_clk", &gcc, 0x3a },
{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc, 0xe3 },
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x38 },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x66 },
{ "gcc_qupv3_wrap0_core_clk", &gcc, 0x65 },
{ "gcc_qupv3_wrap0_s0_clk", &gcc, 0x67 },
{ "gcc_qupv3_wrap0_s1_clk", &gcc, 0x68 },
{ "gcc_qupv3_wrap0_s2_clk", &gcc, 0x69 },
{ "gcc_qupv3_wrap0_s3_clk", &gcc, 0x6a },
{ "gcc_qupv3_wrap0_s4_clk", &gcc, 0x6b },
{ "gcc_qupv3_wrap0_s5_clk", &gcc, 0x6c },
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0xed },
{ "gcc_qupv3_wrap1_core_clk", &gcc, 0xec },
{ "gcc_qupv3_wrap1_s0_clk", &gcc, 0xee },
{ "gcc_qupv3_wrap1_s1_clk", &gcc, 0xef },
{ "gcc_qupv3_wrap1_s2_clk", &gcc, 0xf0 },
{ "gcc_qupv3_wrap1_s3_clk", &gcc, 0xf1 },
{ "gcc_qupv3_wrap1_s4_clk", &gcc, 0xf2 },
{ "gcc_qupv3_wrap1_s5_clk", &gcc, 0xf3 },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x63 },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x64 },
{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0xea },
{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0xeb },
{ "gcc_sdcc1_ahb_clk", &gcc, 0xe8 },
{ "gcc_sdcc1_apps_clk", &gcc, 0xe7 },
{ "gcc_sdcc1_ice_core_clk", &gcc, 0xe9 },
{ "gcc_sdcc2_ahb_clk", &gcc, 0x62 },
{ "gcc_sdcc2_apps_clk", &gcc, 0x61 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9, },
{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc, 0x19 },
{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc, 0x18 },
{ "gcc_ufs_phy_ahb_clk", &gcc, 0x10f },
{ "gcc_ufs_phy_axi_clk", &gcc, 0x10e },
{ "gcc_ufs_phy_ice_core_clk", &gcc, 0x115 },
{ "gcc_ufs_phy_phy_aux_clk", &gcc, 0x116 },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x111 },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x110 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc, 0x114 },
{ "gcc_usb30_prim_master_clk", &gcc, 0x58 },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5a },
{ "gcc_usb30_prim_sleep_clk", &gcc, 0x59 },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5b },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x5c },
{ "gcc_vdda_vs_clk", &gcc, 0xbb },
{ "gcc_vddcx_vs_clk", &gcc, 0xb9 },
{ "gcc_vddmx_vs_clk", &gcc, 0xba },
{ "gcc_video_ahb_clk", &gcc, 0x35 },
{ "gcc_video_axi0_clk", &gcc, 0x3b },
{ "gcc_video_throttle_core_clk", &gcc, 0x49 },
{ "gcc_video_xo_clk", &gcc, 0x3d },
{ "gcc_vs_ctrl_ahb_clk", &gcc, 0xbd },
{ "gcc_vs_ctrl_clk", &gcc, 0xbc },
{ "gcc_wcss_vs_clk", &gcc, 0xc0 },
{ "measure_only_ipa_2x_clk", &gcc, 0xc2 },
{ "perfcl_clk", &cpu_cc, 0x1 },
{ "pwrcl_clk", &cpu_cc, 0x0 },
{ "snoc_clk", &gcc.mux, 0x7 },
{ "bimc_clk", &gcc.mux, 0x97 },
{ "pnoc_clk", &gcc.mux, 0x11 },
{ "gcc_ahb2phy_csi_clk", &gcc.mux, 0x5f },
{ "gcc_ahb2phy_usb_clk", &gcc.mux, 0x60 },
{ "gcc_apc_vs_clk", &gcc.mux, 0xbf },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x72 },
{ "gcc_camera_ahb_clk", &gcc.mux, 0x36 },
{ "gcc_camera_xo_clk", &gcc.mux, 0x3e },
{ "gcc_camss_cci_ahb_clk", &gcc.mux, 0x11f },
{ "gcc_camss_cci_clk", &gcc.mux, 0x11e },
{ "gcc_camss_cphy_csid0_clk", &gcc.mux, 0x13a },
{ "gcc_camss_cphy_csid1_clk", &gcc.mux, 0x140 },
{ "gcc_camss_cphy_csid2_clk", &gcc.mux, 0x145 },
{ "gcc_camss_cphy_csid3_clk", &gcc.mux, 0x14b },
{ "gcc_camss_cpp_ahb_clk", &gcc.mux, 0x154 },
{ "gcc_camss_cpp_axi_clk", &gcc.mux, 0x156 },
{ "gcc_camss_cpp_clk", &gcc.mux, 0x153 },
{ "gcc_camss_cpp_tsctr_clk", &gcc.mux, 0x158 },
{ "gcc_camss_cpp_vbif_ahb_clk", &gcc.mux, 0x155 },
{ "gcc_camss_csi0_ahb_clk", &gcc.mux, 0x13b },
{ "gcc_camss_csi0_clk", &gcc.mux, 0x139 },
{ "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x120 },
{ "gcc_camss_csi0pix_clk", &gcc.mux, 0x13d },
{ "gcc_camss_csi0rdi_clk", &gcc.mux, 0x13c },
{ "gcc_camss_csi1_ahb_clk", &gcc.mux, 0x141 },
{ "gcc_camss_csi1_clk", &gcc.mux, 0x13f },
{ "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x121 },
{ "gcc_camss_csi1pix_clk", &gcc.mux, 0x143 },
{ "gcc_camss_csi1rdi_clk", &gcc.mux, 0x142 },
{ "gcc_camss_csi2_ahb_clk", &gcc.mux, 0x146 },
{ "gcc_camss_csi2_clk", &gcc.mux, 0x144 },
{ "gcc_camss_csi2phytimer_clk", &gcc.mux, 0x122 },
{ "gcc_camss_csi2pix_clk", &gcc.mux, 0x148 },
{ "gcc_camss_csi2rdi_clk", &gcc.mux, 0x147 },
{ "gcc_camss_csi3_ahb_clk", &gcc.mux, 0x14c },
{ "gcc_camss_csi3_clk", &gcc.mux, 0x14a },
{ "gcc_camss_csi3pix_clk", &gcc.mux, 0x14e },
{ "gcc_camss_csi3rdi_clk", &gcc.mux, 0x14d },
{ "gcc_camss_csi_vfe0_clk", &gcc.mux, 0x12e },
{ "gcc_camss_csi_vfe1_clk", &gcc.mux, 0x12f },
{ "gcc_camss_csiphy0_clk", &gcc.mux, 0x135 },
{ "gcc_camss_csiphy1_clk", &gcc.mux, 0x136 },
{ "gcc_camss_csiphy2_clk", &gcc.mux, 0x137 },
{ "gcc_camss_csiphy3_clk", &gcc.mux, 0x138 },
{ "gcc_camss_gp0_clk", &gcc.mux, 0x118 },
{ "gcc_camss_gp1_clk", &gcc.mux, 0x119 },
{ "gcc_camss_ispif_ahb_clk", &gcc.mux, 0x134 },
{ "gcc_camss_jpeg_ahb_clk", &gcc.mux, 0x124 },
{ "gcc_camss_jpeg_axi_clk", &gcc.mux, 0x125 },
{ "gcc_camss_jpeg_clk", &gcc.mux, 0x123 },
{ "gcc_camss_jpeg_tsctr_clk", &gcc.mux, 0x127 },
{ "gcc_camss_mclk0_clk", &gcc.mux, 0x11a },
{ "gcc_camss_mclk1_clk", &gcc.mux, 0x11b },
{ "gcc_camss_mclk2_clk", &gcc.mux, 0x11c },
{ "gcc_camss_mclk3_clk", &gcc.mux, 0x11d },
{ "gcc_camss_micro_ahb_clk", &gcc.mux, 0x152 },
{ "gcc_camss_throttle_nrt_axi_clk", &gcc.mux, 0x150 },
{ "gcc_camss_throttle_rt_axi_clk", &gcc.mux, 0x151 },
{ "gcc_camss_top_ahb_clk", &gcc.mux, 0x14f },
{ "gcc_camss_vfe0_ahb_clk", &gcc.mux, 0x12a },
{ "gcc_camss_vfe0_clk", &gcc.mux, 0x128 },
{ "gcc_camss_vfe0_stream_clk", &gcc.mux, 0x129 },
{ "gcc_camss_vfe1_ahb_clk", &gcc.mux, 0x12d },
{ "gcc_camss_vfe1_clk", &gcc.mux, 0x12b },
{ "gcc_camss_vfe1_stream_clk", &gcc.mux, 0x12c },
{ "gcc_camss_vfe_tsctr_clk", &gcc.mux, 0x133 },
{ "gcc_camss_vfe_vbif_ahb_clk", &gcc.mux, 0x130 },
{ "gcc_camss_vfe_vbif_axi_clk", &gcc.mux, 0x131 },
{ "gcc_ce1_ahb_clk", &gcc.mux, 0x82 },
{ "gcc_ce1_axi_clk", &gcc.mux, 0x81 },
{ "gcc_ce1_clk", &gcc.mux, 0x80 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1d },
{ "gcc_cpuss_ahb_clk", &gcc.mux, 0xa5 },
{ "gcc_cpuss_gnoc_clk", &gcc.mux, 0xa6 },
{ "gcc_cpuss_throttle_core_clk", &gcc.mux, 0xae },
{ "gcc_cpuss_throttle_xo_clk", &gcc.mux, 0xad },
{ "gcc_disp_ahb_clk", &gcc.mux, 0x37 },
{ "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x46 },
{ "gcc_disp_hf_axi_clk", &gcc.mux, 0x3c },
{ "gcc_disp_throttle_core_clk", &gcc.mux, 0x48 },
{ "gcc_disp_xo_clk", &gcc.mux, 0x3f },
{ "gcc_gp1_clk", &gcc.mux, 0xb6 },
{ "gcc_gp2_clk", &gcc.mux, 0xb7 },
{ "gcc_gp3_clk", &gcc.mux, 0xb8 },
{ "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xdb },
{ "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xe1 },
{ "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0xe2 },
{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xde },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xe0 },
{ "gcc_gpu_throttle_core_clk", &gcc.mux, 0xe5 },
{ "gcc_gpu_throttle_xo_clk", &gcc.mux, 0xe4 },
{ "gcc_mss_vs_clk", &gcc.mux, 0xbe },
{ "gcc_pdm2_clk", &gcc.mux, 0x6f },
{ "gcc_pdm_ahb_clk", &gcc.mux, 0x6d },
{ "gcc_pdm_xo4_clk", &gcc.mux, 0x6e },
{ "gcc_prng_ahb_clk", &gcc.mux, 0x70 },
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x39 },
{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x47 },
{ "gcc_qmip_cpuss_cfg_ahb_clk", &gcc.mux, 0xac },
{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3a },
{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0xe3 },
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x38 },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x66 },
{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x65 },
{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x67 },
{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x68 },
{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x69 },
{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x6a },
{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x6b },
{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x6c },
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0xed },
{ "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0xec },
{ "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0xee },
{ "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0xef },
{ "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0xf0 },
{ "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0xf1 },
{ "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0xf2 },
{ "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0xf3 },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x63 },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x64 },
{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0xea },
{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0xeb },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0xe8 },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0xe7 },
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0xe9 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x62 },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x61 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9, },
{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc.mux, 0x19 },
{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x18 },
{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x10f },
{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0x10e },
{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x115 },
{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x116 },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x111 },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x110 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x114 },
{ "gcc_usb30_prim_master_clk", &gcc.mux, 0x58 },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x5a },
{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x59 },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x5b },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x5c },
{ "gcc_vdda_vs_clk", &gcc.mux, 0xbb },
{ "gcc_vddcx_vs_clk", &gcc.mux, 0xb9 },
{ "gcc_vddmx_vs_clk", &gcc.mux, 0xba },
{ "gcc_video_ahb_clk", &gcc.mux, 0x35 },
{ "gcc_video_axi0_clk", &gcc.mux, 0x3b },
{ "gcc_video_throttle_core_clk", &gcc.mux, 0x49 },
{ "gcc_video_xo_clk", &gcc.mux, 0x3d },
{ "gcc_vs_ctrl_ahb_clk", &gcc.mux, 0xbd },
{ "gcc_vs_ctrl_clk", &gcc.mux, 0xbc },
{ "gcc_wcss_vs_clk", &gcc.mux, 0xc0 },
{ "measure_only_ipa_2x_clk", &gcc.mux, 0xc2 },
{ "disp_cc_mdss_ahb_clk", &gcc, 0x41, &disp_cc, 0x1a },
{ "disp_cc_mdss_byte0_clk", &gcc, 0x41, &disp_cc, 0x12 },
{ "disp_cc_mdss_byte0_intf_clk", &gcc, 0x41, &disp_cc, 0x13 },
{ "disp_cc_mdss_dp_aux_clk", &gcc, 0x41, &disp_cc, 0x19 },
{ "disp_cc_mdss_dp_crypto_clk", &gcc, 0x41, &disp_cc, 0x17 },
{ "disp_cc_mdss_dp_link_clk", &gcc, 0x41, &disp_cc, 0x15 },
{ "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x41, &disp_cc, 0x16 },
{ "disp_cc_mdss_dp_pixel_clk", &gcc, 0x41, &disp_cc, 0x18 },
{ "disp_cc_mdss_esc0_clk", &gcc, 0x41, &disp_cc, 0x14 },
{ "disp_cc_mdss_mdp_clk", &gcc, 0x41, &disp_cc, 0xe, },
{ "disp_cc_mdss_mdp_lut_clk", &gcc, 0x41, &disp_cc, 0x10 },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x41, &disp_cc, 0x1b },
{ "disp_cc_mdss_pclk0_clk", &gcc, 0x41, &disp_cc, 0xd, },
{ "disp_cc_mdss_rot_clk", &gcc, 0x41, &disp_cc, 0xf, },
{ "disp_cc_mdss_vsync_clk", &gcc, 0x41, &disp_cc, 0x11 },
{ "disp_cc_sleep_clk", &gcc, 0x41, &disp_cc, 0x24 },
{ "disp_cc_xo_clk", &gcc, 0x41, &disp_cc, 0x23 },
{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x1a },
{ "disp_cc_mdss_byte0_clk", &disp_cc, 0x12 },
{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0x13 },
{ "disp_cc_mdss_dp_aux_clk", &disp_cc, 0x19 },
{ "disp_cc_mdss_dp_crypto_clk", &disp_cc, 0x17 },
{ "disp_cc_mdss_dp_link_clk", &disp_cc, 0x15 },
{ "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 0x16 },
{ "disp_cc_mdss_dp_pixel_clk", &disp_cc, 0x18 },
{ "disp_cc_mdss_esc0_clk", &disp_cc, 0x14 },
{ "disp_cc_mdss_mdp_clk", &disp_cc, 0xe, },
{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0x10 },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x1b },
{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0xd, },
{ "disp_cc_mdss_rot_clk", &disp_cc, 0xf, },
{ "disp_cc_mdss_vsync_clk", &disp_cc, 0x11 },
{ "disp_cc_sleep_clk", &disp_cc, 0x24 },
{ "disp_cc_xo_clk", &disp_cc, 0x23 },
{ "gpu_cc_ahb_clk", &gcc, 0xdd, &gpu_cc, 0x10 },
{ "gpu_cc_crc_ahb_clk", &gcc, 0xdd, &gpu_cc, 0x11 },
{ "gpu_cc_cx_apb_clk", &gcc, 0xdd, &gpu_cc, 0x14 },
{ "gpu_cc_cx_gfx3d_clk", &gcc, 0xdd, &gpu_cc, 0x1a },
{ "gpu_cc_cx_gfx3d_slv_clk", &gcc, 0xdd, &gpu_cc, 0x1b },
{ "gpu_cc_cx_gmu_clk", &gcc, 0xdd, &gpu_cc, 0x18 },
{ "gpu_cc_cx_snoc_dvm_clk", &gcc, 0xdd, &gpu_cc, 0x15 },
{ "gpu_cc_cxo_aon_clk", &gcc, 0xdd, &gpu_cc, 0xa },
{ "gpu_cc_cxo_clk", &gcc, 0xdd, &gpu_cc, 0x19 },
{ "gpu_cc_gx_cxo_clk", &gcc, 0xdd, &gpu_cc, 0xe },
{ "gpu_cc_gx_gfx3d_clk", &gcc, 0xdd, &gpu_cc, 0xb },
{ "gpu_cc_sleep_clk", &gcc, 0xdd, &gpu_cc, 0x16 },
{ "gpu_cc_ahb_clk", &gpu_cc, 0x10 },
{ "gpu_cc_crc_ahb_clk", &gpu_cc, 0x11 },
{ "gpu_cc_cx_apb_clk", &gpu_cc, 0x14 },
{ "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a },
{ "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b },
{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x18 },
{ "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x15 },
{ "gpu_cc_cxo_aon_clk", &gpu_cc, 0xa },
{ "gpu_cc_cxo_clk", &gpu_cc, 0x19 },
{ "gpu_cc_gx_cxo_clk", &gpu_cc, 0xe },
{ "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xb },
{ "gpu_cc_sleep_clk", &gpu_cc, 0x16 },
{ "video_cc_apb_clk", &gcc, 0x42, &video_cc, 0x8 },
{ "video_cc_at_clk", &gcc, 0x42, &video_cc, 0xb },
{ "video_cc_sleep_clk", &gcc, 0x42, &video_cc, 0xd },
{ "video_cc_vcodec0_axi_clk", &gcc, 0x42, &video_cc, 0x6 },
{ "video_cc_vcodec0_core_clk", &gcc, 0x42, &video_cc, 0x3 },
{ "video_cc_venus_ahb_clk", &gcc, 0x42, &video_cc, 0x9 },
{ "video_cc_venus_ctl_axi_clk", &gcc, 0x42, &video_cc, 0x5 },
{ "video_cc_venus_ctl_core_clk", &gcc, 0x42, &video_cc, 0x1 },
{ "video_cc_xo_clk", &gcc, 0x42, &video_cc, 0xc },
{ "video_cc_apb_clk", &video_cc, 0x8 },
{ "video_cc_at_clk", &video_cc, 0xb },
{ "video_cc_sleep_clk", &video_cc, 0xd },
{ "video_cc_vcodec0_axi_clk", &video_cc, 0x6 },
{ "video_cc_vcodec0_core_clk", &video_cc, 0x3 },
{ "video_cc_venus_ahb_clk", &video_cc, 0x9 },
{ "video_cc_venus_ctl_axi_clk", &video_cc, 0x5 },
{ "video_cc_venus_ctl_core_clk", &video_cc, 0x1 },
{ "video_cc_xo_clk", &video_cc, 0xc },
{}
};

321
sm6350.c
View File

@@ -12,11 +12,38 @@
#include "debugcc.h"
static struct gcc_mux gcc = {
.mux = {
.phys = 0x100000,
.size = 0x1f0000,
.measure = measure_gcc,
.enable_reg = 0x3500c,
.enable_mask = BIT(0),
.mux_reg = 0x35f08,
.mux_mask = 0x3ff,
.div_reg = 0x35008,
.div_mask = 0x7,
.div_val = 4,
},
.xo_div4_reg = 0x2c008,
.debug_ctl_reg = 0x35f24,
.debug_status_reg = 0x35f28,
};
static struct debug_mux cpu_cc = {
.phys = 0x182a0000,
.size = 0x1000,
.block_name = "cpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0xbe,
.enable_reg = 0x18,
.enable_mask = BIT(0),
@@ -35,6 +62,10 @@ static struct debug_mux disp_cc = {
.size = 0x20000,
.block_name = "disp",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x40,
.enable_reg = 0x3004,
.enable_mask = BIT(0),
@@ -46,30 +77,15 @@ static struct debug_mux disp_cc = {
.div_val = 4,
};
static struct debug_mux gcc = {
.phys = 0x100000,
.size = 0x1f0000,
.enable_reg = 0x3500c,
.enable_mask = BIT(0),
.mux_reg = 0x35f08,
.mux_mask = 0x3ff,
.div_reg = 0x35008,
.div_mask = 0x7,
.div_val = 4,
.xo_div4_reg = 0x2c008,
.debug_ctl_reg = 0x35f24,
.debug_status_reg = 0x35f28,
};
static struct debug_mux gpu_cc = {
.phys = 0x3d90000,
.size = 0x9000,
.block_name = "gpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x107,
.enable_reg = 0x1100,
.enable_mask = BIT(0),
@@ -87,147 +103,146 @@ static struct debug_mux mc_cc = {
.block_name = "mc",
.measure = measure_mccc,
.parent = &gcc.mux,
.parent_mux_val = 0xab,
};
static struct measure_clk sm6350_clocks[] = {
{ "l3_clk", &gcc, 0xbe, &cpu_cc, 0x41 },
{ "pwrcl_clk", &gcc, 0xbe, &cpu_cc, 0x21 },
{ "perfcl_clk", &gcc, 0xbe, &cpu_cc, 0x25 },
//{ "cam_cc_debug_mux", &gcc.mux, 0x3f },
//{ "npu_cc_debug_mux", &gcc.mux, 0x11a },
//{ "video_cc_debug_mux", &gcc.mux, 0x41 },
//{ "cam_cc_debug_mux", &gcc, 0x3f },
//{ "cpu_cc_debug_mux", &gcc, 0xbe },
//{ "disp_cc_debug_mux", &gcc, 0x40 },
{ "gcc_aggre_ufs_phy_axi_clk", &gcc, 0xe2 },
{ "gcc_aggre_usb3_prim_axi_clk", &gcc, 0xe1 },
{ "gcc_boot_rom_ahb_clk", &gcc, 0x80 },
{ "gcc_camera_ahb_clk", &gcc, 0x32 },
{ "gcc_camera_axi_clk", &gcc, 0x36 },
{ "gcc_camera_throttle_nrt_axi_clk", &gcc, 0x4a },
{ "gcc_camera_throttle_rt_axi_clk", &gcc, 0x39 },
{ "gcc_camera_xo_clk", &gcc, 0x3c },
{ "gcc_ce1_ahb_clk", &gcc, 0x92 },
{ "gcc_ce1_axi_clk", &gcc, 0x91 },
{ "gcc_ce1_clk", &gcc, 0x90 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x18 },
{ "gcc_cpuss_ahb_clk", &gcc, 0xb7 },
{ "gcc_cpuss_gnoc_clk", &gcc, 0xb8 },
{ "gcc_cpuss_rbcpr_clk", &gcc, 0xb9 },
{ "gcc_ddrss_gpu_axi_clk", &gcc, 0xa5 },
{ "gcc_disp_ahb_clk", &gcc, 0x33 },
{ "gcc_disp_axi_clk", &gcc, 0x37 },
{ "gcc_disp_cc_sleep_clk", &gcc, 0x49 },
{ "gcc_disp_cc_xo_clk", &gcc, 0x48 },
{ "gcc_disp_gpll0_clk", &gcc, 0x44 },
{ "gcc_disp_throttle_axi_clk", &gcc, 0x3a },
{ "gcc_disp_xo_clk", &gcc, 0x3d },
{ "gcc_gp1_clk", &gcc, 0xc5 },
{ "gcc_gp2_clk", &gcc, 0xc6 },
{ "gcc_gp3_clk", &gcc, 0xc7 },
{ "gcc_gpu_cfg_ahb_clk", &gcc, 0x105 },
{ "gcc_gpu_gpll0_clk", &gcc, 0x10b },
{ "gcc_gpu_gpll0_div_clk", &gcc, 0x10c },
{ "gcc_gpu_memnoc_gfx_clk", &gcc, 0x108 },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x109 },
{ "gcc_npu_axi_clk", &gcc, 0x116 },
{ "gcc_npu_bwmon_axi_clk", &gcc, 0x11c },
{ "gcc_npu_bwmon_dma_cfg_ahb_clk", &gcc, 0x11d },
{ "gcc_npu_bwmon_dsp_cfg_ahb_clk", &gcc, 0x11e },
{ "gcc_npu_cfg_ahb_clk", &gcc, 0x115 },
{ "gcc_npu_dma_clk", &gcc, 0x11b },
{ "gcc_npu_gpll0_clk", &gcc, 0x118 },
{ "gcc_npu_gpll0_div_clk", &gcc, 0x119 },
{ "gcc_pdm2_clk", &gcc, 0x7d },
{ "gcc_pdm_ahb_clk", &gcc, 0x7b },
{ "gcc_pdm_xo4_clk", &gcc, 0x7c },
{ "gcc_prng_ahb_clk", &gcc, 0x7e },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6a },
{ "gcc_qupv3_wrap0_core_clk", &gcc, 0x69 },
{ "gcc_qupv3_wrap0_s0_clk", &gcc, 0x6b },
{ "gcc_qupv3_wrap0_s1_clk", &gcc, 0x6c },
{ "gcc_qupv3_wrap0_s2_clk", &gcc, 0x6d },
{ "gcc_qupv3_wrap0_s3_clk", &gcc, 0x6e },
{ "gcc_qupv3_wrap0_s4_clk", &gcc, 0x6f },
{ "gcc_qupv3_wrap0_s5_clk", &gcc, 0x70 },
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x71 },
{ "gcc_qupv3_wrap1_core_clk", &gcc, 0x72 },
{ "gcc_qupv3_wrap1_s0_clk", &gcc, 0x75 },
{ "gcc_qupv3_wrap1_s1_clk", &gcc, 0x76 },
{ "gcc_qupv3_wrap1_s2_clk", &gcc, 0x77 },
{ "gcc_qupv3_wrap1_s3_clk", &gcc, 0x78 },
{ "gcc_qupv3_wrap1_s4_clk", &gcc, 0x79 },
{ "gcc_qupv3_wrap1_s5_clk", &gcc, 0x7a },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x67 },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x68 },
{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0x73 },
{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0x74 },
{ "gcc_sdcc1_ahb_clk", &gcc, 0x112 },
{ "gcc_sdcc1_apps_clk", &gcc, 0x113 },
{ "gcc_sdcc1_ice_core_clk", &gcc, 0x114 },
{ "gcc_sdcc2_ahb_clk", &gcc, 0x66 },
{ "gcc_sdcc2_apps_clk", &gcc, 0x65 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 },
{ "gcc_ufs_phy_ahb_clk", &gcc, 0xc8 },
{ "gcc_ufs_phy_axi_clk", &gcc, 0xcc },
{ "gcc_ufs_phy_ice_core_clk", &gcc, 0xd1 },
{ "gcc_ufs_phy_phy_aux_clk", &gcc, 0xd2 },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0xca },
{ "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0xcb },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0xc9 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc, 0xd0 },
{ "gcc_usb30_prim_master_clk", &gcc, 0x5b },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5d },
{ "gcc_usb30_prim_sleep_clk", &gcc, 0x5c },
{ "gcc_usb3_prim_phy_aux_clk", &gcc, 0x5e },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5f },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x60 },
{ "gcc_video_ahb_clk", &gcc, 0x31 },
{ "gcc_video_axi_clk", &gcc, 0x35 },
{ "gcc_video_throttle_axi_clk", &gcc, 0x38 },
{ "gcc_video_xo_clk", &gcc, 0x3b },
//{ "gpu_cc_debug_mux", &gcc, 0x107 },
//{ "mc_cc_debug_mux", &gcc, 0xab },
{ "measure_only_cnoc_clk", &gcc, 0x14 },
{ "measure_only_ipa_2x_clk", &gcc, 0xec },
{ "measure_only_snoc_clk", &gcc, 0x07 },
//{ "npu_cc_debug_mux", &gcc, 0x11a },
//{ "video_cc_debug_mux", &gcc, 0x41 },
{ "l3_clk", &cpu_cc, 0x41 },
{ "pwrcl_clk", &cpu_cc, 0x21 },
{ "perfcl_clk", &cpu_cc, 0x25 },
{ "disp_cc_mdss_ahb_clk", &gcc, 0x40, &disp_cc, 0x14 },
{ "disp_cc_mdss_byte0_clk", &gcc, 0x40, &disp_cc, 0xc },
{ "disp_cc_mdss_byte0_intf_clk", &gcc, 0x40, &disp_cc, 0xd },
{ "disp_cc_mdss_dp_aux_clk", &gcc, 0x40, &disp_cc, 0x13 },
{ "disp_cc_mdss_dp_crypto_clk", &gcc, 0x40, &disp_cc, 0x11 },
{ "disp_cc_mdss_dp_link_clk", &gcc, 0x40, &disp_cc, 0xf },
{ "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x40, &disp_cc, 0x10 },
{ "disp_cc_mdss_dp_pixel_clk", &gcc, 0x40, &disp_cc, 0x12 },
{ "disp_cc_mdss_esc0_clk", &gcc, 0x40, &disp_cc, 0xe },
{ "disp_cc_mdss_mdp_clk", &gcc, 0x40, &disp_cc, 0x8 },
{ "disp_cc_mdss_mdp_lut_clk", &gcc, 0x40, &disp_cc, 0xa },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x40, &disp_cc, 0x15 },
{ "disp_cc_mdss_pclk0_clk", &gcc, 0x40, &disp_cc, 0x7 },
{ "disp_cc_mdss_rot_clk", &gcc, 0x40, &disp_cc, 0x9 },
{ "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x40, &disp_cc, 0x17 },
{ "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x40, &disp_cc, 0x16 },
{ "disp_cc_mdss_vsync_clk", &gcc, 0x40, &disp_cc, 0xb },
{ "disp_cc_sleep_clk", &gcc, 0x40, &disp_cc, 0x1d },
{ "disp_cc_xo_clk", &gcc, 0x40, &disp_cc, 0x1e },
{ "gcc_aggre_ufs_phy_axi_clk", &gcc.mux, 0xe2 },
{ "gcc_aggre_usb3_prim_axi_clk", &gcc.mux, 0xe1 },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x80 },
{ "gcc_camera_ahb_clk", &gcc.mux, 0x32 },
{ "gcc_camera_axi_clk", &gcc.mux, 0x36 },
{ "gcc_camera_throttle_nrt_axi_clk", &gcc.mux, 0x4a },
{ "gcc_camera_throttle_rt_axi_clk", &gcc.mux, 0x39 },
{ "gcc_camera_xo_clk", &gcc.mux, 0x3c },
{ "gcc_ce1_ahb_clk", &gcc.mux, 0x92 },
{ "gcc_ce1_axi_clk", &gcc.mux, 0x91 },
{ "gcc_ce1_clk", &gcc.mux, 0x90 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x18 },
{ "gcc_cpuss_ahb_clk", &gcc.mux, 0xb7 },
{ "gcc_cpuss_gnoc_clk", &gcc.mux, 0xb8 },
{ "gcc_cpuss_rbcpr_clk", &gcc.mux, 0xb9 },
{ "gcc_ddrss_gpu_axi_clk", &gcc.mux, 0xa5 },
{ "gcc_disp_ahb_clk", &gcc.mux, 0x33 },
{ "gcc_disp_axi_clk", &gcc.mux, 0x37 },
{ "gcc_disp_cc_sleep_clk", &gcc.mux, 0x49 },
{ "gcc_disp_cc_xo_clk", &gcc.mux, 0x48 },
{ "gcc_disp_gpll0_clk", &gcc.mux, 0x44 },
{ "gcc_disp_throttle_axi_clk", &gcc.mux, 0x3a },
{ "gcc_disp_xo_clk", &gcc.mux, 0x3d },
{ "gcc_gp1_clk", &gcc.mux, 0xc5 },
{ "gcc_gp2_clk", &gcc.mux, 0xc6 },
{ "gcc_gp3_clk", &gcc.mux, 0xc7 },
{ "gcc_gpu_cfg_ahb_clk", &gcc.mux, 0x105 },
{ "gcc_gpu_gpll0_clk", &gcc.mux, 0x10b },
{ "gcc_gpu_gpll0_div_clk", &gcc.mux, 0x10c },
{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0x108 },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0x109 },
{ "gcc_npu_axi_clk", &gcc.mux, 0x116 },
{ "gcc_npu_bwmon_axi_clk", &gcc.mux, 0x11c },
{ "gcc_npu_bwmon_dma_cfg_ahb_clk", &gcc.mux, 0x11d },
{ "gcc_npu_bwmon_dsp_cfg_ahb_clk", &gcc.mux, 0x11e },
{ "gcc_npu_cfg_ahb_clk", &gcc.mux, 0x115 },
{ "gcc_npu_dma_clk", &gcc.mux, 0x11b },
{ "gcc_npu_gpll0_clk", &gcc.mux, 0x118 },
{ "gcc_npu_gpll0_div_clk", &gcc.mux, 0x119 },
{ "gcc_pdm2_clk", &gcc.mux, 0x7d },
{ "gcc_pdm_ahb_clk", &gcc.mux, 0x7b },
{ "gcc_pdm_xo4_clk", &gcc.mux, 0x7c },
{ "gcc_prng_ahb_clk", &gcc.mux, 0x7e },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x6a },
{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x69 },
{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x6b },
{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x6c },
{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x6d },
{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x6e },
{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x6f },
{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x70 },
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x71 },
{ "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x72 },
{ "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x75 },
{ "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x76 },
{ "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x77 },
{ "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x78 },
{ "gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x79 },
{ "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x7a },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x67 },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x68 },
{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x73 },
{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x74 },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0x112 },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0x113 },
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0x114 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x66 },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x65 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 },
{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0xc8 },
{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0xcc },
{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0xd1 },
{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0xd2 },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0xca },
{ "gcc_ufs_phy_rx_symbol_1_clk", &gcc.mux, 0xcb },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0xc9 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0xd0 },
{ "gcc_usb30_prim_master_clk", &gcc.mux, 0x5b },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x5d },
{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5c },
{ "gcc_usb3_prim_phy_aux_clk", &gcc.mux, 0x5e },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x5f },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x60 },
{ "gcc_video_ahb_clk", &gcc.mux, 0x31 },
{ "gcc_video_axi_clk", &gcc.mux, 0x35 },
{ "gcc_video_throttle_axi_clk", &gcc.mux, 0x38 },
{ "gcc_video_xo_clk", &gcc.mux, 0x3b },
{ "measure_only_cnoc_clk", &gcc.mux, 0x14 },
{ "measure_only_ipa_2x_clk", &gcc.mux, 0xec },
{ "measure_only_snoc_clk", &gcc.mux, 0x07 },
{ "gpu_cc_acd_ahb_clk", &gcc, 0x107, &gpu_cc, 0x20 },
{ "gpu_cc_acd_cxo_clk", &gcc, 0x107, &gpu_cc, 0x1f },
{ "gpu_cc_ahb_clk", &gcc, 0x107, &gpu_cc, 0x11 },
{ "gpu_cc_crc_ahb_clk", &gcc, 0x107, &gpu_cc, 0x12 },
{ "gpu_cc_cx_gfx3d_clk", &gcc, 0x107, &gpu_cc, 0x1a },
{ "gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x107, &gpu_cc, 0x1b },
{ "gpu_cc_cx_gmu_clk", &gcc, 0x107, &gpu_cc, 0x19 },
{ "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x107, &gpu_cc, 0x16 },
{ "gpu_cc_cxo_aon_clk", &gcc, 0x107, &gpu_cc, 0xb },
{ "gpu_cc_cxo_clk", &gcc, 0x107, &gpu_cc, 0xa },
{ "gpu_cc_gx_cxo_clk", &gcc, 0x107, &gpu_cc, 0xf },
{ "gpu_cc_gx_gfx3d_clk", &gcc, 0x107, &gpu_cc, 0xc },
{ "gpu_cc_gx_gmu_clk", &gcc, 0x107, &gpu_cc, 0x10 },
{ "gpu_cc_gx_vsense_clk", &gcc, 0x107, &gpu_cc, 0xd },
{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x14 },
{ "disp_cc_mdss_byte0_clk", &disp_cc, 0xc },
{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0xd },
{ "disp_cc_mdss_dp_aux_clk", &disp_cc, 0x13 },
{ "disp_cc_mdss_dp_crypto_clk", &disp_cc, 0x11 },
{ "disp_cc_mdss_dp_link_clk", &disp_cc, 0xf },
{ "disp_cc_mdss_dp_link_intf_clk", &disp_cc, 0x10 },
{ "disp_cc_mdss_dp_pixel_clk", &disp_cc, 0x12 },
{ "disp_cc_mdss_esc0_clk", &disp_cc, 0xe },
{ "disp_cc_mdss_mdp_clk", &disp_cc, 0x8 },
{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0xa },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x15 },
{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0x7 },
{ "disp_cc_mdss_rot_clk", &disp_cc, 0x9 },
{ "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x17 },
{ "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x16 },
{ "disp_cc_mdss_vsync_clk", &disp_cc, 0xb },
{ "disp_cc_sleep_clk", &disp_cc, 0x1d },
{ "disp_cc_xo_clk", &disp_cc, 0x1e },
{ "mccc_clk", &gcc, 0xab, &mc_cc, 0x50 },
{ "gpu_cc_acd_ahb_clk", &gpu_cc, 0x20 },
{ "gpu_cc_acd_cxo_clk", &gpu_cc, 0x1f },
{ "gpu_cc_ahb_clk", &gpu_cc, 0x11 },
{ "gpu_cc_crc_ahb_clk", &gpu_cc, 0x12 },
{ "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a },
{ "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b },
{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x19 },
{ "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x16 },
{ "gpu_cc_cxo_aon_clk", &gpu_cc, 0xb },
{ "gpu_cc_cxo_clk", &gpu_cc, 0xa },
{ "gpu_cc_gx_cxo_clk", &gpu_cc, 0xf },
{ "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xc },
{ "gpu_cc_gx_gmu_clk", &gpu_cc, 0x10 },
{ "gpu_cc_gx_vsense_clk", &gpu_cc, 0xd },
{ "mccc_clk", &mc_cc, 0x50 },
{}
};

357
sm6375.c
View File

@@ -12,11 +12,36 @@
#include "debugcc.h"
static struct gcc_mux gcc = {
.mux = {
.phys = 0x1400000,
.size = 0x1f0000,
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.div_reg = 0x30000,
.div_mask = 0xf,
.div_val = 1,
},
.xo_div4_reg = 0x28008,
.debug_ctl_reg = 0x62038,
.debug_status_reg = 0x6203c,
};
static struct debug_mux cpu_cc = {
.phys = 0xfaa0000,
.size = 0x1000,
.block_name = "cpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0xbf,
.enable_reg = 0x18,
.enable_mask = BIT(0),
@@ -35,6 +60,10 @@ static struct debug_mux disp_cc = {
.size = 0x20000,
.block_name = "disp",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0x43,
.enable_reg = 0x3004,
.enable_mask = BIT(0),
@@ -46,30 +75,15 @@ static struct debug_mux disp_cc = {
.div_val = 4,
};
static struct debug_mux gcc = {
.phys = 0x1400000,
.size = 0x1f0000,
.enable_reg = 0x30004,
.enable_mask = BIT(0),
.mux_reg = 0x62000,
.mux_mask = 0x3ff,
.div_reg = 0x30000,
.div_mask = 0xf,
.div_val = 1,
.xo_div4_reg = 0x28008,
.debug_ctl_reg = 0x62038,
.debug_status_reg = 0x6203c,
};
static struct debug_mux gpu_cc = {
.phys = 0x5990000,
.size = 0x9000,
.block_name = "gpu",
.measure = measure_leaf,
.parent = &gcc.mux,
.parent_mux_val = 0xfb,
.enable_reg = 0x1100,
.enable_mask = BIT(0),
@@ -88,165 +102,164 @@ static struct debug_mux mc_cc = {
.block_name = "mc",
.measure = measure_mccc,
.parent = &gcc.mux,
.parent_mux_val = 0xae,
};
static struct measure_clk sm6375_clocks[] = {
{ "l3_clk", &gcc, 0xbf, &cpu_cc, 0x41 },
{ "perfcl_clk", &gcc, 0xbf, &cpu_cc, 0x25 },
{ "pwrcl_clk", &gcc, 0xbf, &cpu_cc, 0x21 },
//{ "cpu_cc_debug_mux", &gcc, 0xbf },
//{ "disp_cc_debug_mux", &gcc, 0x43 },
{ "gcc_ahb2phy_csi_clk", &gcc, 0x67 },
{ "gcc_ahb2phy_usb_clk", &gcc, 0x68 },
{ "gcc_bimc_gpu_axi_clk", &gcc, 0x9d },
{ "gcc_boot_rom_ahb_clk", &gcc, 0x84 },
{ "gcc_cam_throttle_nrt_clk", &gcc, 0x4d },
{ "gcc_cam_throttle_rt_clk", &gcc, 0x4c },
{ "gcc_camss_axi_clk", &gcc, 0x154 },
{ "gcc_camss_cci_0_clk", &gcc, 0x151 },
{ "gcc_camss_cci_1_clk", &gcc, 0x152 },
{ "gcc_camss_cphy_0_clk", &gcc, 0x140 },
{ "gcc_camss_cphy_1_clk", &gcc, 0x141 },
{ "gcc_camss_cphy_2_clk", &gcc, 0x142 },
{ "gcc_camss_cphy_3_clk", &gcc, 0x143 },
{ "gcc_camss_csi0phytimer_clk", &gcc, 0x130 },
{ "gcc_camss_csi1phytimer_clk", &gcc, 0x131 },
{ "gcc_camss_csi2phytimer_clk", &gcc, 0x132 },
{ "gcc_camss_csi3phytimer_clk", &gcc, 0x133 },
{ "gcc_camss_mclk0_clk", &gcc, 0x134 },
{ "gcc_camss_mclk1_clk", &gcc, 0x135 },
{ "gcc_camss_mclk2_clk", &gcc, 0x136 },
{ "gcc_camss_mclk3_clk", &gcc, 0x137 },
{ "gcc_camss_mclk4_clk", &gcc, 0x138 },
{ "gcc_camss_nrt_axi_clk", &gcc, 0x158 },
{ "gcc_camss_ope_ahb_clk", &gcc, 0x150 },
{ "gcc_camss_ope_clk", &gcc, 0x14e },
{ "gcc_camss_rt_axi_clk", &gcc, 0x15a },
{ "gcc_camss_tfe_0_clk", &gcc, 0x139 },
{ "gcc_camss_tfe_0_cphy_rx_clk", &gcc, 0x13d },
{ "gcc_camss_tfe_0_csid_clk", &gcc, 0x144 },
{ "gcc_camss_tfe_1_clk", &gcc, 0x13a },
{ "gcc_camss_tfe_1_cphy_rx_clk", &gcc, 0x13e },
{ "gcc_camss_tfe_1_csid_clk", &gcc, 0x146 },
{ "gcc_camss_tfe_2_clk", &gcc, 0x13b },
{ "gcc_camss_tfe_2_cphy_rx_clk", &gcc, 0x13f },
{ "gcc_camss_tfe_2_csid_clk", &gcc, 0x148 },
{ "gcc_camss_top_ahb_clk", &gcc, 0x153 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1f },
{ "gcc_disp_gpll0_div_clk_src", &gcc, 0x48 },
{ "gcc_disp_hf_axi_clk", &gcc, 0x3e },
{ "gcc_disp_sleep_clk", &gcc, 0x4e },
{ "gcc_disp_throttle_core_clk", &gcc, 0x4a },
{ "gcc_gp1_clk", &gcc, 0xca },
{ "gcc_gp2_clk", &gcc, 0xcb },
{ "gcc_gp3_clk", &gcc, 0xcc },
{ "gcc_gpu_gpll0_clk_src", &gcc, 0xff },
{ "gcc_gpu_gpll0_div_clk_src", &gcc, 0x100 },
{ "gcc_gpu_memnoc_gfx_clk", &gcc, 0xfc },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0xfe },
{ "gcc_gpu_throttle_core_clk", &gcc, 0x103 },
{ "gcc_pdm2_clk", &gcc, 0x81 },
{ "gcc_pdm_ahb_clk", &gcc, 0x7f },
{ "gcc_pdm_xo4_clk", &gcc, 0x80 },
{ "gcc_prng_ahb_clk", &gcc, 0x82 },
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x3b },
{ "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x49 },
{ "gcc_qmip_disp_ahb_clk", &gcc, 0x3c },
{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc, 0x101 },
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x3a },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6e },
{ "gcc_qupv3_wrap0_core_clk", &gcc, 0x6d },
{ "gcc_qupv3_wrap0_s0_clk", &gcc, 0x6f },
{ "gcc_qupv3_wrap0_s1_clk", &gcc, 0x70 },
{ "gcc_qupv3_wrap0_s2_clk", &gcc, 0x71 },
{ "gcc_qupv3_wrap0_s3_clk", &gcc, 0x72 },
{ "gcc_qupv3_wrap0_s4_clk", &gcc, 0x73 },
{ "gcc_qupv3_wrap0_s5_clk", &gcc, 0x74 },
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x78 },
{ "gcc_qupv3_wrap1_core_clk", &gcc, 0x77 },
{ "gcc_qupv3_wrap1_s0_clk", &gcc, 0x79 },
{ "gcc_qupv3_wrap1_s1_clk", &gcc, 0x7a },
{ "gcc_qupv3_wrap1_s2_clk", &gcc, 0x7b },
{ "gcc_qupv3_wrap1_s3_clk", &gcc, 0x7c },
{ "gcc_qupv3_wrap1_s5_clk", &gcc, 0x7e },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x6b },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x6c },
{ "gcc_sdcc1_ahb_clk", &gcc, 0x108 },
{ "gcc_sdcc1_apps_clk", &gcc, 0x107 },
{ "gcc_sdcc1_ice_core_clk", &gcc, 0x109 },
{ "gcc_sdcc2_ahb_clk", &gcc, 0x6a },
{ "gcc_sdcc2_apps_clk", &gcc, 0x69 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 },
{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc, 0x1b },
{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc, 0x1a },
{ "gcc_ufs_phy_ahb_clk", &gcc, 0x127 },
{ "gcc_ufs_phy_axi_clk", &gcc, 0x126 },
{ "gcc_ufs_phy_ice_core_clk", &gcc, 0x12d },
{ "gcc_ufs_phy_phy_aux_clk", &gcc, 0x12e },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x129 },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x128 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc, 0x12c },
{ "gcc_usb30_prim_master_clk", &gcc, 0x5e },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x60 },
{ "gcc_usb30_prim_sleep_clk", &gcc, 0x5f },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x61 },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x62 },
{ "gcc_vcodec0_axi_clk", &gcc, 0x160 },
{ "gcc_venus_ahb_clk", &gcc, 0x161 },
{ "gcc_venus_ctl_axi_clk", &gcc, 0x15f },
{ "gcc_video_axi0_clk", &gcc, 0x3d },
{ "gcc_video_throttle_core_clk", &gcc, 0x4b },
{ "gcc_video_vcodec0_sys_clk", &gcc, 0x15d },
{ "gcc_video_venus_ctl_clk", &gcc, 0x15b },
{ "gcc_video_xo_clk", &gcc, 0x3f },
//{ "gpu_cc_debug_mux", &gcc, 0xfb },
//{ "mc_cc_debug_mux", &gcc, 0xae },
{ "measure_only_cnoc_clk", &gcc, 0x1d },
{ "measure_only_gcc_camera_ahb_clk", &gcc, 0x38 },
{ "measure_only_gcc_camera_xo_clk", &gcc, 0x40 },
{ "measure_only_gcc_cpuss_gnoc_clk", &gcc, 0xba },
{ "measure_only_gcc_disp_ahb_clk", &gcc, 0x39 },
{ "measure_only_gcc_disp_xo_clk", &gcc, 0x41 },
{ "measure_only_gcc_gpu_cfg_ahb_clk", &gcc, 0xf9 },
{ "measure_only_gcc_qupv3_wrap1_s4_clk", &gcc, 0x7d },
{ "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0x75 },
{ "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0x76 },
{ "measure_only_gcc_video_ahb_clk", &gcc, 0x37 },
{ "measure_only_hwkm_ahb_clk", &gcc, 0x166 },
{ "measure_only_hwkm_km_core_clk", &gcc, 0x167 },
{ "measure_only_ipa_2x_clk", &gcc, 0xd7 },
{ "measure_only_pka_ahb_clk", &gcc, 0x162 },
{ "measure_only_pka_core_clk", &gcc, 0x163 },
{ "measure_only_snoc_clk", &gcc, 0x7 },
{ "l3_clk", &cpu_cc, 0x41 },
{ "perfcl_clk", &cpu_cc, 0x25 },
{ "pwrcl_clk", &cpu_cc, 0x21 },
{ "disp_cc_mdss_ahb_clk", &gcc, 0x43, &disp_cc, 0x14 },
{ "disp_cc_mdss_byte0_clk", &gcc, 0x43, &disp_cc, 0xc },
{ "disp_cc_mdss_byte0_intf_clk", &gcc, 0x43, &disp_cc, 0xd },
{ "disp_cc_mdss_esc0_clk", &gcc, 0x43, &disp_cc, 0xe },
{ "disp_cc_mdss_mdp_clk", &gcc, 0x43, &disp_cc, 0x8 },
{ "disp_cc_mdss_mdp_lut_clk", &gcc, 0x43, &disp_cc, 0xa },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x43, &disp_cc, 0x15 },
{ "disp_cc_mdss_pclk0_clk", &gcc, 0x43, &disp_cc, 0x7 },
{ "disp_cc_mdss_rot_clk", &gcc, 0x43, &disp_cc, 0x9 },
{ "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x43, &disp_cc, 0x17 },
{ "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x43, &disp_cc, 0x16 },
{ "disp_cc_mdss_vsync_clk", &gcc, 0x43, &disp_cc, 0xb },
{ "measure_only_disp_cc_sleep_clk", &gcc, 0x43, &disp_cc, 0x1d },
{ "measure_only_disp_cc_xo_clk", &gcc, 0x43, &disp_cc, 0x1e },
{ "gcc_ahb2phy_csi_clk", &gcc.mux, 0x67 },
{ "gcc_ahb2phy_usb_clk", &gcc.mux, 0x68 },
{ "gcc_bimc_gpu_axi_clk", &gcc.mux, 0x9d },
{ "gcc_boot_rom_ahb_clk", &gcc.mux, 0x84 },
{ "gcc_cam_throttle_nrt_clk", &gcc.mux, 0x4d },
{ "gcc_cam_throttle_rt_clk", &gcc.mux, 0x4c },
{ "gcc_camss_axi_clk", &gcc.mux, 0x154 },
{ "gcc_camss_cci_0_clk", &gcc.mux, 0x151 },
{ "gcc_camss_cci_1_clk", &gcc.mux, 0x152 },
{ "gcc_camss_cphy_0_clk", &gcc.mux, 0x140 },
{ "gcc_camss_cphy_1_clk", &gcc.mux, 0x141 },
{ "gcc_camss_cphy_2_clk", &gcc.mux, 0x142 },
{ "gcc_camss_cphy_3_clk", &gcc.mux, 0x143 },
{ "gcc_camss_csi0phytimer_clk", &gcc.mux, 0x130 },
{ "gcc_camss_csi1phytimer_clk", &gcc.mux, 0x131 },
{ "gcc_camss_csi2phytimer_clk", &gcc.mux, 0x132 },
{ "gcc_camss_csi3phytimer_clk", &gcc.mux, 0x133 },
{ "gcc_camss_mclk0_clk", &gcc.mux, 0x134 },
{ "gcc_camss_mclk1_clk", &gcc.mux, 0x135 },
{ "gcc_camss_mclk2_clk", &gcc.mux, 0x136 },
{ "gcc_camss_mclk3_clk", &gcc.mux, 0x137 },
{ "gcc_camss_mclk4_clk", &gcc.mux, 0x138 },
{ "gcc_camss_nrt_axi_clk", &gcc.mux, 0x158 },
{ "gcc_camss_ope_ahb_clk", &gcc.mux, 0x150 },
{ "gcc_camss_ope_clk", &gcc.mux, 0x14e },
{ "gcc_camss_rt_axi_clk", &gcc.mux, 0x15a },
{ "gcc_camss_tfe_0_clk", &gcc.mux, 0x139 },
{ "gcc_camss_tfe_0_cphy_rx_clk", &gcc.mux, 0x13d },
{ "gcc_camss_tfe_0_csid_clk", &gcc.mux, 0x144 },
{ "gcc_camss_tfe_1_clk", &gcc.mux, 0x13a },
{ "gcc_camss_tfe_1_cphy_rx_clk", &gcc.mux, 0x13e },
{ "gcc_camss_tfe_1_csid_clk", &gcc.mux, 0x146 },
{ "gcc_camss_tfe_2_clk", &gcc.mux, 0x13b },
{ "gcc_camss_tfe_2_cphy_rx_clk", &gcc.mux, 0x13f },
{ "gcc_camss_tfe_2_csid_clk", &gcc.mux, 0x148 },
{ "gcc_camss_top_ahb_clk", &gcc.mux, 0x153 },
{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc.mux, 0x1f },
{ "gcc_disp_gpll0_div_clk_src", &gcc.mux, 0x48 },
{ "gcc_disp_hf_axi_clk", &gcc.mux, 0x3e },
{ "gcc_disp_sleep_clk", &gcc.mux, 0x4e },
{ "gcc_disp_throttle_core_clk", &gcc.mux, 0x4a },
{ "gcc_gp1_clk", &gcc.mux, 0xca },
{ "gcc_gp2_clk", &gcc.mux, 0xcb },
{ "gcc_gp3_clk", &gcc.mux, 0xcc },
{ "gcc_gpu_gpll0_clk_src", &gcc.mux, 0xff },
{ "gcc_gpu_gpll0_div_clk_src", &gcc.mux, 0x100 },
{ "gcc_gpu_memnoc_gfx_clk", &gcc.mux, 0xfc },
{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc.mux, 0xfe },
{ "gcc_gpu_throttle_core_clk", &gcc.mux, 0x103 },
{ "gcc_pdm2_clk", &gcc.mux, 0x81 },
{ "gcc_pdm_ahb_clk", &gcc.mux, 0x7f },
{ "gcc_pdm_xo4_clk", &gcc.mux, 0x80 },
{ "gcc_prng_ahb_clk", &gcc.mux, 0x82 },
{ "gcc_qmip_camera_nrt_ahb_clk", &gcc.mux, 0x3b },
{ "gcc_qmip_camera_rt_ahb_clk", &gcc.mux, 0x49 },
{ "gcc_qmip_disp_ahb_clk", &gcc.mux, 0x3c },
{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc.mux, 0x101 },
{ "gcc_qmip_video_vcodec_ahb_clk", &gcc.mux, 0x3a },
{ "gcc_qupv3_wrap0_core_2x_clk", &gcc.mux, 0x6e },
{ "gcc_qupv3_wrap0_core_clk", &gcc.mux, 0x6d },
{ "gcc_qupv3_wrap0_s0_clk", &gcc.mux, 0x6f },
{ "gcc_qupv3_wrap0_s1_clk", &gcc.mux, 0x70 },
{ "gcc_qupv3_wrap0_s2_clk", &gcc.mux, 0x71 },
{ "gcc_qupv3_wrap0_s3_clk", &gcc.mux, 0x72 },
{ "gcc_qupv3_wrap0_s4_clk", &gcc.mux, 0x73 },
{ "gcc_qupv3_wrap0_s5_clk", &gcc.mux, 0x74 },
{ "gcc_qupv3_wrap1_core_2x_clk", &gcc.mux, 0x78 },
{ "gcc_qupv3_wrap1_core_clk", &gcc.mux, 0x77 },
{ "gcc_qupv3_wrap1_s0_clk", &gcc.mux, 0x79 },
{ "gcc_qupv3_wrap1_s1_clk", &gcc.mux, 0x7a },
{ "gcc_qupv3_wrap1_s2_clk", &gcc.mux, 0x7b },
{ "gcc_qupv3_wrap1_s3_clk", &gcc.mux, 0x7c },
{ "gcc_qupv3_wrap1_s5_clk", &gcc.mux, 0x7e },
{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc.mux, 0x6b },
{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc.mux, 0x6c },
{ "gcc_sdcc1_ahb_clk", &gcc.mux, 0x108 },
{ "gcc_sdcc1_apps_clk", &gcc.mux, 0x107 },
{ "gcc_sdcc1_ice_core_clk", &gcc.mux, 0x109 },
{ "gcc_sdcc2_ahb_clk", &gcc.mux, 0x6a },
{ "gcc_sdcc2_apps_clk", &gcc.mux, 0x69 },
{ "gcc_sys_noc_cpuss_ahb_clk", &gcc.mux, 0x9 },
{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc.mux, 0x1b },
{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc.mux, 0x1a },
{ "gcc_ufs_phy_ahb_clk", &gcc.mux, 0x127 },
{ "gcc_ufs_phy_axi_clk", &gcc.mux, 0x126 },
{ "gcc_ufs_phy_ice_core_clk", &gcc.mux, 0x12d },
{ "gcc_ufs_phy_phy_aux_clk", &gcc.mux, 0x12e },
{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc.mux, 0x129 },
{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc.mux, 0x128 },
{ "gcc_ufs_phy_unipro_core_clk", &gcc.mux, 0x12c },
{ "gcc_usb30_prim_master_clk", &gcc.mux, 0x5e },
{ "gcc_usb30_prim_mock_utmi_clk", &gcc.mux, 0x60 },
{ "gcc_usb30_prim_sleep_clk", &gcc.mux, 0x5f },
{ "gcc_usb3_prim_phy_com_aux_clk", &gcc.mux, 0x61 },
{ "gcc_usb3_prim_phy_pipe_clk", &gcc.mux, 0x62 },
{ "gcc_vcodec0_axi_clk", &gcc.mux, 0x160 },
{ "gcc_venus_ahb_clk", &gcc.mux, 0x161 },
{ "gcc_venus_ctl_axi_clk", &gcc.mux, 0x15f },
{ "gcc_video_axi0_clk", &gcc.mux, 0x3d },
{ "gcc_video_throttle_core_clk", &gcc.mux, 0x4b },
{ "gcc_video_vcodec0_sys_clk", &gcc.mux, 0x15d },
{ "gcc_video_venus_ctl_clk", &gcc.mux, 0x15b },
{ "gcc_video_xo_clk", &gcc.mux, 0x3f },
{ "measure_only_cnoc_clk", &gcc.mux, 0x1d },
{ "measure_only_gcc_camera_ahb_clk", &gcc.mux, 0x38 },
{ "measure_only_gcc_camera_xo_clk", &gcc.mux, 0x40 },
{ "measure_only_gcc_cpuss_gnoc_clk", &gcc.mux, 0xba },
{ "measure_only_gcc_disp_ahb_clk", &gcc.mux, 0x39 },
{ "measure_only_gcc_disp_xo_clk", &gcc.mux, 0x41 },
{ "measure_only_gcc_gpu_cfg_ahb_clk", &gcc.mux, 0xf9 },
{ "measure_only_gcc_qupv3_wrap1_s4_clk", &gcc.mux, 0x7d },
{ "measure_only_gcc_qupv3_wrap_1_m_ahb_clk", &gcc.mux, 0x75 },
{ "measure_only_gcc_qupv3_wrap_1_s_ahb_clk", &gcc.mux, 0x76 },
{ "measure_only_gcc_video_ahb_clk", &gcc.mux, 0x37 },
{ "measure_only_hwkm_ahb_clk", &gcc.mux, 0x166 },
{ "measure_only_hwkm_km_core_clk", &gcc.mux, 0x167 },
{ "measure_only_ipa_2x_clk", &gcc.mux, 0xd7 },
{ "measure_only_pka_ahb_clk", &gcc.mux, 0x162 },
{ "measure_only_pka_core_clk", &gcc.mux, 0x163 },
{ "measure_only_snoc_clk", &gcc.mux, 0x7 },
{ "gpu_cc_ahb_clk", &gcc, 0xfb, &gpu_cc, 0x11 },
{ "gpu_cc_cx_gfx3d_clk", &gcc, 0xfb, &gpu_cc, 0x1a },
{ "gpu_cc_cx_gfx3d_slv_clk", &gcc, 0xfb, &gpu_cc, 0x1b },
{ "gpu_cc_cx_gmu_clk", &gcc, 0xfb, &gpu_cc, 0x19 },
{ "gpu_cc_cx_snoc_dvm_clk", &gcc, 0xfb, &gpu_cc, 0x16 },
{ "gpu_cc_cxo_aon_clk", &gcc, 0xfb, &gpu_cc, 0xb },
{ "gpu_cc_cxo_clk", &gcc, 0xfb, &gpu_cc, 0xa },
{ "gpu_cc_gx_cxo_clk", &gcc, 0xfb, &gpu_cc, 0xf },
{ "gpu_cc_gx_gfx3d_clk", &gcc, 0xfb, &gpu_cc, 0xc },
{ "gpu_cc_gx_gmu_clk", &gcc, 0xfb, &gpu_cc, 0x10 },
{ "gpu_cc_sleep_clk", &gcc, 0xfb, &gpu_cc, 0x17 },
{ "disp_cc_mdss_ahb_clk", &disp_cc, 0x14 },
{ "disp_cc_mdss_byte0_clk", &disp_cc, 0xc },
{ "disp_cc_mdss_byte0_intf_clk", &disp_cc, 0xd },
{ "disp_cc_mdss_esc0_clk", &disp_cc, 0xe },
{ "disp_cc_mdss_mdp_clk", &disp_cc, 0x8 },
{ "disp_cc_mdss_mdp_lut_clk", &disp_cc, 0xa },
{ "disp_cc_mdss_non_gdsc_ahb_clk", &disp_cc, 0x15 },
{ "disp_cc_mdss_pclk0_clk", &disp_cc, 0x7 },
{ "disp_cc_mdss_rot_clk", &disp_cc, 0x9 },
{ "disp_cc_mdss_rscc_ahb_clk", &disp_cc, 0x17 },
{ "disp_cc_mdss_rscc_vsync_clk", &disp_cc, 0x16 },
{ "disp_cc_mdss_vsync_clk", &disp_cc, 0xb },
{ "measure_only_disp_cc_sleep_clk", &disp_cc, 0x1d },
{ "measure_only_disp_cc_xo_clk", &disp_cc, 0x1e },
{ "mccc_clk", &gcc, 0xae, &mc_cc, 0x220 },
{ "gpu_cc_ahb_clk", &gpu_cc, 0x11 },
{ "gpu_cc_cx_gfx3d_clk", &gpu_cc, 0x1a },
{ "gpu_cc_cx_gfx3d_slv_clk", &gpu_cc, 0x1b },
{ "gpu_cc_cx_gmu_clk", &gpu_cc, 0x19 },
{ "gpu_cc_cx_snoc_dvm_clk", &gpu_cc, 0x16 },
{ "gpu_cc_cxo_aon_clk", &gpu_cc, 0xb },
{ "gpu_cc_cxo_clk", &gpu_cc, 0xa },
{ "gpu_cc_gx_cxo_clk", &gpu_cc, 0xf },
{ "gpu_cc_gx_gfx3d_clk", &gpu_cc, 0xc },
{ "gpu_cc_gx_gmu_clk", &gpu_cc, 0x10 },
{ "gpu_cc_sleep_clk", &gpu_cc, 0x17 },
{ "mccc_clk", &mc_cc, 0x220 },
{}
};

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sm8150.c
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sm8250.c
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566
sm8350.c
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626
sm8450.c
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629
sm8550.c
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