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https://github.com/linux-msm/debugcc.git
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cf5664f7c4
Enforcing a primary+leaf configuration does not walk for all the cases. Some clocks (msm8996 CPU) have more muxes to be powered on. Other (MCCC) do not require GCC at all. Make clock measurement more versatile by reworking GCC + optional leaf into a chain of muxes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
192 lines
7.2 KiB
C
192 lines
7.2 KiB
C
/*
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* Copyright (c) 2022, Linaro Ltd.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/mman.h>
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#include <err.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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#define GCC_BASE 0x01800000
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#define GCC_SIZE 0x80000
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#define GCC_DEBUG_CLK_CTL 0x74000
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#define GCC_CLOCK_FREQ_MEASURE_CTL 0x74004
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#define GCC_CLOCK_FREQ_MEASURE_STATUS 0x74008
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#define GCC_XO_DIV4_CBCR 0x30034
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static struct gcc_mux gcc = {
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.mux = {
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.phys = GCC_BASE,
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.size = GCC_SIZE,
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.measure = measure_gcc,
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.enable_reg = GCC_DEBUG_CLK_CTL,
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.enable_mask = BIT(16),
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.mux_reg = GCC_DEBUG_CLK_CTL,
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.mux_mask = 0x1ff,
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.div_reg = GCC_DEBUG_CLK_CTL,
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.div_shift = 12,
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.div_mask = 0xf << 12,
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.div_val = 4,
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},
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.xo_div4_reg = GCC_XO_DIV4_CBCR,
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.debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL,
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.debug_status_reg = GCC_CLOCK_FREQ_MEASURE_STATUS,
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};
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static struct measure_clk msm8936_clocks[] = {
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{ "gcc_gp1_clk", &gcc.mux, 16 },
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{ "gcc_gp2_clk", &gcc.mux, 17 },
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{ "gcc_gp3_clk", &gcc.mux, 18 },
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{ "gcc_bimc_gfx_clk", &gcc.mux, 45 },
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{ "gcc_mss_cfg_ahb_clk", &gcc.mux, 48 },
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{ "gcc_mss_q6_bimc_axi_clk", &gcc.mux, 49 },
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{ "gcc_apss_tcu_clk", &gcc.mux, 80 },
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{ "gcc_mdp_tbu_clk", &gcc.mux, 81 },
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{ "gcc_gfx_tbu_clk", &gcc.mux, 82 },
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{ "gcc_gfx_tcu_clk", &gcc.mux, 83 },
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{ "gcc_venus_tbu_clk", &gcc.mux, 84 },
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{ "gcc_gtcu_ahb_clk", &gcc.mux, 88 },
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{ "gcc_vfe_tbu_clk", &gcc.mux, 90 },
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{ "gcc_smmu_cfg_clk", &gcc.mux, 91 },
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{ "gcc_jpeg_tbu_clk", &gcc.mux, 92 },
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{ "gcc_usb_hs_system_clk", &gcc.mux, 96 },
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{ "gcc_usb_hs_ahb_clk", &gcc.mux, 97 },
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{ "gcc_usb_fs_ahb_clk", &gcc.mux, 241 },
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{ "gcc_usb_fs_ic_clk", &gcc.mux, 244 },
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{ "gcc_usb2a_phy_sleep_clk", &gcc.mux, 99 },
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{ "gcc_sdcc1_apps_clk", &gcc.mux, 104 },
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{ "gcc_sdcc1_ahb_clk", &gcc.mux, 105 },
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{ "gcc_sdcc2_apps_clk", &gcc.mux, 112 },
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{ "gcc_sdcc2_ahb_clk", &gcc.mux, 113 },
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{ "gcc_blsp1_ahb_clk", &gcc.mux, 136 },
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{ "gcc_blsp1_qup1_spi_apps_clk", &gcc.mux, 138 },
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{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc.mux, 139 },
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{ "gcc_blsp1_uart1_apps_clk", &gcc.mux, 140 },
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{ "gcc_blsp1_qup2_spi_apps_clk", &gcc.mux, 142 },
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{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc.mux, 144 },
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{ "gcc_blsp1_uart2_apps_clk", &gcc.mux, 145 },
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{ "gcc_blsp1_qup3_spi_apps_clk", &gcc.mux, 147 },
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{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc.mux, 148 },
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{ "gcc_blsp1_qup4_spi_apps_clk", &gcc.mux, 152 },
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{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc.mux, 153 },
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{ "gcc_blsp1_qup5_spi_apps_clk", &gcc.mux, 156 },
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{ "gcc_blsp1_qup5_i2c_apps_clk", &gcc.mux, 157 },
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{ "gcc_blsp1_qup6_spi_apps_clk", &gcc.mux, 161 },
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{ "gcc_blsp1_qup6_i2c_apps_clk", &gcc.mux, 162 },
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{ "gcc_camss_ahb_clk", &gcc.mux, 168 },
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{ "gcc_camss_top_ahb_clk", &gcc.mux, 169 },
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{ "gcc_camss_micro_ahb_clk", &gcc.mux, 170 },
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{ "gcc_camss_gp0_clk", &gcc.mux, 171 },
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{ "gcc_camss_gp1_clk", &gcc.mux, 172 },
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{ "gcc_camss_mclk0_clk", &gcc.mux, 173 },
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{ "gcc_camss_mclk1_clk", &gcc.mux, 174 },
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{ "gcc_camss_mclk2_clk", &gcc.mux, 445 },
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{ "gcc_camss_cci_clk", &gcc.mux, 175 },
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{ "gcc_camss_cci_ahb_clk", &gcc.mux, 176 },
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{ "gcc_camss_csi0phytimer_clk", &gcc.mux, 177 },
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{ "gcc_camss_csi1phytimer_clk", &gcc.mux, 178 },
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{ "gcc_camss_jpeg0_clk", &gcc.mux, 179 },
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{ "gcc_camss_jpeg_ahb_clk", &gcc.mux, 180 },
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{ "gcc_camss_jpeg_axi_clk", &gcc.mux, 181 },
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{ "gcc_camss_vfe0_clk", &gcc.mux, 184 },
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{ "gcc_camss_cpp_clk", &gcc.mux, 185 },
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{ "gcc_camss_cpp_ahb_clk", &gcc.mux, 186 },
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{ "gcc_camss_vfe_ahb_clk", &gcc.mux, 187 },
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{ "gcc_camss_vfe_axi_clk", &gcc.mux, 188 },
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{ "gcc_camss_csi_vfe0_clk", &gcc.mux, 191 },
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{ "gcc_camss_csi0_clk", &gcc.mux, 192 },
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{ "gcc_camss_csi0_ahb_clk", &gcc.mux, 193 },
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{ "gcc_camss_csi0phy_clk", &gcc.mux, 194 },
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{ "gcc_camss_csi0rdi_clk", &gcc.mux, 195 },
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{ "gcc_camss_csi0pix_clk", &gcc.mux, 196 },
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{ "gcc_camss_csi1_clk", &gcc.mux, 197 },
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{ "gcc_camss_csi1_ahb_clk", &gcc.mux, 198 },
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{ "gcc_camss_csi1phy_clk", &gcc.mux, 199 },
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{ "gcc_camss_csi2_clk", &gcc.mux, 227 },
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{ "gcc_camss_csi2_ahb_clk", &gcc.mux, 228 },
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{ "gcc_camss_csi2phy_clk", &gcc.mux, 229 },
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{ "gcc_camss_csi2rdi_clk", &gcc.mux, 230 },
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{ "gcc_camss_csi2pix_clk", &gcc.mux, 231 },
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{ "gcc_pdm_ahb_clk", &gcc.mux, 208 },
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{ "gcc_pdm2_clk", &gcc.mux, 210 },
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{ "gcc_prng_ahb_clk", &gcc.mux, 216 },
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{ "gcc_camss_csi1rdi_clk", &gcc.mux, 224 },
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{ "gcc_camss_csi1pix_clk", &gcc.mux, 225 },
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{ "gcc_camss_ispif_ahb_clk", &gcc.mux, 226 },
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{ "gcc_boot_rom_ahb_clk", &gcc.mux, 248 },
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{ "gcc_crypto_clk", &gcc.mux, 312 },
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{ "gcc_crypto_axi_clk", &gcc.mux, 313 },
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{ "gcc_crypto_ahb_clk", &gcc.mux, 314 },
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{ "gcc_oxili_timer_clk", &gcc.mux, 489 },
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{ "gcc_oxili_gfx3d_clk", &gcc.mux, 490 },
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{ "gcc_oxili_ahb_clk", &gcc.mux, 491 },
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{ "gcc_oxili_gmem_clk", &gcc.mux, 496 },
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{ "gcc_venus0_vcodec0_clk", &gcc.mux, 497 },
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{ "gcc_venus0_core0_vcodec0_clk", &gcc.mux, 440 },
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{ "gcc_venus0_core1_vcodec0_clk", &gcc.mux, 441 },
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{ "gcc_venus0_axi_clk", &gcc.mux, 498 },
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{ "gcc_venus0_ahb_clk", &gcc.mux, 499 },
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{ "gcc_mdss_ahb_clk", &gcc.mux, 502 },
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{ "gcc_mdss_axi_clk", &gcc.mux, 503 },
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{ "gcc_mdss_pclk0_clk", &gcc.mux, 504 },
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{ "gcc_mdss_pclk1_clk", &gcc.mux, 442 },
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{ "gcc_mdss_mdp_clk", &gcc.mux, 505 },
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{ "gcc_mdss_vsync_clk", &gcc.mux, 507 },
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{ "gcc_mdss_byte0_clk", &gcc.mux, 508 },
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{ "gcc_mdss_byte1_clk", &gcc.mux, 443 },
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{ "gcc_mdss_esc0_clk", &gcc.mux, 509 },
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{ "gcc_mdss_esc1_clk", &gcc.mux, 444 },
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{ "gcc_bimc_clk", &gcc.mux, 340 },
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{ "gcc_bimc_gpu_clk", &gcc.mux, 343 },
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{ "gcc_bimc_ddr_ch0_clk", &gcc.mux, 346 },
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{ "gcc_cpp_tbu_clk", &gcc.mux, 233 },
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{ "gcc_mdp_rt_tbu_clk", &gcc.mux, 238 },
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{ "wcnss_m_clk", &gcc.mux, 408 },
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{},
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};
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struct debugcc_platform msm8936_debugcc = {
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"msm8936",
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msm8936_clocks,
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};
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