mirror of
https://github.com/linux-msm/debugcc.git
synced 2026-02-25 13:12:32 -08:00
Add SM6115 / bengal
SM6115 and its other bengal friends have 5 debug muxes, one of which (memory controller) is out of scope here, as it's not defined in dt. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
This commit is contained in:
Konrad Dybcio
committed by
Bjorn Andersson
Bjorn Andersson
parent
7abf9d5f7b
commit
80f81a693b
14
Makefile
14
Makefile
@@ -6,7 +6,18 @@ CFLAGS := -O2 -Wall -g
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LDFLAGS := -static -static-libgcc
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prefix := /usr/local
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SRCS := debugcc.c msm8936.c msm8996.c qcs404.c sc8280xp.c sdm845.c sm8150.c sm8250.c sm8350.c sm8450.c sm8550.c
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SRCS := debugcc.c \
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msm8936.c \
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msm8996.c \
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qcs404.c \
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sc8280xp.c \
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sdm845.c \
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sm6115.c \
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sm8150.c \
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sm8250.c \
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sm8350.c \
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sm8450.c \
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sm8550.c
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OBJS := $(SRCS:.c=.o)
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$(OUT): $(OBJS)
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@@ -16,6 +27,7 @@ $(OUT): $(OBJS)
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ln -f $(OUT) qcs404-debugcc
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ln -f $(OUT) sc8280xp-debugcc
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ln -f $(OUT) sdm845-debugcc
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ln -f $(OUT) sm6115-debugcc
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ln -f $(OUT) sm8150-debugcc
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ln -f $(OUT) sm8250-debugcc
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ln -f $(OUT) sm8350-debugcc
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@@ -48,6 +48,7 @@ static const struct debugcc_platform *platforms[] = {
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&qcs404_debugcc,
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&sc8280xp_debugcc,
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&sdm845_debugcc,
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&sm6115_debugcc,
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&sm8150_debugcc,
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&sm8250_debugcc,
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&sm8350_debugcc,
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@@ -94,6 +94,7 @@ extern struct debugcc_platform msm8996_debugcc;
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extern struct debugcc_platform qcs404_debugcc;
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extern struct debugcc_platform sc8280xp_debugcc;
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extern struct debugcc_platform sdm845_debugcc;
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extern struct debugcc_platform sm6115_debugcc;
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extern struct debugcc_platform sm8150_debugcc;
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extern struct debugcc_platform sm8250_debugcc;
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extern struct debugcc_platform sm8350_debugcc;
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215
sm6115.c
Normal file
215
sm6115.c
Normal file
@@ -0,0 +1,215 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/* Copyright (c) 2022, Linaro Limited */
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#include <sys/mman.h>
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#include <err.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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static struct debug_mux cpu_cc = {
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.phys = 0xf111000,
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.size = 0x1000,
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.block_name = "cpu",
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.enable_reg = 0x1c,
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.enable_mask = BIT(0),
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.mux_reg = 0x1c,
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.mux_mask = 0x3ff << 8,
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.mux_shift = 8,
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.div_reg = 0x1c,
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.div_mask = 0xf << 28,
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.div_shift = 28,
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};
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static struct debug_mux disp_cc = {
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.phys = 0x5f00000,
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.size = 0x20000,
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.block_name = "disp",
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.enable_reg = 0x500c,
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.enable_mask = BIT(0),
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.mux_reg = 0x7000,
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.mux_mask = 0xff,
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.div_reg = 0x5008,
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.div_mask = 0x3,
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.div_val = 4,
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};
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static struct debug_mux gcc = {
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.phys = 0x1400000,
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.size = 0x1f0000,
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.enable_reg = 0x30004,
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.enable_mask = BIT(0),
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.mux_reg = 0x62000,
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.mux_mask = 0x3ff,
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.div_reg = 0x30000,
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.div_mask = 0xf,
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.div_val = 4,
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.xo_div4_reg = 0x28008,
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.debug_ctl_reg = 0x62038,
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.debug_status_reg = 0x6203c,
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};
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static struct debug_mux gpu_cc = {
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.phys = 0x5990000,
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.size = 0x9000,
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.block_name = "gpu",
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.enable_reg = 0x1100,
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.enable_mask = BIT(0),
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.mux_reg = 0x1568,
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.mux_mask = 0xff,
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.div_reg = 0x10fc,
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.div_mask = 0x3,
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.div_val = 2,
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};
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static struct measure_clk sm6115_clocks[] = {
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{ "perfcl_clk", &gcc, 0xaf, &cpu_cc, 0x1 },
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{ "pwrcl_clk", &gcc, 0xaf, &cpu_cc, 0x0 },
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//{ "cpu_cc_debug_mux", &gcc, 0xaf },
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//{ "disp_cc_debug_mux", &gcc, 0x42 },
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{ "gcc_ahb2phy_csi_clk", &gcc, 0x63 },
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{ "gcc_ahb2phy_usb_clk", &gcc, 0x64 },
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{ "gcc_bimc_gpu_axi_clk", &gcc, 0x90 },
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{ "gcc_boot_rom_ahb_clk", &gcc, 0x76 },
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{ "gcc_cam_throttle_nrt_clk", &gcc, 0x4c },
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{ "gcc_cam_throttle_rt_clk", &gcc, 0x4b },
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{ "gcc_camera_ahb_clk", &gcc, 0x37 },
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{ "gcc_camera_xo_clk", &gcc, 0x3f },
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{ "gcc_camss_axi_clk", &gcc, 0x136 },
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{ "gcc_camss_camnoc_atb_clk", &gcc, 0x138 },
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{ "gcc_camss_camnoc_nts_xo_clk", &gcc, 0x139 },
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{ "gcc_camss_cci_0_clk", &gcc, 0x134 },
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{ "gcc_camss_cphy_0_clk", &gcc, 0x128 },
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{ "gcc_camss_cphy_1_clk", &gcc, 0x129 },
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{ "gcc_camss_cphy_2_clk", &gcc, 0x12a },
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{ "gcc_camss_csi0phytimer_clk", &gcc, 0x11a },
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{ "gcc_camss_csi1phytimer_clk", &gcc, 0x11b },
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{ "gcc_camss_csi2phytimer_clk", &gcc, 0x11c },
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{ "gcc_camss_mclk0_clk", &gcc, 0x11d },
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{ "gcc_camss_mclk1_clk", &gcc, 0x11e },
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{ "gcc_camss_mclk2_clk", &gcc, 0x11f },
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{ "gcc_camss_mclk3_clk", &gcc, 0x120 },
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{ "gcc_camss_nrt_axi_clk", &gcc, 0x13a },
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{ "gcc_camss_ope_ahb_clk", &gcc, 0x133 },
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{ "gcc_camss_ope_clk", &gcc, 0x131 },
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{ "gcc_camss_rt_axi_clk", &gcc, 0x13c },
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{ "gcc_camss_tfe_0_clk", &gcc, 0x121 },
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{ "gcc_camss_tfe_0_cphy_rx_clk", &gcc, 0x125 },
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{ "gcc_camss_tfe_0_csid_clk", &gcc, 0x12b },
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{ "gcc_camss_tfe_1_clk", &gcc, 0x122 },
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{ "gcc_camss_tfe_1_cphy_rx_clk", &gcc, 0x126 },
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{ "gcc_camss_tfe_1_csid_clk", &gcc, 0x12d },
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{ "gcc_camss_tfe_2_clk", &gcc, 0x123 },
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{ "gcc_camss_tfe_2_cphy_rx_clk", &gcc, 0x127 },
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{ "gcc_camss_tfe_2_csid_clk", &gcc, 0x12f },
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{ "gcc_camss_top_ahb_clk", &gcc, 0x135 },
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{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x1d },
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{ "gcc_cpuss_gnoc_clk", &gcc, 0xaa },
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{ "gcc_disp_ahb_clk", &gcc, 0x38 },
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{ "gcc_disp_gpll0_div_clk_src", &gcc, 0x47 },
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{ "gcc_disp_hf_axi_clk", &gcc, 0x3d },
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{ "gcc_disp_throttle_core_clk", &gcc, 0x49 },
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{ "gcc_disp_xo_clk", &gcc, 0x40 },
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{ "gcc_gp1_clk", &gcc, 0xba },
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{ "gcc_gp2_clk", &gcc, 0xbb },
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{ "gcc_gp3_clk", &gcc, 0xbc },
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{ "gcc_gpu_cfg_ahb_clk", &gcc, 0xe5 },
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{ "gcc_gpu_gpll0_clk_src", &gcc, 0xeb },
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{ "gcc_gpu_gpll0_div_clk_src", &gcc, 0xec },
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{ "gcc_gpu_memnoc_gfx_clk", &gcc, 0xe8 },
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{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0xea },
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{ "gcc_gpu_throttle_core_clk", &gcc, 0xef },
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{ "gcc_pdm2_clk", &gcc, 0x73 },
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{ "gcc_pdm_ahb_clk", &gcc, 0x71 },
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{ "gcc_pdm_xo4_clk", &gcc, 0x72 },
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{ "gcc_prng_ahb_clk", &gcc, 0x74 },
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{ "gcc_qmip_camera_nrt_ahb_clk", &gcc, 0x3a },
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{ "gcc_qmip_camera_rt_ahb_clk", &gcc, 0x48 },
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{ "gcc_qmip_disp_ahb_clk", &gcc, 0x3b },
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{ "gcc_qmip_gpu_cfg_ahb_clk", &gcc, 0xed },
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{ "gcc_qmip_video_vcodec_ahb_clk", &gcc, 0x39 },
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{ "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6a },
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{ "gcc_qupv3_wrap0_core_clk", &gcc, 0x69 },
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{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x67 },
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{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x68 },
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{ "gcc_sdcc1_ahb_clk", &gcc, 0xf3 },
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{ "gcc_sdcc1_apps_clk", &gcc, 0xf2 },
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{ "gcc_sdcc1_ice_core_clk", &gcc, 0xf4 },
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{ "gcc_sdcc2_ahb_clk", &gcc, 0x66 },
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{ "gcc_sdcc2_apps_clk", &gcc, 0x65 },
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{ "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 },
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{ "gcc_sys_noc_ufs_phy_axi_clk", &gcc, 0x19 },
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{ "gcc_sys_noc_usb3_prim_axi_clk", &gcc, 0x18 },
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{ "gcc_ufs_phy_ahb_clk", &gcc, 0x111 },
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{ "gcc_ufs_phy_axi_clk", &gcc, 0x110 },
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{ "gcc_ufs_phy_ice_core_clk", &gcc, 0x117 },
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{ "gcc_ufs_phy_phy_aux_clk", &gcc, 0x118 },
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{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0x113 },
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{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0x112 },
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{ "gcc_ufs_phy_unipro_core_clk", &gcc, 0x116 },
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{ "gcc_usb30_prim_master_clk", &gcc, 0x5c },
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{ "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5e },
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{ "gcc_usb30_prim_sleep_clk", &gcc, 0x5d },
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{ "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5f },
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{ "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x60 },
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{ "gcc_vcodec0_axi_clk", &gcc, 0x142 },
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{ "gcc_venus_ahb_clk", &gcc, 0x143 },
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{ "gcc_venus_ctl_axi_clk", &gcc, 0x141 },
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{ "gcc_video_ahb_clk", &gcc, 0x36 },
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{ "gcc_video_axi0_clk", &gcc, 0x3c },
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{ "gcc_video_throttle_core_clk", &gcc, 0x4a },
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{ "gcc_video_vcodec0_sys_clk", &gcc, 0x13f },
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{ "gcc_video_venus_ctl_clk", &gcc, 0x13d },
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{ "gcc_video_xo_clk", &gcc, 0x3e },
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//{ "gpu_cc_debug_mux", &gcc, 0xe7 },
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//{ "mc_cc_debug_mux", &gcc, 0x9e },
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{ "measure_only_cnoc_clk", &gcc, 0x1a },
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{ "measure_only_ipa_2x_clk", &gcc, 0xc6 },
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{ "measure_only_snoc_clk", &gcc, 0x7 },
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{ "disp_cc_mdss_ahb_clk", &gcc, 0x42, &disp_cc, 0x1a },
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{ "disp_cc_mdss_byte0_clk", &gcc, 0x42, &disp_cc, 0x12 },
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{ "disp_cc_mdss_byte0_intf_clk", &gcc, 0x42, &disp_cc, 0x13 },
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{ "disp_cc_mdss_esc0_clk", &gcc, 0x42, &disp_cc, 0x14 },
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{ "disp_cc_mdss_mdp_clk", &gcc, 0x42, &disp_cc, 0xe },
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{ "disp_cc_mdss_mdp_lut_clk", &gcc, 0x42, &disp_cc, 0x10 },
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{ "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x42, &disp_cc, 0x1b },
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{ "disp_cc_mdss_pclk0_clk", &gcc, 0x42, &disp_cc, 0xd },
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{ "disp_cc_mdss_rot_clk", &gcc, 0x42, &disp_cc, 0xf },
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{ "disp_cc_mdss_vsync_clk", &gcc, 0x42, &disp_cc, 0x11 },
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{ "disp_cc_sleep_clk", &gcc, 0x42, &disp_cc, 0x24 },
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{ "disp_cc_xo_clk", &gcc, 0x42, &disp_cc, 0x23 },
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{ "gpu_cc_ahb_clk", &gcc, 0xe7, &gpu_cc, 0x10 },
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{ "gpu_cc_crc_ahb_clk", &gcc, 0xe7, &gpu_cc, 0x11 },
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{ "gpu_cc_cx_gfx3d_clk", &gcc, 0xe7, &gpu_cc, 0x1a },
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{ "gpu_cc_cx_gmu_clk", &gcc, 0xe7, &gpu_cc, 0x18 },
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{ "gpu_cc_cx_snoc_dvm_clk", &gcc, 0xe7, &gpu_cc, 0x15 },
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{ "gpu_cc_cxo_aon_clk", &gcc, 0xe7, &gpu_cc, 0xa },
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{ "gpu_cc_cxo_clk", &gcc, 0xe7, &gpu_cc, 0x19 },
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{ "gpu_cc_gx_cxo_clk", &gcc, 0xe7, &gpu_cc, 0xe },
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{ "gpu_cc_gx_gfx3d_clk", &gcc, 0xe7, &gpu_cc, 0xb },
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{ "gpu_cc_sleep_clk", &gcc, 0xe7, &gpu_cc, 0x16 },
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{}
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};
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struct debugcc_platform sm6115_debugcc = {
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"sm6115",
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sm6115_clocks,
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};
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