mirror of
https://github.com/linux-msm/debugcc.git
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Add QCS404 platform
Add QCS404 measure clocks from the downstream kernel. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Bjorn Andersson
3
Makefile
3
Makefile
@@ -6,11 +6,12 @@ CFLAGS := -O2 -Wall -g
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LDFLAGS :=
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prefix := /usr/local
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SRCS := debugcc.c
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SRCS := debugcc.c qcs404.c
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OBJS := $(SRCS:.c=.o)
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$(OUT): $(OBJS)
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$(CC) -o $@ $^ $(LDFLAGS)
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ln -f $(OUT) qcs404-debugcc
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clean:
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rm -f $(OUT) $(OBJS) *-debugcc
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198
qcs404.c
Normal file
198
qcs404.c
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@@ -0,0 +1,198 @@
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/*
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* Copyright (c) 2019, Linaro Ltd.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/mman.h>
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#include <err.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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#define GCC_BASE 0x01800000
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#define GCC_SIZE 0x80000
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#define GCC_DEBUG_CLK_CTL 0x74000
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#define GCC_CLOCK_FREQ_MEASURE_CTL 0x74004
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#define GCC_CLOCK_FREQ_MEASURE_STATUS 0x74008
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#define GCC_XO_DIV4_CBCR 0x30034
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static struct debug_mux gcc;
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static struct debug_mux gcc = {
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.phys = GCC_BASE,
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.size = GCC_SIZE,
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.enable_reg = GCC_DEBUG_CLK_CTL,
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.enable_mask = BIT(16),
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.mux_reg = GCC_DEBUG_CLK_CTL,
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.mux_mask = 0x1ff,
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.div_reg = GCC_DEBUG_CLK_CTL,
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.div_shift = 12,
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.div_mask = 0xf << 12,
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.xo_div4_reg = GCC_XO_DIV4_CBCR,
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.debug_ctl_reg = GCC_CLOCK_FREQ_MEASURE_CTL,
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.debug_status_reg = GCC_CLOCK_FREQ_MEASURE_STATUS,
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};
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static struct debug_mux turing = {
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.phys = 0x800000,
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.size = 0x30000,
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.enable_reg = 0x22008,
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.enable_mask = BIT(0),
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.mux_reg = 0x22000,
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.mux_mask = 0xffff,
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.div_mask = 0,
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.ahb_reg = 0x5e004,
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.ahb_mask = BIT(31),
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};
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static struct measure_clk qcs404_clocks[] = {
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{ "snoc_clk", &gcc, 0, 4 },
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{ "gcc_sys_noc_usb3_clk", &gcc, 1, 4 },
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{ "pnoc_clk", &gcc, 8, 4 },
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{ "gcc_pcnoc_usb2_clk", &gcc, 9, 4 },
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{ "gcc_pcnoc_usb3_clk", &gcc, 10, 4 },
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{ "gcc_gp1_clk", &gcc, 16, 4 },
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{ "gcc_gp2_clk", &gcc, 17, 4 },
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{ "gcc_gp3_clk", &gcc, 18, 4 },
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{ "gcc_bimc_gfx_clk", &gcc, 45, 4 },
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{ "aon_clk_src", &gcc, 50, 1, &turing, 1, 4 },
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{ "turing_wrapper_aon_clk", &gcc, 50, 1, &turing, 2, 4 },
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{ "turing_wrapper_cnoc_sway_aon_clk", &gcc, 50, 1, &turing, 3, 4 },
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{ "turing_wrapper_qos_ahbs_aon_clk", &gcc, 50, 1, &turing, 4, 4 },
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{ "q6ss_ahbm_aon_clk", &gcc, 50, 1, &turing, 5, 4 },
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{ "q6ss_ahbs_aon_clk", &gcc, 50, 1, &turing, 6, 4},
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{ "turing_wrapper_bus_timeout_aon_clk", &gcc, 50, 1, &turing, 7, 4 },
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{ "turing_wrapper_rscc_aon_clk", &gcc, 50, 1, &turing, 8, 4 },
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{ "q6ss_alt_reset_aon_clk", &gcc, 50, 1, &turing, 10, 4 },
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{ "qos_fixed_lat_counter_clk_src", &gcc, 50, 1, &turing, 11, 4 },
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{ "turing_wrapper_qos_dmonitor_fixed_lat_counter_clk", &gcc, 50, 1, &turing, 12, 4 },
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{ "turing_wrapper_qos_danger_fixed_lat_counter_clk", &gcc, 50, 1, &turing, 13, 4 },
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{ "q6_xo_clk_src", &gcc, 50, 1, &turing, 14, 4 },
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{ "qos_xo_clk_src", &gcc, 50, 1, &turing, 15, 4 },
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{ "turing_wrapper_qos_xo_lat_counter_clk", &gcc, 50, 1, &turing, 16, 4 },
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{ "bcr_slp_clk_src", &gcc, 50, 1, &turing, 19, 4 },
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{ "q6ss_bcr_slp_clk", &gcc, 50, 1, &turing, 20, 4 },
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{ "turing_wrapper_cnoc_ahbs_clk", &gcc, 50, 1, &turing, 28, 4 },
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{ "q6ss_q6_axim_clk", &gcc, 50, 1, &turing, 29, 4 },
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{ "q6ss_sleep_clk_src", &gcc, 50, 1, &turing, 33, 4 },
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{ "qdsp6ss_xo_clk", &gcc, 50, 1, &turing, 36, 4 },
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{ "qdsp6ss_sleep_clk", &gcc, 50, 1, &turing, 37, 4 },
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{ "q6ss_dbg_in_clk", &gcc, 50, 1, &turing, 39, 4 },
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{ "gcc_usb_hs_system_clk", &gcc, 96, 4 },
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{ "gcc_usb_hs_inactivity_timers_clk", &gcc, 98, 4 },
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{ "gcc_usb2a_phy_sleep_clk", &gcc, 99, 4 },
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{ "gcc_usb_hs_phy_cfg_ahb_clk", &gcc, 100, 4 },
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{ "gcc_usb20_mock_utmi_clk", &gcc, 101, 4 },
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{ "gcc_sdcc1_apps_clk", &gcc, 104, 4 },
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{ "gcc_sdcc1_ahb_clk", &gcc, 105, 4 },
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{ "gcc_sdcc1_ice_core_clk", &gcc, 106, 4 },
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{ "gcc_sdcc2_apps_clk", &gcc, 112, 4 },
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{ "gcc_sdcc2_ahb_clk", &gcc, 113, 4 },
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{ "gcc_usb30_master_clk", &gcc, 120, 4 },
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{ "gcc_usb30_sleep_clk", &gcc, 121, 4 },
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{ "gcc_usb30_mock_utmi_clk", &gcc, 122, 4 },
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{ "gcc_usb3_phy_pipe_clk", &gcc, 123, 4 },
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{ "gcc_usb3_phy_aux_clk", &gcc, 124, 4 },
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{ "gcc_eth_axi_clk", &gcc, 128, 4 },
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{ "gcc_eth_rgmii_clk", &gcc, 129, 4 },
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{ "gcc_eth_slave_ahb_clk", &gcc, 130, 4 },
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{ "gcc_eth_ptp_clk", &gcc, 131, 4 },
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{ "gcc_blsp1_ahb_clk", &gcc, 136, 4 },
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{ "gcc_blsp1_qup1_spi_apps_clk", &gcc, 138, 4 },
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{ "wcnss_m_clk", &gcc, 138, 4 },
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{ "gcc_blsp1_qup1_i2c_apps_clk", &gcc, 139, 4 },
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{ "gcc_blsp1_uart1_apps_clk", &gcc, 140, 4 },
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{ "gcc_blsp1_qup2_spi_apps_clk", &gcc, 142, 4 },
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{ "gcc_blsp1_qup2_i2c_apps_clk", &gcc, 143, 4 },
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{ "gcc_blsp1_uart2_apps_clk", &gcc, 144, 4 },
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{ "gcc_blsp1_qup3_spi_apps_clk", &gcc, 146, 4 },
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{ "gcc_blsp1_qup3_i2c_apps_clk", &gcc, 147, 4 },
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{ "gcc_blsp1_qup4_spi_apps_clk", &gcc, 148, 4 },
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{ "gcc_blsp1_qup4_i2c_apps_clk", &gcc, 149, 4 },
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{ "gcc_blsp1_uart3_apps_clk", &gcc, 150, 4 },
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{ "gcc_blsp1_qup0_spi_apps_clk", &gcc, 152, 4 },
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{ "gcc_blsp1_qup0_i2c_apps_clk", &gcc, 153, 4 },
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{ "gcc_blsp1_uart0_apps_clk", &gcc, 154, 4 },
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{ "gcc_blsp2_ahb_clk", &gcc, 160, 4 },
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{ "gcc_blsp2_qup0_i2c_apps_clk", &gcc, 162, 4 },
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{ "gcc_blsp2_qup0_spi_apps_clk", &gcc, 163, 4 },
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{ "gcc_blsp2_uart0_apps_clk", &gcc, 164, 4 },
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{ "gcc_pcie_0_slv_axi_clk", &gcc, 168, 4 },
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{ "gcc_pcie_0_mstr_axi_clk", &gcc, 169, 4 },
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{ "gcc_pcie_0_cfg_ahb_clk", &gcc, 170, 4 },
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{ "gcc_pcie_0_aux_clk", &gcc, 171, 4 },
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{ "gcc_pcie_0_pipe_clk", &gcc, 172, 4 },
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{ "pcie0_pipe_clk", &gcc, 173, 1 },
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{ "qpic_clk", &gcc, 192, 4 },
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{ "gcc_pdm_ahb_clk", &gcc, 208, 4 },
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{ "gcc_pdm2_clk", &gcc, 210, 4 },
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{ "gcc_pwm0_xo512_clk", &gcc, 211, 4 },
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{ "gcc_pwm1_xo512_clk", &gcc, 212, 4 },
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{ "gcc_pwm2_xo512_clk", &gcc, 213, 4 },
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{ "gcc_prng_ahb_clk", &gcc, 216, 4 },
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{ "gcc_geni_ir_s_clk", &gcc, 238, 4 },
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{ "gcc_boot_rom_ahb_clk", &gcc, 248, 4 },
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{ "ce1_clk", &gcc, 312, 4 },
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{ "bimc_clk", &gcc, 346, 4 },
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{ "bimc_fsm_ddr_clk", &gcc, 350, 1 },
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{ "gcc_apss_ahb_clk", &gcc, 360, 4 },
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{ "gcc_dcc_clk", &gcc, 441, 4 },
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{ "gcc_oxili_gfx3d_clk", &gcc, 490, 4 },
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{ "gcc_oxili_ahb_clk", &gcc, 491, 4 },
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{ "gcc_mdss_hdmi_pclk_clk", &gcc, 497, 4 },
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{ "gcc_mdss_hdmi_app_clk", &gcc, 498, 4 },
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{ "gcc_mdss_ahb_clk", &gcc, 502, 4 },
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{ "gcc_mdss_axi_clk", &gcc, 503, 4 },
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{ "gcc_mdss_pclk0_clk", &gcc, 504, 4 },
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{ "gcc_mdss_mdp_clk", &gcc, 505, 4 },
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{ "gcc_mdss_vsync_clk", &gcc, 507, 4 },
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{ "gcc_mdss_byte0_clk", &gcc, 508, 4 },
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{ "gcc_mdss_esc0_clk", &gcc, 509, 4 },
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{}
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};
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struct debugcc_platform qcs404_debugcc = {
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"qcs404",
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qcs404_clocks,
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};
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