mirror of
https://github.com/linux-msm/debugcc.git
synced 2026-02-25 13:12:32 -08:00
Add SM6350 / lagoon
This commit is contained in:
Konrad Dybcio
committed by
Bjorn Andersson
Bjorn Andersson
parent
6a32f8a8bd
commit
5341f2d08e
2
Makefile
2
Makefile
@@ -15,6 +15,7 @@ SRCS := debugcc.c \
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sdm845.c \
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sm6115.c \
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sm6125.c \
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sm6350.c \
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sm8150.c \
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sm8250.c \
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sm8350.c \
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@@ -32,6 +33,7 @@ $(OUT): $(OBJS)
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ln -f $(OUT) sdm845-debugcc
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ln -f $(OUT) sm6115-debugcc
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ln -f $(OUT) sm6125-debugcc
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ln -f $(OUT) sm6350-debugcc
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ln -f $(OUT) sm8150-debugcc
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ln -f $(OUT) sm8250-debugcc
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ln -f $(OUT) sm8350-debugcc
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@@ -51,6 +51,7 @@ static const struct debugcc_platform *platforms[] = {
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&sdm845_debugcc,
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&sm6115_debugcc,
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&sm6125_debugcc,
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&sm6350_debugcc,
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&sm8150_debugcc,
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&sm8250_debugcc,
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&sm8350_debugcc,
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@@ -97,6 +97,7 @@ extern struct debugcc_platform sc8280xp_debugcc;
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extern struct debugcc_platform sdm845_debugcc;
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extern struct debugcc_platform sm6115_debugcc;
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extern struct debugcc_platform sm6125_debugcc;
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extern struct debugcc_platform sm6350_debugcc;
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extern struct debugcc_platform sm8150_debugcc;
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extern struct debugcc_platform sm8250_debugcc;
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extern struct debugcc_platform sm8350_debugcc;
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228
sm6350.c
Normal file
228
sm6350.c
Normal file
@@ -0,0 +1,228 @@
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// SPDX-License-Identifier: BSD-3-Clause
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/* Copyright (c) 2022, Linaro Limited */
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#include <sys/mman.h>
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#include <err.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <unistd.h>
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#include "debugcc.h"
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static struct debug_mux cpu_cc = {
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.phys = 0x182a0000,
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.size = 0x1000,
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.block_name = "cpu",
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.enable_reg = 0x18,
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.enable_mask = BIT(0),
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.mux_reg = 0x18,
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.mux_mask = 0x7f << 4,
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.mux_shift = 4,
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.div_reg = 0x18,
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.div_mask = 0xf << 11,
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.div_shift = 11,
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.div_val = 8,
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};
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static struct debug_mux disp_cc = {
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.phys = 0xaf00000,
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.size = 0x20000,
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.block_name = "disp",
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.enable_reg = 0x3004,
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.enable_mask = BIT(0),
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.mux_reg = 0x7000,
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.mux_mask = 0xff,
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.div_reg = 0x3000,
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.div_mask = 0x3,
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.div_val = 4,
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};
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static struct debug_mux gcc = {
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.phys = 0x100000,
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.size = 0x1f0000,
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.enable_reg = 0x3500c,
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.enable_mask = BIT(0),
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.mux_reg = 0x35f08,
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.mux_mask = 0x3ff,
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.div_reg = 0x35008,
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.div_mask = 0x7,
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.div_val = 4,
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.xo_div4_reg = 0x2c008,
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.debug_ctl_reg = 0x35f24,
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.debug_status_reg = 0x35f28,
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};
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static struct debug_mux gpu_cc = {
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.phys = 0x3d90000,
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.size = 0x9000,
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.block_name = "gpu",
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.enable_reg = 0x1100,
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.enable_mask = BIT(0),
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.mux_reg = 0x1568,
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.mux_mask = 0xff,
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.div_reg = 0x10fc,
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.div_mask = 0x3,
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.div_val = 2,
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};
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static struct measure_clk sm6350_clocks[] = {
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{ "l3_clk", &gcc, 0xbe, &cpu_cc, 0x41 },
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{ "pwrcl_clk", &gcc, 0xbe, &cpu_cc, 0x21 },
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{ "perfcl_clk", &gcc, 0xbe, &cpu_cc, 0x25 },
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//{ "cam_cc_debug_mux", &gcc, 0x3f },
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//{ "cpu_cc_debug_mux", &gcc, 0xbe },
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//{ "disp_cc_debug_mux", &gcc, 0x40 },
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{ "gcc_aggre_ufs_phy_axi_clk", &gcc, 0xe2 },
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{ "gcc_aggre_usb3_prim_axi_clk", &gcc, 0xe1 },
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{ "gcc_boot_rom_ahb_clk", &gcc, 0x80 },
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{ "gcc_camera_ahb_clk", &gcc, 0x32 },
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{ "gcc_camera_axi_clk", &gcc, 0x36 },
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{ "gcc_camera_throttle_nrt_axi_clk", &gcc, 0x4a },
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{ "gcc_camera_throttle_rt_axi_clk", &gcc, 0x39 },
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{ "gcc_camera_xo_clk", &gcc, 0x3c },
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{ "gcc_ce1_ahb_clk", &gcc, 0x92 },
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{ "gcc_ce1_axi_clk", &gcc, 0x91 },
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{ "gcc_ce1_clk", &gcc, 0x90 },
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{ "gcc_cfg_noc_usb3_prim_axi_clk", &gcc, 0x18 },
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{ "gcc_cpuss_ahb_clk", &gcc, 0xb7 },
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{ "gcc_cpuss_gnoc_clk", &gcc, 0xb8 },
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{ "gcc_cpuss_rbcpr_clk", &gcc, 0xb9 },
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{ "gcc_ddrss_gpu_axi_clk", &gcc, 0xa5 },
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{ "gcc_disp_ahb_clk", &gcc, 0x33 },
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{ "gcc_disp_axi_clk", &gcc, 0x37 },
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{ "gcc_disp_cc_sleep_clk", &gcc, 0x49 },
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{ "gcc_disp_cc_xo_clk", &gcc, 0x48 },
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{ "gcc_disp_gpll0_clk", &gcc, 0x44 },
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{ "gcc_disp_throttle_axi_clk", &gcc, 0x3a },
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{ "gcc_disp_xo_clk", &gcc, 0x3d },
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{ "gcc_gp1_clk", &gcc, 0xc5 },
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{ "gcc_gp2_clk", &gcc, 0xc6 },
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{ "gcc_gp3_clk", &gcc, 0xc7 },
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{ "gcc_gpu_cfg_ahb_clk", &gcc, 0x105 },
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{ "gcc_gpu_gpll0_clk", &gcc, 0x10b },
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{ "gcc_gpu_gpll0_div_clk", &gcc, 0x10c },
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{ "gcc_gpu_memnoc_gfx_clk", &gcc, 0x108 },
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{ "gcc_gpu_snoc_dvm_gfx_clk", &gcc, 0x109 },
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{ "gcc_npu_axi_clk", &gcc, 0x116 },
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{ "gcc_npu_bwmon_axi_clk", &gcc, 0x11c },
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{ "gcc_npu_bwmon_dma_cfg_ahb_clk", &gcc, 0x11d },
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{ "gcc_npu_bwmon_dsp_cfg_ahb_clk", &gcc, 0x11e },
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{ "gcc_npu_cfg_ahb_clk", &gcc, 0x115 },
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{ "gcc_npu_dma_clk", &gcc, 0x11b },
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{ "gcc_npu_gpll0_clk", &gcc, 0x118 },
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{ "gcc_npu_gpll0_div_clk", &gcc, 0x119 },
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{ "gcc_pdm2_clk", &gcc, 0x7d },
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{ "gcc_pdm_ahb_clk", &gcc, 0x7b },
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{ "gcc_pdm_xo4_clk", &gcc, 0x7c },
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{ "gcc_prng_ahb_clk", &gcc, 0x7e },
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{ "gcc_qupv3_wrap0_core_2x_clk", &gcc, 0x6a },
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{ "gcc_qupv3_wrap0_core_clk", &gcc, 0x69 },
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{ "gcc_qupv3_wrap0_s0_clk", &gcc, 0x6b },
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{ "gcc_qupv3_wrap0_s1_clk", &gcc, 0x6c },
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{ "gcc_qupv3_wrap0_s2_clk", &gcc, 0x6d },
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{ "gcc_qupv3_wrap0_s3_clk", &gcc, 0x6e },
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{ "gcc_qupv3_wrap0_s4_clk", &gcc, 0x6f },
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{ "gcc_qupv3_wrap0_s5_clk", &gcc, 0x70 },
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{ "gcc_qupv3_wrap1_core_2x_clk", &gcc, 0x71 },
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{ "gcc_qupv3_wrap1_core_clk", &gcc, 0x72 },
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{ "gcc_qupv3_wrap1_s0_clk", &gcc, 0x75 },
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{ "gcc_qupv3_wrap1_s1_clk", &gcc, 0x76 },
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{ "gcc_qupv3_wrap1_s2_clk", &gcc, 0x77 },
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{ "gcc_qupv3_wrap1_s3_clk", &gcc, 0x78 },
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{ "gcc_qupv3_wrap1_s4_clk", &gcc, 0x79 },
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{ "gcc_qupv3_wrap1_s5_clk", &gcc, 0x7a },
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{ "gcc_qupv3_wrap_0_m_ahb_clk", &gcc, 0x67 },
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{ "gcc_qupv3_wrap_0_s_ahb_clk", &gcc, 0x68 },
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{ "gcc_qupv3_wrap_1_m_ahb_clk", &gcc, 0x73 },
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{ "gcc_qupv3_wrap_1_s_ahb_clk", &gcc, 0x74 },
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{ "gcc_sdcc1_ahb_clk", &gcc, 0x112 },
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{ "gcc_sdcc1_apps_clk", &gcc, 0x113 },
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{ "gcc_sdcc1_ice_core_clk", &gcc, 0x114 },
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{ "gcc_sdcc2_ahb_clk", &gcc, 0x66 },
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{ "gcc_sdcc2_apps_clk", &gcc, 0x65 },
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{ "gcc_sys_noc_cpuss_ahb_clk", &gcc, 0x9 },
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{ "gcc_ufs_phy_ahb_clk", &gcc, 0xc8 },
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{ "gcc_ufs_phy_axi_clk", &gcc, 0xcc },
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{ "gcc_ufs_phy_ice_core_clk", &gcc, 0xd1 },
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{ "gcc_ufs_phy_phy_aux_clk", &gcc, 0xd2 },
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{ "gcc_ufs_phy_rx_symbol_0_clk", &gcc, 0xca },
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{ "gcc_ufs_phy_rx_symbol_1_clk", &gcc, 0xcb },
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{ "gcc_ufs_phy_tx_symbol_0_clk", &gcc, 0xc9 },
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{ "gcc_ufs_phy_unipro_core_clk", &gcc, 0xd0 },
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{ "gcc_usb30_prim_master_clk", &gcc, 0x5b },
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{ "gcc_usb30_prim_mock_utmi_clk", &gcc, 0x5d },
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{ "gcc_usb30_prim_sleep_clk", &gcc, 0x5c },
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{ "gcc_usb3_prim_phy_aux_clk", &gcc, 0x5e },
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{ "gcc_usb3_prim_phy_com_aux_clk", &gcc, 0x5f },
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{ "gcc_usb3_prim_phy_pipe_clk", &gcc, 0x60 },
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{ "gcc_video_ahb_clk", &gcc, 0x31 },
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{ "gcc_video_axi_clk", &gcc, 0x35 },
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{ "gcc_video_throttle_axi_clk", &gcc, 0x38 },
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{ "gcc_video_xo_clk", &gcc, 0x3b },
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//{ "gpu_cc_debug_mux", &gcc, 0x107 },
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//{ "mc_cc_debug_mux", &gcc, 0xab },
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{ "measure_only_cnoc_clk", &gcc, 0x14 },
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{ "measure_only_ipa_2x_clk", &gcc, 0xec },
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{ "measure_only_snoc_clk", &gcc, 0x07 },
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//{ "npu_cc_debug_mux", &gcc, 0x11a },
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//{ "video_cc_debug_mux", &gcc, 0x41 },
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{ "disp_cc_mdss_ahb_clk", &gcc, 0x40, &disp_cc, 0x14 },
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{ "disp_cc_mdss_byte0_clk", &gcc, 0x40, &disp_cc, 0xc },
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{ "disp_cc_mdss_byte0_intf_clk", &gcc, 0x40, &disp_cc, 0xd },
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{ "disp_cc_mdss_dp_aux_clk", &gcc, 0x40, &disp_cc, 0x13 },
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{ "disp_cc_mdss_dp_crypto_clk", &gcc, 0x40, &disp_cc, 0x11 },
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{ "disp_cc_mdss_dp_link_clk", &gcc, 0x40, &disp_cc, 0xf },
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{ "disp_cc_mdss_dp_link_intf_clk", &gcc, 0x40, &disp_cc, 0x10 },
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{ "disp_cc_mdss_dp_pixel_clk", &gcc, 0x40, &disp_cc, 0x12 },
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{ "disp_cc_mdss_esc0_clk", &gcc, 0x40, &disp_cc, 0xe },
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{ "disp_cc_mdss_mdp_clk", &gcc, 0x40, &disp_cc, 0x8 },
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{ "disp_cc_mdss_mdp_lut_clk", &gcc, 0x40, &disp_cc, 0xa },
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{ "disp_cc_mdss_non_gdsc_ahb_clk", &gcc, 0x40, &disp_cc, 0x15 },
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{ "disp_cc_mdss_pclk0_clk", &gcc, 0x40, &disp_cc, 0x7 },
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{ "disp_cc_mdss_rot_clk", &gcc, 0x40, &disp_cc, 0x9 },
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{ "disp_cc_mdss_rscc_ahb_clk", &gcc, 0x40, &disp_cc, 0x17 },
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{ "disp_cc_mdss_rscc_vsync_clk", &gcc, 0x40, &disp_cc, 0x16 },
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{ "disp_cc_mdss_vsync_clk", &gcc, 0x40, &disp_cc, 0xb },
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{ "disp_cc_sleep_clk", &gcc, 0x40, &disp_cc, 0x1d },
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{ "disp_cc_xo_clk", &gcc, 0x40, &disp_cc, 0x1e },
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{ "gpu_cc_acd_ahb_clk", &gcc, 0x107, &gpu_cc, 0x20 },
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{ "gpu_cc_acd_cxo_clk", &gcc, 0x107, &gpu_cc, 0x1f },
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{ "gpu_cc_ahb_clk", &gcc, 0x107, &gpu_cc, 0x11 },
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{ "gpu_cc_crc_ahb_clk", &gcc, 0x107, &gpu_cc, 0x12 },
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{ "gpu_cc_cx_gfx3d_clk", &gcc, 0x107, &gpu_cc, 0x1a },
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{ "gpu_cc_cx_gfx3d_slv_clk", &gcc, 0x107, &gpu_cc, 0x1b },
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{ "gpu_cc_cx_gmu_clk", &gcc, 0x107, &gpu_cc, 0x19 },
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{ "gpu_cc_cx_snoc_dvm_clk", &gcc, 0x107, &gpu_cc, 0x16 },
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{ "gpu_cc_cxo_aon_clk", &gcc, 0x107, &gpu_cc, 0xb },
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{ "gpu_cc_cxo_clk", &gcc, 0x107, &gpu_cc, 0xa },
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{ "gpu_cc_gx_cxo_clk", &gcc, 0x107, &gpu_cc, 0xf },
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{ "gpu_cc_gx_gfx3d_clk", &gcc, 0x107, &gpu_cc, 0xc },
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{ "gpu_cc_gx_gmu_clk", &gcc, 0x107, &gpu_cc, 0x10 },
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{ "gpu_cc_gx_vsense_clk", &gcc, 0x107, &gpu_cc, 0xd },
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{}
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};
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struct debugcc_platform sm6350_debugcc = {
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"sm6350",
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sm6350_clocks,
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};
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