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Author SHA1 Message Date
Alex Deucher eacf3e149e drm/amdgpu: make wb 256bit function names consistent 
Use a lower case b to be consistent with the other wb functions.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:59 -04:00
Yong Zhao 51ac7eec62 drm/amdgpu: Support IOMMU on Raven 
We achieved that by setting S(SYSTEM) and P(PDE as PTE) bit to 1 for
PDEs and setting S bit to 1 for PTEs when the corresponding addresses
are not occupied by gpu driver allocated buffers.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:58 -04:00
Yong Zhao 2046d46db9 drm/amdgpu: Add a parameter to amdgpu_bo_create() 
The parameter init_value contains the value to which we initialized
VRAM bo when AMDGPU_GEM_CREATE_VRAM_CLEARED flag is set.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:58 -04:00
Christian König 078af1a3e9 drm/amdgpu: use amdgpu_bo_free_kernel more often 
Saves us even more loc.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:57 -04:00
Christian König a4a0277789 drm/amdgpu: use amdgpu_bo_create_kernel more often 
Saves us quite a bunch of loc.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:56 -04:00
Christian König 9d903cbd99 drm/amdgpu: add amdgpu_bo_create_reserved 
Same as amdgpu_bo_create_kernel, but keeps the BO reserved.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:56 -04:00
Christian König 53766e5ada drm/amdgpu: improve amdgpu_bo_create_kernel 
Make allocating the new BO optional.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:55 -04:00
Christian König ed5b89c69c drm/amdgpu: shadow and mn list are mutually exclusive 
Save some memory because only one of those is used at all times.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:54 -04:00
Christian König 9124a3983b drm/amdgpu: move some defines around 
Move amdgpu_bo and related structures into amdgpu_object.h.

Move amdgpu_bo_list structures to the amdgpu_bo_list functions.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:54 -04:00
Christian König 7ecc245a8c drm/amdgpu: consistent use u64_to_user_ptr 
Instead of open coding the conversion from u64 to pointers.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:53 -04:00
Christian König f5e1c740af drm/amdgpu: cleanup kptr handling 
Don't keep around the same pointer twice.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:53 -04:00
Evan Quan 4dbc9908d4 drm/amd/powerplay: update didt configs 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:52 -04:00
Evan Quan de3be0f307 drm/amd/powerplay: updated vega10 fan control 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:51 -04:00
Evan Quan ba219b3c18 drm/amdgpu: update vega10 golden setting 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Ken Wang <ken.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:51 -04:00
Rex Zhu e55687efe5 drm/amd/powerplay: delete PCC error message in smu7_hwmgr.c 
In some asics,Really no need to program PCC HW register.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:50 -04:00
Frank Min 51668b0b1b drm/amdgpu/sdma4: Enable sdma poll mem addr on vega10 for SRIOV 
While doing flr on VFs, there is possibility to lost the doorbell
writing for sdma, so enable poll mem for sdma, then sdma fw would
check the pollmem holding wptr.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:49 -04:00
Frank Min 81fe3f35ac drm/amdgpu/uvd7: optimize uvd initialization sequence for SRIOV 
1.Since in sriov there is no need of decoding, so skip the related code;
2.Vcpu boot up and umc enable need to take at the end of the init sequence;

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:49 -04:00
Frank Min a1aacc9759 drm/amdgpu/vce4: optimize vce 4.0 init table sequence for SRIOV 
Optimize init table sequence for sriov.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:48 -04:00
Frank Min 4ed11d793c drm/amdgpu: According hardware design revert vce and uvd doorbell assignment 
Now uvd doorbell is from 0xf8-0xfb and vce doorbell is from 0xfc-0xff

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:47 -04:00
Frank Min a1b9022a3b drm/amdgpu: Skip uvd and vce ring test for SRIOV 
Since rptr would not be accessed on later secure asics in sriov, remove
the ring test.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:47 -04:00
Frank Min 088c69aad4 drm/amdgpu/vce4: Remove vce interrupt enable related code for sriov 
Interrupt enable is contained in vce init table and this register could
not be accessed in secure ASICs, so just remove it.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:46 -04:00
Frank Min 257deb8cc6 drm/amdgpu: Enable uvd and vce gpu re-init for SRIOV gpu reset 
Add uvd and vce re-init after gpu reset.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:45 -04:00
Frank Min ab2b2e4f8b drm/amdgpu: Clear vce&uvd ring wptr for SRIOV 
MMSCH FW need to get the wptr from 0 after it get the mailbox request
from driver, since every time kick the mailbox, mmsch thinks that it
is the first time engine start to initialize.

Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Xiangliang.Yu <Xiangliang.Yu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:45 -04:00
Yong Zhao 330df03b3a drm/amdgpu: Add support for filling a buffer with 64 bit value 
That function will be used later to support setting a page table
block with 64 bit value.

Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:44 -04:00
Leo Liu aef060e114 drm/amdgpu: disable vcn power control for now 
The dpm control for vcn has been moved to firmware, kernel always spins
"amdgpu: [powerplay] pp_dpm_powergate_uvd was not implemented", each
time when application runs, disable it for now till pg/cg. Also remove
clock manual setting when dpm disabled, which was inherited from uvd.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2017-08-15 14:45:44 -04:00