[Testing] Add a lot more missing instruction tests

src/xenia/cpu/ppc/testing/instr_addx.s

@@ -0,0 +1,90 @@
+test_addx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000002000
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addx_1_constant:
+  li r4, 0x1000
+  li r5, 0x2000
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addx_overflow:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000001
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_addx_negative:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000001
+  add. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_addcx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000002000
+  addc. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addcx_overflow:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000001
+  addc. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_addex_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000002000
+  #_ REGISTER_IN r0 0x0000000020000000
+  mtxer r0
+  adde. r3, r4, r5
+  mfcr r12
+  mfxer r6
+  blr
+  #_ REGISTER_OUT r3 0x0000000000003001
+  #_ REGISTER_OUT r6 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addmex_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r0 0x0000000000000000
+  mtxer r0
+  addme. r3, r4
+  mfcr r12
+  mfxer r6
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000FFF
+  #_ REGISTER_OUT r6 0x0000000020000000
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_addzex_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r0 0x0000000000000000
+  mtxer r0
+  addze. r3, r4
+  mfcr r12
+  mfxer r6
+  blr
+  #_ REGISTER_OUT r3 0x0000000000001000
+  #_ REGISTER_OUT r6 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000040000000

src/xenia/cpu/ppc/testing/instr_cntlzdx.s

@@ -0,0 +1,27 @@
+test_cntlzdx_1:
+  #_ REGISTER_IN r4 0x0000000000000001
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000003F
+  #_ REGISTER_OUT r4 0x0000000000000001
+
+test_cntlzdx_2:
+  #_ REGISTER_IN r4 0x8000000000000000
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x8000000000000000
+
+test_cntlzdx_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000040
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_cntlzdx_4:
+  #_ REGISTER_IN r4 0x0000000100000000
+  cntlzd. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000001F
+  #_ REGISTER_OUT r4 0x0000000100000000

src/xenia/cpu/ppc/testing/instr_cntlzwx.s

@@ -0,0 +1,27 @@
+test_cntlzwx_1:
+  #_ REGISTER_IN r4 0x0000000000000001
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000001F
+  #_ REGISTER_OUT r4 0x0000000000000001
+
+test_cntlzwx_2:
+  #_ REGISTER_IN r4 0x0000000080000000
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0x0000000080000000
+
+test_cntlzwx_3:
+  #_ REGISTER_IN r4 0x0000000000000000
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000020
+  #_ REGISTER_OUT r4 0x0000000000000000
+
+test_cntlzwx_4:
+  #_ REGISTER_IN r4 0x0000000000010000
+  cntlzw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000000F
+  #_ REGISTER_OUT r4 0x0000000000010000

src/xenia/cpu/ppc/testing/instr_dcbf.s

@@ -0,0 +1,31 @@
+test_dcbf_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbf_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbf_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbf_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbf r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbst.s

@@ -0,0 +1,31 @@
+test_dcbst_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbst_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbst_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbst_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbt.s

@@ -0,0 +1,31 @@
+test_dcbt_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbt_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbt_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbt_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbt r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbtst.s

@@ -0,0 +1,31 @@
+test_dcbtst_1:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 0
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 0
+
+test_dcbtst_2:
+  #_ REGISTER_IN r4 0x00001000
+  #_ REGISTER_IN r5 64
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00001000
+  #_ REGISTER_OUT r5 64
+
+test_dcbtst_3:
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x00001000
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x00001000
+
+test_dcbtst_4:
+  #_ REGISTER_IN r4 0x00002000
+  #_ REGISTER_IN r5 128
+  dcbtst r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x00002000
+  #_ REGISTER_OUT r5 128

src/xenia/cpu/ppc/testing/instr_dcbz.s

@@ -0,0 +1,39 @@
+test_dcbz_1:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 0
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 0
+  #_ MEMORY_OUT 10001000 00000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz_2:
+  #_ MEMORY_IN 0x0000000010001040 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 64
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 64
+  #_ MEMORY_OUT 10001040 00000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz_3:
+  #_ MEMORY_IN 0x0000000010001000 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0
+  #_ REGISTER_IN r5 0x0000000010001000
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r5 0x0000000010001000
+  #_ MEMORY_OUT 10001000 00000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz_4:
+  #_ MEMORY_IN 0x0000000010001080 [FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF, FF]
+  #_ REGISTER_IN r4 0x0000000010001000
+  #_ REGISTER_IN r5 128
+  dcbz r4, r5
+  blr
+  #_ REGISTER_OUT r4 0x0000000010001000
+  #_ REGISTER_OUT r5 128
+  #_ MEMORY_OUT 10001080 00000000000000000000000000000000000000000000000000000000000000

src/xenia/cpu/ppc/testing/instr_dcbz128.s

@@ -0,0 +1,28 @@
+test_dcbz128_1:
+  # Clear 128 bytes starting at aligned address
+  #_ MEMORY_IN 10001000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80
+  li r4, 0x1000
+  oris r4, r4, 0x1000
+  dcbz128 r0, r4
+  blr
+  #_ MEMORY_OUT 10001000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz128_2:
+  # Clear 128 bytes with non-zero base register
+  #_ MEMORY_IN 10002000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80
+  li r3, 0x1000
+  oris r3, r3, 0x1000
+  li r4, 0x1000
+  dcbz128 r3, r4
+  blr
+  #_ MEMORY_OUT 10002000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+
+test_dcbz128_3:
+  # Verify unaligned address is rounded down to 128-byte boundary
+  # Address 10003040 should clear block starting at 10003000
+  #_ MEMORY_IN 10003000 0102030405060708090A0B0C0D0E0F10111213141516171819191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F80
+  li r4, 0x3040
+  oris r4, r4, 0x1000
+  dcbz128 r0, r4
+  blr
+  #_ MEMORY_OUT 10003000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

src/xenia/cpu/ppc/testing/instr_divdx.s

@@ -0,0 +1,89 @@
+test_divdx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divdx_1_constant:
+  li r4, 0x1000
+  li r5, 0x10
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divdx_negative:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFF000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF00
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_divdx_by_zero:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000000
+  divd. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r12 0x0000000020000000
+
+test_divdux_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divdu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divdux_large:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  divdu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_divwx_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divw. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divwx_negative:
+  #_ REGISTER_IN r4 0x00000000FFFFF000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divw. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x00000000FFFFFF00
+  #_ REGISTER_OUT r12 0x0000000080000000
+
+test_divwux_1:
+  #_ REGISTER_IN r4 0x0000000000001000
+  #_ REGISTER_IN r5 0x0000000000000010
+  divwu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000100
+  #_ REGISTER_OUT r12 0x0000000040000000
+
+test_divwux_large:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  #_ REGISTER_IN r5 0x0000000000000002
+  divwu. r3, r4, r5
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r12 0x0000000040000000

src/xenia/cpu/ppc/testing/instr_eieio.s

@@ -0,0 +1,13 @@
+test_eieio_1:
+  #_ REGISTER_IN r3 0x0000000000000001
+  eieio
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+
+test_eieio_2:
+  #_ REGISTER_IN r4 0x0000000012345678
+  #_ REGISTER_IN r5 0xABCDEF0123456789
+  eieio
+  blr
+  #_ REGISTER_OUT r4 0x0000000012345678
+  #_ REGISTER_OUT r5 0xABCDEF0123456789

src/xenia/cpu/ppc/testing/instr_eqvx.s

@@ -0,0 +1,35 @@
+test_eqvx_1:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+
+test_eqvx_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xAAAAAAAAAAAAAAAA
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xAAAAAAAAAAAAAAAA
+
+test_eqvx_3:
+  #_ REGISTER_IN r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_IN r5 0x5555555555555555
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000000
+  #_ REGISTER_OUT r4 0xAAAAAAAAAAAAAAAA
+  #_ REGISTER_OUT r5 0x5555555555555555
+
+test_eqvx_4:
+  #_ REGISTER_IN r4 0x123456789ABCDEF0
+  #_ REGISTER_IN r5 0x123456789ABCDEF0
+  eqv. r3, r4, r5
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x123456789ABCDEF0
+  #_ REGISTER_OUT r5 0x123456789ABCDEF0

src/xenia/cpu/ppc/testing/instr_extsbx.s

@@ -0,0 +1,27 @@
+test_extsbx_1:
+  #_ REGISTER_IN r4 0x000000000000007F
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007F
+  #_ REGISTER_OUT r4 0x000000000000007F
+
+test_extsbx_2:
+  #_ REGISTER_IN r4 0x0000000000000080
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFF80
+  #_ REGISTER_OUT r4 0x0000000000000080
+
+test_extsbx_3:
+  #_ REGISTER_IN r4 0x00000000000000FF
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000000000000FF
+
+test_extsbx_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  extsb. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_extshx.s

@@ -0,0 +1,27 @@
+test_extshx_1:
+  #_ REGISTER_IN r4 0x0000000000007FFF
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000007FFF
+  #_ REGISTER_OUT r4 0x0000000000007FFF
+
+test_extshx_2:
+  #_ REGISTER_IN r4 0x0000000000008000
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFF8000
+  #_ REGISTER_OUT r4 0x0000000000008000
+
+test_extshx_3:
+  #_ REGISTER_IN r4 0x000000000000FFFF
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x000000000000FFFF
+
+test_extshx_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  extsh. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_extswx.s

@@ -0,0 +1,27 @@
+test_extswx_1:
+  #_ REGISTER_IN r4 0x000000007FFFFFFF
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x000000007FFFFFFF
+  #_ REGISTER_OUT r4 0x000000007FFFFFFF
+
+test_extswx_2:
+  #_ REGISTER_IN r4 0x0000000080000000
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFF80000000
+  #_ REGISTER_OUT r4 0x0000000080000000
+
+test_extswx_3:
+  #_ REGISTER_IN r4 0x00000000FFFFFFFF
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0x00000000FFFFFFFF
+
+test_extswx_4:
+  #_ REGISTER_IN r4 0x0000000000000001
+  extsw. r3, r4
+  blr
+  #_ REGISTER_OUT r3 0x0000000000000001
+  #_ REGISTER_OUT r4 0x0000000000000001

src/xenia/cpu/ppc/testing/instr_fabsx.s

@@ -0,0 +1,27 @@
+test_fabsx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+
+test_fabsx_2:
+  #_ REGISTER_IN f4 [BFF0000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [3FF0000000000000]
+  #_ REGISTER_OUT f4 [BFF0000000000000]
+
+test_fabsx_3:
+  #_ REGISTER_IN f4 [8000000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [8000000000000000]
+
+test_fabsx_4:
+  #_ REGISTER_IN f4 [C005000000000000]
+  fabs. f3, f4
+  blr
+  #_ REGISTER_OUT f3 [4005000000000000]
+  #_ REGISTER_OUT f4 [C005000000000000]

src/xenia/cpu/ppc/testing/instr_faddsx.s

@@ -0,0 +1,35 @@
+test_faddsx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4008000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_faddsx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [BFF0000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [BFF0000000000000]
+
+test_faddsx_3:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4010000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_faddsx_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fadds. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_faddx.s

@@ -0,0 +1,35 @@
+test_faddx_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4008000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_faddx_2:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [BFF0000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [BFF0000000000000]
+
+test_faddx_3:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4008000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [4010000000000000]
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4008000000000000]
+
+test_faddx_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fadd. f3, f4, f5
+  blr
+  #_ REGISTER_OUT f3 [0000000000000000]
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]

src/xenia/cpu/ppc/testing/instr_fcfidx.s

@@ -0,0 +1,27 @@
+test_fcfidx_1:
+  #_ REGISTER_IN f1 0x0000000000000001
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 1.0
+  #_ REGISTER_OUT f1 0x0000000000000001
+
+test_fcfidx_2:
+  #_ REGISTER_IN f1 0xFFFFFFFFFFFFFFFF
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 -1.0
+  #_ REGISTER_OUT f1 0xFFFFFFFFFFFFFFFF
+
+test_fcfidx_3:
+  #_ REGISTER_IN f1 0x0000000000000064
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 100.0
+  #_ REGISTER_OUT f1 0x0000000000000064
+
+test_fcfidx_4:
+  #_ REGISTER_IN f1 0x0000000000000000
+  fcfid. f3, f1
+  blr
+  #_ REGISTER_OUT f3 0.0
+  #_ REGISTER_OUT f1 0x0000000000000000

src/xenia/cpu/ppc/testing/instr_fcmpo.s

@@ -0,0 +1,39 @@
+test_fcmpo_1:
+  #_ REGISTER_IN f4 [3FF0000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [3FF0000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fcmpo_2:
+  #_ REGISTER_IN f4 [4000000000000000]
+  #_ REGISTER_IN f5 [4000000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [4000000000000000]
+  #_ REGISTER_OUT f5 [4000000000000000]
+
+test_fcmpo_3:
+  #_ REGISTER_IN f4 [4008000000000000]
+  #_ REGISTER_IN f5 [3FF0000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [4008000000000000]
+  #_ REGISTER_OUT f5 [3FF0000000000000]
+
+test_fcmpo_4:
+  #_ REGISTER_IN f4 [0000000000000000]
+  #_ REGISTER_IN f5 [0000000000000000]
+  fcmpo cr0, f4, f5
+  mfcr r3
+  blr
+  #_ REGISTER_OUT r3 0x20000000
+  #_ REGISTER_OUT f4 [0000000000000000]
+  #_ REGISTER_OUT f5 [0000000000000000]