[Vulkan] add no_discard_stencil_in_transfer_pipelines support

src/xenia/gpu/d3d12/d3d12_render_target_cache.cc

@@ -37,7 +37,6 @@ DEFINE_bool(
     "Allow stencil reference output usage on Direct3D 12 on Intel GPUs - not "
     "working on UHD Graphics 630 as of March 2021 (driver 27.20.0100.8336).",
     "GPU");
-DEFINE_bool(no_discard_stencil_in_transfer_pipelines, false, "bleh", "GPU");
 
 namespace xe {
 namespace gpu {

src/xenia/gpu/gpu_flags.cc

@@ -145,3 +145,8 @@ DEFINE_bool(submit_on_primary_buffer_end, true,
             "Submit the command buffer when a PM4 primary buffer ends if it's "
             "possible to submit immediately to try to reduce frame latency.",
             "GPU");
+
+DEFINE_bool(no_discard_stencil_in_transfer_pipelines, false,
+            "Skip stencil bit discard in render target transfer pipelines. "
+            "May improve performance on some GPUs.",
+            "GPU");

src/xenia/gpu/gpu_flags.h

@@ -48,6 +48,8 @@ bool IsGpuDebugMarkersEnabled();
 
 DECLARE_string(render_target_path);
 
+DECLARE_bool(no_discard_stencil_in_transfer_pipelines);
+
 #define XE_GPU_FINE_GRAINED_DRAW_SCOPES 1
 
 #endif  // XENIA_GPU_GPU_FLAGS_H_

src/xenia/gpu/vulkan/vulkan_render_target_cache.cc

@@ -4270,7 +4270,7 @@ VkShaderModule VulkanRenderTargetCache::GetTransferShader(
         }
       } break;
       case TransferOutput::kStencilBit: {
-        if (packed) {
+        if (packed && !cvars::no_discard_stencil_in_transfer_pipelines) {
           // Kill the sample if the needed stencil bit is not set.
           assert_true(push_constants_member_stencil_mask != UINT32_MAX);
           id_vector_temp.clear();