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Richard Henderson 4889d96660 Merge tag 'pull-10.2-maintainer-291025-1' of https://gitlab.com/stsquad/qemu into staging 
maintainer updates for 10.2

  - clean-up remaining 32 bit armhf bits in ci
  - rationalise build-environment.yml for Debian and Ubuntu
  - generate a Debian ppc64 package list
  - rationalise gitlab-runner.yml for Debian and Ubuntu
  - new TCG plugin feature to track discontinuities
  - add missing CFI annotation to plugin callbacks
  - drop SBSA_REF from minimal Arm build
  - format string fix for gdbstub syscall response
  - simplify the gdbstub flen handling for semihosting

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmkCInQACgkQ+9DbCVqe
# KkSZRwf/ReHIqQMxf8TqthskX8PLGUvsvWMkJptpu0Yc4HyU6DSjdPbU4L0tOmLU
# ss2sb+dZncp1iRxHpqOhPJ+a987RHHzFbz2GQ/nV37D7BTwtq0iID4SxmdfiYOAm
# VVm/WQ0HMjIYY84rzfE6U/3H+FgL+GaPbB0WYa5CtKpMOHMl4gJgoSsxljXQrmYe
# BCC+Z9loVUAnKVVM5BUMP/0Agfn0CUZlUHGEn6RvmNg81dJ5DWCfO9yW1EezLZmc
# PhS/txAWrpTqktPxN4h+um8ILvej5FF8nnNCsxodxD1XZImWsxawxcQAcgQQJGWu
# dFLBMre7QSM1ddIOgdyZt+zuDcpUiA==
# =QEqf
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 29 Oct 2025 03:19:32 PM CET
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-10.2-maintainer-291025-1' of https://gitlab.com/stsquad/qemu: (35 commits)
  semihosting: Fix GDB File-I/O FLEN
  gdbstub: Fix %s formatting
  configs: drop SBSA_REF from minimal specification
  plugins/core: add missing QEMU_DISABLE_CFI annotations
  tests: add test with interrupted memory accesses on rv64
  tests: add test for double-traps on rv64
  tests: add plugin asserting correctness of discon event's to_pc
  target/xtensa: call plugin trap callbacks
  target/tricore: call plugin trap callbacks
  target/sparc: call plugin trap callbacks
  target/sh4: call plugin trap callbacks
  target/s390x: call plugin trap callbacks
  target/rx: call plugin trap callbacks
  target/riscv: call plugin trap callbacks
  target/ppc: call plugin trap callbacks
  target/openrisc: call plugin trap callbacks
  target/mips: call plugin trap callbacks
  target/microblaze: call plugin trap callbacks
  target/m68k: call plugin trap callbacks
  target/loongarch: call plugin trap callbacks
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-10-30 09:25:15 +01:00
Julian GanzandAlex Bennée cd6ee56222 target/microblaze: call plugin trap callbacks 
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.

This change places the hook for MicroBlaze targets. This architecture
has one special "exception" for interrupts and no host calls.

Signed-off-by: Julian Ganz <neither@nut.email>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251027110344.2289945-19-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 2025-10-29 14:12:43 +00:00
Edgar E. Iglesias cfc1d54251 target/microblaze: Handle signed division overflows 
Handle signed division overflows as specified in UG984:
https://docs.amd.com/r/en-US/ug984-vivado-microblaze-ref/idiv

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 2025-10-29 13:37:44 +01:00
Edgar E. Iglesias 0e46b4d1f1 target/microblaze: div: Break out raise_divzero() 
Break out raise_divzero() and take the opportunity to rename
and reorder function args to better match with spec and
pseudo code.

No functional change.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2025-10-29 13:37:44 +01:00
Edgar E. Iglesias a04c5ba543 target/microblaze: Remove unused arg from check_divz() 
Remove unused arg from check_divz(). No functional change.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 2025-10-29 13:37:44 +01:00
Philippe Mathieu-Daudé 5dfe024f9e target/microblaze: Convert CPUMBState::res_addr field to uint32_t type 
CPUMBState::@res_addr field is used as u32 since commit
cfeea807e5 ("target-microblaze: Tighten up TCGv_i32 vs
TCGv type usage"). Convert it as such, bumping the migration
version. Use the RES_ADDR_NONE definition when appropriate.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-8-philmd@linaro.org>
 2025-10-16 17:07:27 +02:00
Philippe Mathieu-Daudé 2c12ba4d8b target/microblaze: Have do_load/store() take a TCGv_i32 address argument 
All callers of do_load() and do_store() pass a TCGv_i32 address
type, have both functions take a TCGv_i32.

Suggested-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-7-philmd@linaro.org>
 2025-10-16 17:07:27 +02:00
Philippe Mathieu-Daudé 1bf79694bc target/microblaze: Have compute_ldst_addr_type[ab] return TCGv_i32 
Both compute_ldst_addr_typea() and compute_ldst_addr_typeb()
bodies use a TCGv_i32, so return the same type.

Suggested-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-6-philmd@linaro.org>
 2025-10-16 17:07:27 +02:00
Philippe Mathieu-Daudé 92035b7b0d target/microblaze: Remove target_ulong use in helper_stackprot() 
Since commit 36a9529e60 ("target/microblaze: Simplify
compute_ldst_addr_type{a,b}"), helper_stackprot() takes
a TCGv_i32 argument.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-5-philmd@linaro.org>
 2025-10-16 17:07:27 +02:00
Philippe Mathieu-Daudé dc693a4a88 target/microblaze: Remove target_ulong use in gen_goto_tb() 
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4 ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-4-philmd@linaro.org>
 2025-10-16 17:07:27 +02:00
Philippe Mathieu-Daudé 0651ea17e8 target/microblaze: Remove target_ulong uses in get_phys_page_attrs_debug 
The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
and return a 'hwaddr' type since commit 00b941e581 ("cpu: Turn
cpu_get_phys_page_debug() into a CPUClass hook").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-3-philmd@linaro.org>
 2025-10-16 17:07:27 +02:00
Philippe Mathieu-Daudé 1f097e46a3 target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault() 
cpu_handle_mmu_fault() -- renamed in commit f429d607c7 -- expects
a vaddr type for its address argument since commit 7510454e3e
("cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook").

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251015180115.97493-2-philmd@linaro.org>
 2025-10-16 17:07:27 +02:00
Philippe Mathieu-Daudé 482869ca84 accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx 
tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
Declare the argument as unsigned and rename it as @tb_slot_idx
(which is more descriptive than @n) on all targets.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20251010031745.37528-1-philmd@linaro.org>
 2025-10-16 10:33:33 +02:00
Igor MammedovandPaolo Bonzini 87511341c3 add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 
The helpers form load-acquire/store-release pair and ensure
that appropriate barriers are in place in case checks happen
outside of BQL.

Use them to replace open-coded checkers/setters across the code,
to make sure that barriers are not missed.  Helpers also make code a
bit more readable.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Jason J. Herne <jjherne@linux.ibm.com>
Link: https://lore.kernel.org/r/20250821155603.2422553-1-imammedo@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
 2025-08-29 12:48:14 +02:00
Richard Henderson 981f2beb16 target: Use cpu_pointer_wrap_uint32 for 32-bit targets 
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are
all 32-bit targets.  AVR is more complicated, but using
a 32-bit wrap preserves current behaviour.

Cc: Michael Rolnik <mrolnik@gmail.com>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Stafford Horne <shorne@gmail.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore)
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:48 +01:00
Richard Henderson 36a9529e60 target/microblaze: Simplify compute_ldst_addr_type{a,b} 
Require TCGv_i32 and TCGv be identical, so drop
the extensions.  Return constants when possible
instead of a mov into a temporary.  Return register
inputs unchanged when possible.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson bd07403fc1 target/microblaze: Drop DisasContext.r0 
Return a constant 0 from reg_for_read, and a new
temporary from reg_for_write.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson 17ac97a958 target/microblaze: Fix printf format in mmu_translate 
Use TARGET_FMT_lx to match the target_ulong type of vaddr.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson 14c1d81354 target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea 
Use an explicit 64-bit type for extended addresses.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson 8cea8bd4d3 target/microblaze: Use uint64_t for CPUMBState.ear 
Use an explicit 64-bit type for EAR.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson beea772666 target/microblaze: Implement extended address load/store out of line 
Use helpers and address_space_ld/st instead of inline
loads and stores.  This allows us to perform operations
on physical addresses wider than virtual addresses.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson 526b0d364a target/microblaze: Split out mb_transaction_failed_internal 
Use an explicit 64-bit type for the address to store in EAR.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson 3f8d6b432d target/microblaze: Introduce helper_unaligned_access 
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Richard Henderson 67f2d507ca target/microblaze: Split out mb_unaligned_access_internal 
Use an explicit 64-bit type for the address to store in EAR.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 2025-05-28 08:08:47 +01:00
Peter Maydell 6222ae143d target/microblaze: Delay gdb_register_coprocessor() to realize 
Currently the microblaze code calls gdb_register_coprocessor() in its
initfn.  This works, but we would like to delay setting up GDB
registers until realize.  All other target architectures only call
gdb_register_coprocessor() in realize, after the call to
cpu_exec_realizefn().

Move the microblaze gdb_register_coprocessor() use, bringing it
in line with other targets.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250429132200.605611-3-peter.maydell@linaro.org
 2025-05-14 14:29:45 +01:00