Commit Graph
157 Commits
Author SHA1 Message Date
Igor MammedovandPhilippe Mathieu-Daudé 6c5571e72a rx: cpu: fix interrupts check in rx_cpu_do_interrupt()
Commit 87511341c3 broke interrupt handling, replacing interrupts
fetch with a bool and then the remaining code attempting to check
individual bits on that bool value, which effectively masked those
interrupts.

Fix it by checking individual interrupt bits directly instead of
old 'fetch then check' approach.

Fixes: 87511341c3 ("add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide")
Reported-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20251030165932.138512-1-imammedo@redhat.com>
[PMD: Rebased on commit dde21df239 "call plugin trap callbacks"]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-11-03 14:15:57 +01:00
Julian GanzandAlex Bennée dde21df239 target/rx: call plugin trap callbacks
We recently introduced API for registering callbacks for trap related
events as well as the corresponding hook functions. Due to differences
between architectures, the latter need to be called from target specific
code.

This change places hooks for Renesas Xtreme targets.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Yoshinori Sato <yoshinori.sato@nifty.com>
Signed-off-by: Julian Ganz <neither@nut.email>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251027110344.2289945-24-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2025-10-29 14:12:43 +00:00
Philippe Mathieu-Daudé bec018f122 target/rx: Un-inline various helpers
Rely on the linker to optimize at linking time.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009200012.33650-1-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé 86114e43ff target/rx: Expand TCG register definitions for 32-bit target
The RX target is only built as 32-bit:

  $ git grep TARGET_LONG_BITS configs/targets/rx-*
  configs/targets/rx-softmmu.mak:5:TARGET_LONG_BITS=32

Therefore target_ulong always expands to uint32_t.

Replace and adapt the API uses mechanically:

  TCGv -> TCGv_i32
  tcg_temp_new -> tcg_temp_new_i32

There is no functional change.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-9-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé f9903a8a23 target/rx: Replace MO_TE -> MO_LE
We only build the RX targets using little endianness order:

  $ git grep TARGET_BIG_ENDIAN configs/targets/rx-*
  $

Therefore the MO_TE definition always expands to MO_LE.
Use the latter to simplify.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-8-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé cb8e4556d5 target/rx: Factor mo_endian() helper out
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-7-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé 363fff6d1b target/rx: Propagate DisasContext to gen_ld[u]() and gen_st()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-6-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé 8b71fd6ffe target/rx: Propagate DisasContext to push() / pop()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-5-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé 2062fa663c target/rx: Propagate DisasContext to generated helpers
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-4-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé 0f4af4e267 target/rx: Use MemOp type in gen_ld[u]() and gen_st()
The @size argument is of MemOp type. All callers respect that.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-3-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé 2982b948a9 target/rx: Replace target_ulong -> vaddr for translator API uses
Since commit b1c09220b4 ("accel/tcg: Replace target_ulong with
vaddr in translator_*()") the API takes vaddr argument, not
target_ulong. Update the 2 callers.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251009151607.26278-2-philmd@linaro.org>
2025-10-16 17:07:52 +02:00
Philippe Mathieu-Daudé 482869ca84 accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
Declare the argument as unsigned and rename it as @tb_slot_idx
(which is more descriptive than @n) on all targets.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20251010031745.37528-1-philmd@linaro.org>
2025-10-16 10:33:33 +02:00
Paolo Bonzini 602d5ebba2 treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt()
Open coding cpu_reset_interrupt() can cause bugs if the BQL is not
taken, for example i386 has the call chain kvm_cpu_exec() ->
kvm_put_vcpu_events() -> kvm_arch_put_registers().

Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-09-17 19:00:55 +02:00
Igor MammedovandPaolo Bonzini 87511341c3 add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide
The helpers form load-acquire/store-release pair and ensure
that appropriate barriers are in place in case checks happen
outside of BQL.

Use them to replace open-coded checkers/setters across the code,
to make sure that barriers are not missed.  Helpers also make code a
bit more readable.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Jason J. Herne <jjherne@linux.ibm.com>
Link: https://lore.kernel.org/r/20250821155603.2422553-1-imammedo@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-08-29 12:48:14 +02:00
Richard Henderson 981f2beb16 target: Use cpu_pointer_wrap_uint32 for 32-bit targets
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are
all 32-bit targets.  AVR is more complicated, but using
a 32-bit wrap preserves current behaviour.

Cc: Michael Rolnik <mrolnik@gmail.com>
Cc: Laurent Vivier <laurent@vivier.eu>
Cc: Stafford Horne <shorne@gmail.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore)
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28 08:08:48 +01:00
Richard Henderson c37f8978d9 accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps
Move the global function name to a hook on TCGCPUOps.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson 4759aae432 accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state
Combine 3 different pointer returns into one structure return.

Include a cflags field in TCGTBCPUState, not filled in by
cpu_get_tb_cpu_state, but used by all callers.  This fills
a hole in the structure and is useful in some subroutines.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson a59a876999 accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.h
For some targets, simply remove the local definition.
For other targets, move the inline definition out of line.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Richard Henderson 9181ab4528 accel/tcg: Introduce TCGCPUOps.cpu_exec_reset
Initialize all instances with cpu_reset(), so that there
is no functional change.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30 12:45:05 -07:00
Philippe Mathieu-DaudéandRichard Henderson 84307cd602 include: Remove 'exec/exec-all.h'
"exec/exec-all.h" is now fully empty, let's remove it.

Mechanical change running:

  $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250424202412.91612-14-philmd@linaro.org>
2025-04-30 12:45:05 -07:00
Philippe Mathieu-Daudé 12d1a768bd qom: Have class_init() take a const data argument
Mechanical change using gsed, then style manually adapted
to pass checkpatch.pl script.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20250424194905.82506-4-philmd@linaro.org>
2025-04-25 17:00:41 +02:00
Philippe Mathieu-DaudéandRichard Henderson a3d40b5eff tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field
Instead of having a compile-time TARGET_SUPPORTS_MTTCG definition,
have each target set the 'mttcg_supported' field in the TCGCPUOps
structure.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250405161320.76854-17-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23 15:07:32 -07:00
Philippe Mathieu-DaudéandRichard Henderson 8201f1a29c tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally
By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23 15:07:32 -07:00
Philippe Mathieu-DaudéandRichard Henderson 04583ce7e0 tcg: Define guest_default_memory_order in TCGCPUOps
Add the TCGCPUOps::guest_default_memory_order field and have
each target initialize it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23 15:07:32 -07:00
Philippe Mathieu-DaudéandRichard Henderson c2ba9fea42 tcg: Always define TCG_GUEST_DEFAULT_MO
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.

In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23 15:07:32 -07:00