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tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally

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By directly using TCGCPUOps::guest_default_memory_order,
we don't need the TCG_GUEST_DEFAULT_MO definition anymore.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
2025-04-23 15:07:32 -07:00
committed by Richard Henderson
parent 0eca13c29a
commit 8201f1a29c
40 changed files with 66 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files
docs/devel/multi-thread-tcg.rst
+2 -2
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@@ -28,8 +28,8 @@ vCPU Scheduling
We introduce a new running mode where each vCPU will run on its own
user-space thread. This is enabled by default for all FE/BE
combinations where the host memory model is able to accommodate the
guest (TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO is zero) and the
guest has had the required work done to support this safely
guest (TCGCPUOps::guest_default_memory_order & ~TCG_TARGET_DEFAULT_MO is zero)
and the guest has had the required work done to support this safely
(TARGET_SUPPORTS_MTTCG).
System emulation will fall back to the original round robin approach
target/alpha/cpu-param.h
-3
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@@ -26,7 +26,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
/* Alpha processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#endif
target/alpha/cpu.c
+2 -1
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@@ -235,7 +235,8 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps alpha_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* Alpha processors have a weak memory model */
.guest_default_memory_order = 0,
.initialize = alpha_translate_init,
.translate_code = alpha_translate_code,
target/arm/cpu-param.h
-3
View File
@@ -44,7 +44,4 @@
*/
#define TARGET_INSN_START_EXTRA_WORDS 2
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#endif
target/arm/cpu.c
+2 -1
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@@ -2671,7 +2671,8 @@ static const struct SysemuCPUOps arm_sysemu_ops = {
#ifdef CONFIG_TCG
static const TCGCPUOps arm_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* ARM processors have a weak memory model */
.guest_default_memory_order = 0,
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
target/arm/tcg/cpu-v7m.c
+2 -1
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@@ -232,7 +232,8 @@ static void cortex_m55_initfn(Object *obj)
}
static const TCGCPUOps arm_v7m_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* ARM processors have a weak memory model */
.guest_default_memory_order = 0,
.initialize = arm_translate_init,
.translate_code = arm_translate_code,
target/avr/cpu-param.h
-2
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@@ -27,6 +27,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO 0
#endif
target/avr/cpu.c
+1 -1
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@@ -224,7 +224,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps avr_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = avr_cpu_tcg_init,
.translate_code = avr_cpu_translate_code,
.synchronize_from_tb = avr_cpu_synchronize_from_tb,
target/hexagon/cpu-param.h
-3
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@@ -25,7 +25,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
/* MTTCG not yet supported: require strict ordering */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif
target/hexagon/cpu.c
+2 -1
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@@ -325,7 +325,8 @@ static void hexagon_cpu_init(Object *obj)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hexagon_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = hexagon_translate_init,
.translate_code = hexagon_translate_code,
.synchronize_from_tb = hexagon_cpu_synchronize_from_tb,
target/hppa/cpu-param.h
-8
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@@ -21,12 +21,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 2
/* PA-RISC 1.x processors have a strong memory model. */
/*
* ??? While we do not yet implement PA-RISC 2.0, those processors have
* a weak memory model, but with TLB bits that force ordering on a per-page
* basis. It's probably easier to fall back to a strong memory model.
*/
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif
target/hppa/cpu.c
+7 -1
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@@ -253,7 +253,13 @@ static const struct SysemuCPUOps hppa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps hppa_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* PA-RISC 1.x processors have a strong memory model. */
/*
* ??? While we do not yet implement PA-RISC 2.0, those processors have
* a weak memory model, but with TLB bits that force ordering on a per-page
* basis. It's probably easier to fall back to a strong memory model.
*/
.guest_default_memory_order = TCG_MO_ALL,
.initialize = hppa_translate_init,
.translate_code = hppa_translate_code,
target/i386/cpu-param.h
-3
View File
@@ -24,7 +24,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/* The x86 has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
#endif
target/i386/tcg/tcg-cpu.c
+4 -1
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@@ -125,7 +125,10 @@ static bool x86_debug_check_breakpoint(CPUState *cs)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps x86_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/*
* The x86 has a strong memory model with some store-after-load re-ordering
*/
.guest_default_memory_order = TCG_MO_ALL & ~TCG_MO_ST_LD,
.initialize = tcg_x86_init,
.translate_code = x86_translate_code,
.synchronize_from_tb = x86_cpu_synchronize_from_tb,
target/loongarch/cpu-param.h
-2
View File
@@ -15,6 +15,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 0
#define TCG_GUEST_DEFAULT_MO (0)
#endif
target/loongarch/cpu.c
+1 -1
View File
@@ -864,7 +864,7 @@ static void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps loongarch_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
.guest_default_memory_order = 0,
.initialize = loongarch_translate_init,
.translate_code = loongarch_translate_code,
target/m68k/cpu-param.h
-3
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@@ -19,7 +19,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/* MTTCG not yet supported: require strict ordering */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif
target/m68k/cpu.c
+2 -1
View File
@@ -589,7 +589,8 @@ static const struct SysemuCPUOps m68k_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps m68k_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MTTCG not yet supported: require strict ordering */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = m68k_tcg_init,
.translate_code = m68k_translate_code,
target/microblaze/cpu-param.h
-3
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@@ -29,7 +29,4 @@
#define TARGET_INSN_START_EXTRA_WORDS 1
/* MicroBlaze is always in-order. */
#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
#endif
target/microblaze/cpu.c
+2 -1
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@@ -427,7 +427,8 @@ static const struct SysemuCPUOps mb_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps mb_tcg_ops = {
.guest_default_memory_order = TCG_GUEST_DEFAULT_MO,
/* MicroBlaze is always in-order. */
.guest_default_memory_order = TCG_MO_ALL,
.initialize = mb_tcg_init,
.translate_code = mb_translate_code,

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