mirror of
https://github.com/izzy2lost/xemu.git
synced 2026-07-06 00:20:22 -07:00
Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into staging
Convert TCG backend code generators to TCGOutOp structures, decomposing the monolithic tcg_out_op functions. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmgRDgcdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+0SQf9Ef8IE5QWjXEws706 # q+1deeDV2xa1sKAHG5fnskk1bXM31Cy4koNdDQbHTtDWedNEzWKyR7FxjlRm+zSW # 6CposaEEsCGxdKUbvraflGbWuf2NUZpJoreNGo9BYZkfNWE9yJ0HlypjpxclziRA # G0Ro4XMevi+yVA3cd8lEmft9cW+woFrVWu5I4tucMwY/8gzWRiHV4Z5YCeCEjD3C # 3YYukhRTaA+7Lyd1G3rcqh8uSsAGGv2NLO26upK1mnVtZOoS/CgKWfBq5enVEuDd # X6T544ipz8Z3eXFgzTzK4nl7TpmO+XEUbja3op7psrLHU84puX1/47HLk4TkHlE+ # 6/95eA== # =vzOx # -----END PGP SIGNATURE----- # gpg: Signature made Tue 29 Apr 2025 13:36:07 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu: (161 commits) tcg/sparc64: Implement CTPOP tcg/sparc64: Unexport use_vis3_instructions tcg: Remove tcg_out_op tcg: Convert qemu_st{2} to TCGOutOpLdSt{2} tcg: Convert qemu_ld{2} to TCGOutOpLoad{2} tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128} tcg: Remove INDEX_op_qemu_st8_* tcg: Stash MemOp size in TCGOP_FLAGS tcg: Merge INDEX_op_st*_{i32,i64} tcg: Convert st to TCGOutOpStore tcg: Merge INDEX_op_ld*_{i32,i64} tcg: Convert ld to TCGOutOpLoad tcg: Formalize tcg_out_goto_ptr tcg: Formalize tcg_out_br tcg: Formalize tcg_out_mb tcg: Remove add2/sub2 opcodes tcg/tci: Implement add/sub carry opcodes tcg/sparc64: Implement add/sub carry opcodes tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi
+141
-87
@@ -239,7 +239,7 @@ Jumps/Labels
|
||||
|
||||
- | Jump to label.
|
||||
|
||||
* - brcond_i32/i64 *t0*, *t1*, *cond*, *label*
|
||||
* - brcond *t0*, *t1*, *cond*, *label*
|
||||
|
||||
- | Conditional jump if *t0* *cond* *t1* is true. *cond* can be:
|
||||
|
|
||||
@@ -261,98 +261,117 @@ Arithmetic
|
||||
|
||||
.. list-table::
|
||||
|
||||
* - add_i32/i64 *t0*, *t1*, *t2*
|
||||
* - add *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* + *t2*
|
||||
|
||||
* - sub_i32/i64 *t0*, *t1*, *t2*
|
||||
* - sub *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* - *t2*
|
||||
|
||||
* - neg_i32/i64 *t0*, *t1*
|
||||
* - neg *t0*, *t1*
|
||||
|
||||
- | *t0* = -*t1* (two's complement)
|
||||
|
||||
* - mul_i32/i64 *t0*, *t1*, *t2*
|
||||
* - mul *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* * *t2*
|
||||
|
||||
* - div_i32/i64 *t0*, *t1*, *t2*
|
||||
* - divs *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* / *t2* (signed)
|
||||
| Undefined behavior if division by zero or overflow.
|
||||
|
||||
* - divu_i32/i64 *t0*, *t1*, *t2*
|
||||
* - divu *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* / *t2* (unsigned)
|
||||
| Undefined behavior if division by zero.
|
||||
|
||||
* - rem_i32/i64 *t0*, *t1*, *t2*
|
||||
* - rems *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* % *t2* (signed)
|
||||
| Undefined behavior if division by zero or overflow.
|
||||
|
||||
* - remu_i32/i64 *t0*, *t1*, *t2*
|
||||
* - remu *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* % *t2* (unsigned)
|
||||
| Undefined behavior if division by zero.
|
||||
|
||||
* - divs2 *q*, *r*, *nl*, *nh*, *d*
|
||||
|
||||
- | *q* = *nh:nl* / *d* (signed)
|
||||
| *r* = *nh:nl* % *d*
|
||||
| Undefined behaviour if division by zero, or the double-word
|
||||
numerator divided by the single-word divisor does not fit
|
||||
within the single-word quotient. The code generator will
|
||||
pass *nh* as a simple sign-extension of *nl*, so the only
|
||||
overflow should be *INT_MIN* / -1.
|
||||
|
||||
* - divu2 *q*, *r*, *nl*, *nh*, *d*
|
||||
|
||||
- | *q* = *nh:nl* / *d* (unsigned)
|
||||
| *r* = *nh:nl* % *d*
|
||||
| Undefined behaviour if division by zero, or the double-word
|
||||
numerator divided by the single-word divisor does not fit
|
||||
within the single-word quotient. The code generator will
|
||||
pass 0 to *nh* to make a simple zero-extension of *nl*,
|
||||
so overflow should never occur.
|
||||
|
||||
Logical
|
||||
-------
|
||||
|
||||
.. list-table::
|
||||
|
||||
* - and_i32/i64 *t0*, *t1*, *t2*
|
||||
* - and *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* & *t2*
|
||||
|
||||
* - or_i32/i64 *t0*, *t1*, *t2*
|
||||
* - or *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* | *t2*
|
||||
|
||||
* - xor_i32/i64 *t0*, *t1*, *t2*
|
||||
* - xor *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* ^ *t2*
|
||||
|
||||
* - not_i32/i64 *t0*, *t1*
|
||||
* - not *t0*, *t1*
|
||||
|
||||
- | *t0* = ~\ *t1*
|
||||
|
||||
* - andc_i32/i64 *t0*, *t1*, *t2*
|
||||
* - andc *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* & ~\ *t2*
|
||||
|
||||
* - eqv_i32/i64 *t0*, *t1*, *t2*
|
||||
* - eqv *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = ~(*t1* ^ *t2*), or equivalently, *t0* = *t1* ^ ~\ *t2*
|
||||
|
||||
* - nand_i32/i64 *t0*, *t1*, *t2*
|
||||
* - nand *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = ~(*t1* & *t2*)
|
||||
|
||||
* - nor_i32/i64 *t0*, *t1*, *t2*
|
||||
* - nor *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = ~(*t1* | *t2*)
|
||||
|
||||
* - orc_i32/i64 *t0*, *t1*, *t2*
|
||||
* - orc *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* | ~\ *t2*
|
||||
|
||||
* - clz_i32/i64 *t0*, *t1*, *t2*
|
||||
* - clz *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* ? clz(*t1*) : *t2*
|
||||
|
||||
* - ctz_i32/i64 *t0*, *t1*, *t2*
|
||||
* - ctz *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* ? ctz(*t1*) : *t2*
|
||||
|
||||
* - ctpop_i32/i64 *t0*, *t1*
|
||||
* - ctpop *t0*, *t1*
|
||||
|
||||
- | *t0* = number of bits set in *t1*
|
||||
|
|
||||
| With *ctpop* short for "count population", matching
|
||||
| the function name used in ``include/qemu/host-utils.h``.
|
||||
| The name *ctpop* is short for "count population", and matches
|
||||
the function name used in ``include/qemu/host-utils.h``.
|
||||
|
||||
|
||||
Shifts/Rotates
|
||||
@@ -360,30 +379,30 @@ Shifts/Rotates
|
||||
|
||||
.. list-table::
|
||||
|
||||
* - shl_i32/i64 *t0*, *t1*, *t2*
|
||||
* - shl *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* << *t2*
|
||||
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
|
||||
| Unspecified behavior for negative or out-of-range shifts.
|
||||
|
||||
* - shr_i32/i64 *t0*, *t1*, *t2*
|
||||
* - shr *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* >> *t2* (unsigned)
|
||||
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
|
||||
| Unspecified behavior for negative or out-of-range shifts.
|
||||
|
||||
* - sar_i32/i64 *t0*, *t1*, *t2*
|
||||
* - sar *t0*, *t1*, *t2*
|
||||
|
||||
- | *t0* = *t1* >> *t2* (signed)
|
||||
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
|
||||
| Unspecified behavior for negative or out-of-range shifts.
|
||||
|
||||
* - rotl_i32/i64 *t0*, *t1*, *t2*
|
||||
* - rotl *t0*, *t1*, *t2*
|
||||
|
||||
- | Rotation of *t2* bits to the left
|
||||
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
|
||||
| Unspecified behavior for negative or out-of-range shifts.
|
||||
|
||||
* - rotr_i32/i64 *t0*, *t1*, *t2*
|
||||
* - rotr *t0*, *t1*, *t2*
|
||||
|
||||
- | Rotation of *t2* bits to the right.
|
||||
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
|
||||
| Unspecified behavior for negative or out-of-range shifts.
|
||||
|
||||
|
||||
Misc
|
||||
@@ -391,26 +410,12 @@ Misc
|
||||
|
||||
.. list-table::
|
||||
|
||||
* - mov_i32/i64 *t0*, *t1*
|
||||
* - mov *t0*, *t1*
|
||||
|
||||
- | *t0* = *t1*
|
||||
| Move *t1* to *t0* (both operands must have the same type).
|
||||
| Move *t1* to *t0*.
|
||||
|
||||
* - ext8s_i32/i64 *t0*, *t1*
|
||||
|
||||
ext8u_i32/i64 *t0*, *t1*
|
||||
|
||||
ext16s_i32/i64 *t0*, *t1*
|
||||
|
||||
ext16u_i32/i64 *t0*, *t1*
|
||||
|
||||
ext32s_i64 *t0*, *t1*
|
||||
|
||||
ext32u_i64 *t0*, *t1*
|
||||
|
||||
- | 8, 16 or 32 bit sign/zero extension (both operands must have the same type)
|
||||
|
||||
* - bswap16_i32/i64 *t0*, *t1*, *flags*
|
||||
* - bswap16 *t0*, *t1*, *flags*
|
||||
|
||||
- | 16 bit byte swap on the low bits of a 32/64 bit input.
|
||||
|
|
||||
@@ -420,24 +425,24 @@ Misc
|
||||
|
|
||||
| If neither ``TCG_BSWAP_OZ`` nor ``TCG_BSWAP_OS`` are set, then the bits of *t0* above bit 15 may contain any value.
|
||||
|
||||
* - bswap32_i64 *t0*, *t1*, *flags*
|
||||
* - bswap32 *t0*, *t1*, *flags*
|
||||
|
||||
- | 32 bit byte swap on a 64-bit value. The flags are the same as for bswap16,
|
||||
except they apply from bit 31 instead of bit 15.
|
||||
- | 32 bit byte swap. The flags are the same as for bswap16, except
|
||||
they apply from bit 31 instead of bit 15. On TCG_TYPE_I32, the
|
||||
flags should be zero.
|
||||
|
||||
* - bswap32_i32 *t0*, *t1*, *flags*
|
||||
* - bswap64 *t0*, *t1*, *flags*
|
||||
|
||||
bswap64_i64 *t0*, *t1*, *flags*
|
||||
|
||||
- | 32/64 bit byte swap. The flags are ignored, but still present
|
||||
for consistency with the other bswap opcodes.
|
||||
- | 64 bit byte swap. The flags are ignored, but still present
|
||||
for consistency with the other bswap opcodes. For future
|
||||
compatibility, the flags should be zero.
|
||||
|
||||
* - discard_i32/i64 *t0*
|
||||
|
||||
- | Indicate that the value of *t0* won't be used later. It is useful to
|
||||
force dead code elimination.
|
||||
|
||||
* - deposit_i32/i64 *dest*, *t1*, *t2*, *pos*, *len*
|
||||
* - deposit *dest*, *t1*, *t2*, *pos*, *len*
|
||||
|
||||
- | Deposit *t2* as a bitfield into *t1*, placing the result in *dest*.
|
||||
|
|
||||
@@ -446,14 +451,16 @@ Misc
|
||||
| *len* - the length of the bitfield
|
||||
| *pos* - the position of the first bit, counting from the LSB
|
||||
|
|
||||
| For example, "deposit_i32 dest, t1, t2, 8, 4" indicates a 4-bit field
|
||||
| For example, "deposit dest, t1, t2, 8, 4" indicates a 4-bit field
|
||||
at bit 8. This operation would be equivalent to
|
||||
|
|
||||
| *dest* = (*t1* & ~0x0f00) | ((*t2* << 8) & 0x0f00)
|
||||
|
|
||||
| on TCG_TYPE_I32.
|
||||
|
||||
* - extract_i32/i64 *dest*, *t1*, *pos*, *len*
|
||||
* - extract *dest*, *t1*, *pos*, *len*
|
||||
|
||||
sextract_i32/i64 *dest*, *t1*, *pos*, *len*
|
||||
sextract *dest*, *t1*, *pos*, *len*
|
||||
|
||||
- | Extract a bitfield from *t1*, placing the result in *dest*.
|
||||
|
|
||||
@@ -462,16 +469,16 @@ Misc
|
||||
to the left with zeros; for sextract_*, the result will be extended
|
||||
to the left with copies of the bitfield sign bit at *pos* + *len* - 1.
|
||||
|
|
||||
| For example, "sextract_i32 dest, t1, 8, 4" indicates a 4-bit field
|
||||
| For example, "sextract dest, t1, 8, 4" indicates a 4-bit field
|
||||
at bit 8. This operation would be equivalent to
|
||||
|
|
||||
| *dest* = (*t1* << 20) >> 28
|
||||
|
|
||||
| (using an arithmetic right shift).
|
||||
| (using an arithmetic right shift) on TCG_TYPE_I32.
|
||||
|
||||
* - extract2_i32/i64 *dest*, *t1*, *t2*, *pos*
|
||||
* - extract2 *dest*, *t1*, *t2*, *pos*
|
||||
|
||||
- | For N = {32,64}, extract an N-bit quantity from the concatenation
|
||||
- | For TCG_TYPE_I{N}, extract an N-bit quantity from the concatenation
|
||||
of *t2*:*t1*, beginning at *pos*. The tcg_gen_extract2_{i32,i64} expander
|
||||
accepts 0 <= *pos* <= N as inputs. The backend code generator will
|
||||
not see either 0 or N as inputs for these opcodes.
|
||||
@@ -494,19 +501,19 @@ Conditional moves
|
||||
|
||||
.. list-table::
|
||||
|
||||
* - setcond_i32/i64 *dest*, *t1*, *t2*, *cond*
|
||||
* - setcond *dest*, *t1*, *t2*, *cond*
|
||||
|
||||
- | *dest* = (*t1* *cond* *t2*)
|
||||
|
|
||||
| Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
|
||||
|
||||
* - negsetcond_i32/i64 *dest*, *t1*, *t2*, *cond*
|
||||
* - negsetcond *dest*, *t1*, *t2*, *cond*
|
||||
|
||||
- | *dest* = -(*t1* *cond* *t2*)
|
||||
|
|
||||
| Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0.
|
||||
|
||||
* - movcond_i32/i64 *dest*, *c1*, *c2*, *v1*, *v2*, *cond*
|
||||
* - movcond *dest*, *c1*, *c2*, *v1*, *v2*, *cond*
|
||||
|
||||
- | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*)
|
||||
|
|
||||
@@ -586,26 +593,79 @@ Multiword arithmetic support
|
||||
|
||||
.. list-table::
|
||||
|
||||
* - add2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high*
|
||||
* - addco *t0*, *t1*, *t2*
|
||||
|
||||
sub2_i32/i64 *t0_low*, *t0_high*, *t1_low*, *t1_high*, *t2_low*, *t2_high*
|
||||
- | Compute *t0* = *t1* + *t2* and in addition output to the
|
||||
carry bit provided by the host architecture.
|
||||
|
||||
- | Similar to add/sub, except that the double-word inputs *t1* and *t2* are
|
||||
formed from two single-word arguments, and the double-word output *t0*
|
||||
is returned in two single-word outputs.
|
||||
* - addci *t0, *t1*, *t2*
|
||||
|
||||
* - mulu2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
|
||||
- | Compute *t0* = *t1* + *t2* + *C*, where *C* is the
|
||||
input carry bit provided by the host architecture.
|
||||
The output carry bit need not be computed.
|
||||
|
||||
* - addcio *t0, *t1*, *t2*
|
||||
|
||||
- | Compute *t0* = *t1* + *t2* + *C*, where *C* is the
|
||||
input carry bit provided by the host architecture,
|
||||
and also compute the output carry bit.
|
||||
|
||||
* - addc1o *t0, *t1*, *t2*
|
||||
|
||||
- | Compute *t0* = *t1* + *t2* + 1, and in addition output to the
|
||||
carry bit provided by the host architecture. This is akin to
|
||||
*addcio* with a fixed carry-in value of 1.
|
||||
| This is intended to be used by the optimization pass,
|
||||
intermediate to complete folding of the addition chain.
|
||||
In some cases complete folding is not possible and this
|
||||
opcode will remain until output. If this happens, the
|
||||
code generator will use ``tcg_out_set_carry`` and then
|
||||
the output routine for *addcio*.
|
||||
|
||||
* - subbo *t0*, *t1*, *t2*
|
||||
|
||||
- | Compute *t0* = *t1* - *t2* and in addition output to the
|
||||
borrow bit provided by the host architecture.
|
||||
| Depending on the host architecture, the carry bit may or may not be
|
||||
identical to the borrow bit. Thus the addc\* and subb\*
|
||||
opcodes must not be mixed.
|
||||
|
||||
* - subbi *t0, *t1*, *t2*
|
||||
|
||||
- | Compute *t0* = *t1* - *t2* - *B*, where *B* is the
|
||||
input borrow bit provided by the host architecture.
|
||||
The output borrow bit need not be computed.
|
||||
|
||||
* - subbio *t0, *t1*, *t2*
|
||||
|
||||
- | Compute *t0* = *t1* - *t2* - *B*, where *B* is the
|
||||
input borrow bit provided by the host architecture,
|
||||
and also compute the output borrow bit.
|
||||
|
||||
* - subb1o *t0, *t1*, *t2*
|
||||
|
||||
- | Compute *t0* = *t1* - *t2* - 1, and in addition output to the
|
||||
borrow bit provided by the host architecture. This is akin to
|
||||
*subbio* with a fixed borrow-in value of 1.
|
||||
| This is intended to be used by the optimization pass,
|
||||
intermediate to complete folding of the subtraction chain.
|
||||
In some cases complete folding is not possible and this
|
||||
opcode will remain until output. If this happens, the
|
||||
code generator will use ``tcg_out_set_borrow`` and then
|
||||
the output routine for *subbio*.
|
||||
|
||||
* - mulu2 *t0_low*, *t0_high*, *t1*, *t2*
|
||||
|
||||
- | Similar to mul, except two unsigned inputs *t1* and *t2* yielding the full
|
||||
double-word product *t0*. The latter is returned in two single-word outputs.
|
||||
|
||||
* - muls2_i32/i64 *t0_low*, *t0_high*, *t1*, *t2*
|
||||
* - muls2 *t0_low*, *t0_high*, *t1*, *t2*
|
||||
|
||||
- | Similar to mulu2, except the two inputs *t1* and *t2* are signed.
|
||||
|
||||
* - mulsh_i32/i64 *t0*, *t1*, *t2*
|
||||
* - mulsh *t0*, *t1*, *t2*
|
||||
|
||||
muluh_i32/i64 *t0*, *t1*, *t2*
|
||||
muluh *t0*, *t1*, *t2*
|
||||
|
||||
- | Provide the high part of a signed or unsigned multiply, respectively.
|
||||
|
|
||||
@@ -684,8 +744,6 @@ QEMU specific operations
|
||||
|
||||
qemu_st_i32/i64/i128 *t0*, *t1*, *flags*, *memidx*
|
||||
|
||||
qemu_st8_i32 *t0*, *t1*, *flags*, *memidx*
|
||||
|
||||
- | Load data at the guest address *t1* into *t0*, or store data in *t0* at guest
|
||||
address *t1*. The _i32/_i64/_i128 size applies to the size of the input/output
|
||||
register *t0* only. The address *t1* is always sized according to the guest,
|
||||
@@ -703,10 +761,6 @@ QEMU specific operations
|
||||
64-bit memory access specified in *flags*.
|
||||
|
|
||||
| For qemu_ld/st_i128, these are only supported for a 64-bit host.
|
||||
|
|
||||
| For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of
|
||||
the memory operation is known to be 8-bit. This allows the backend to
|
||||
provide a different set of register constraints.
|
||||
|
||||
|
||||
Host vector operations
|
||||
@@ -884,9 +938,9 @@ Assumptions
|
||||
The target word size (``TCG_TARGET_REG_BITS``) is expected to be 32 bit or
|
||||
64 bit. It is expected that the pointer has the same size as the word.
|
||||
|
||||
On a 32 bit target, all 64 bit operations are converted to 32 bits. A
|
||||
few specific operations must be implemented to allow it (see add2_i32,
|
||||
sub2_i32, brcond2_i32).
|
||||
On a 32 bit target, all 64 bit operations are converted to 32 bits.
|
||||
A few specific operations must be implemented to allow it
|
||||
(see brcond2_i32, setcond2_i32).
|
||||
|
||||
On a 64 bit target, the values are transferred between 32 and 64-bit
|
||||
registers using the following ops:
|
||||
|
||||
@@ -135,6 +135,8 @@ void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
|
||||
TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
|
||||
void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
|
||||
TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
|
||||
void tcg_gen_addcio_i32(TCGv_i32 r, TCGv_i32 co,
|
||||
TCGv_i32 a, TCGv_i32 b, TCGv_i32 ci);
|
||||
void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
|
||||
void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
|
||||
void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
|
||||
@@ -238,6 +240,8 @@ void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
|
||||
TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
|
||||
void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
|
||||
TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
|
||||
void tcg_gen_addcio_i64(TCGv_i64 r, TCGv_i64 co,
|
||||
TCGv_i64 a, TCGv_i64 b, TCGv_i64 ci);
|
||||
void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
|
||||
void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
|
||||
void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
|
||||
|
||||
@@ -253,6 +253,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
|
||||
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
|
||||
#define tcg_gen_add2_tl tcg_gen_add2_i64
|
||||
#define tcg_gen_sub2_tl tcg_gen_sub2_i64
|
||||
#define tcg_gen_addcio_tl tcg_gen_addcio_i64
|
||||
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
|
||||
#define tcg_gen_muls2_tl tcg_gen_muls2_i64
|
||||
#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
|
||||
@@ -371,6 +372,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
|
||||
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
|
||||
#define tcg_gen_add2_tl tcg_gen_add2_i32
|
||||
#define tcg_gen_sub2_tl tcg_gen_sub2_i32
|
||||
#define tcg_gen_addcio_tl tcg_gen_addcio_i32
|
||||
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
|
||||
#define tcg_gen_muls2_tl tcg_gen_muls2_i32
|
||||
#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
|
||||
|
||||
+68
-144
@@ -34,148 +34,84 @@ DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
|
||||
DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
|
||||
|
||||
DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
|
||||
DEF(brcond, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | TCG_OPF_INT)
|
||||
|
||||
DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
|
||||
|
||||
DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
|
||||
DEF(setcond_i32, 1, 2, 1, 0)
|
||||
DEF(negsetcond_i32, 1, 2, 1, 0)
|
||||
DEF(movcond_i32, 1, 4, 1, 0)
|
||||
/* load/store */
|
||||
DEF(ld8u_i32, 1, 1, 1, 0)
|
||||
DEF(ld8s_i32, 1, 1, 1, 0)
|
||||
DEF(ld16u_i32, 1, 1, 1, 0)
|
||||
DEF(ld16s_i32, 1, 1, 1, 0)
|
||||
DEF(ld_i32, 1, 1, 1, 0)
|
||||
DEF(st8_i32, 0, 2, 1, 0)
|
||||
DEF(st16_i32, 0, 2, 1, 0)
|
||||
DEF(st_i32, 0, 2, 1, 0)
|
||||
/* arith */
|
||||
DEF(add_i32, 1, 2, 0, 0)
|
||||
DEF(sub_i32, 1, 2, 0, 0)
|
||||
DEF(mul_i32, 1, 2, 0, 0)
|
||||
DEF(div_i32, 1, 2, 0, 0)
|
||||
DEF(divu_i32, 1, 2, 0, 0)
|
||||
DEF(rem_i32, 1, 2, 0, 0)
|
||||
DEF(remu_i32, 1, 2, 0, 0)
|
||||
DEF(div2_i32, 2, 3, 0, 0)
|
||||
DEF(divu2_i32, 2, 3, 0, 0)
|
||||
DEF(and_i32, 1, 2, 0, 0)
|
||||
DEF(or_i32, 1, 2, 0, 0)
|
||||
DEF(xor_i32, 1, 2, 0, 0)
|
||||
/* shifts/rotates */
|
||||
DEF(shl_i32, 1, 2, 0, 0)
|
||||
DEF(shr_i32, 1, 2, 0, 0)
|
||||
DEF(sar_i32, 1, 2, 0, 0)
|
||||
DEF(rotl_i32, 1, 2, 0, 0)
|
||||
DEF(rotr_i32, 1, 2, 0, 0)
|
||||
DEF(deposit_i32, 1, 2, 2, 0)
|
||||
DEF(extract_i32, 1, 1, 2, 0)
|
||||
DEF(sextract_i32, 1, 1, 2, 0)
|
||||
DEF(extract2_i32, 1, 2, 1, 0)
|
||||
DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT)
|
||||
|
||||
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
|
||||
DEF(add, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(and, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(andc, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(bswap64, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(clz, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(ctpop, 1, 1, 0, TCG_OPF_INT)
|
||||
DEF(ctz, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(deposit, 1, 2, 2, TCG_OPF_INT)
|
||||
DEF(divs, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(divs2, 2, 3, 0, TCG_OPF_INT)
|
||||
DEF(divu, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(divu2, 2, 3, 0, TCG_OPF_INT)
|
||||
DEF(eqv, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(extract, 1, 1, 2, TCG_OPF_INT)
|
||||
DEF(extract2, 1, 2, 1, TCG_OPF_INT)
|
||||
DEF(ld8u, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(ld8s, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(ld16u, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(ld16s, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(ld32u, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(ld32s, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(ld, 1, 1, 1, TCG_OPF_INT)
|
||||
DEF(movcond, 1, 4, 1, TCG_OPF_INT)
|
||||
DEF(mul, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(muls2, 2, 2, 0, TCG_OPF_INT)
|
||||
DEF(mulsh, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(mulu2, 2, 2, 0, TCG_OPF_INT)
|
||||
DEF(muluh, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(nand, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(neg, 1, 1, 0, TCG_OPF_INT)
|
||||
DEF(negsetcond, 1, 2, 1, TCG_OPF_INT)
|
||||
DEF(nor, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(not, 1, 1, 0, TCG_OPF_INT)
|
||||
DEF(or, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(orc, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(rems, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(remu, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(rotl, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(rotr, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(sar, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(setcond, 1, 2, 1, TCG_OPF_INT)
|
||||
DEF(sextract, 1, 1, 2, TCG_OPF_INT)
|
||||
DEF(shl, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(shr, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(st8, 0, 2, 1, TCG_OPF_INT)
|
||||
DEF(st16, 0, 2, 1, TCG_OPF_INT)
|
||||
DEF(st32, 0, 2, 1, TCG_OPF_INT)
|
||||
DEF(st, 0, 2, 1, TCG_OPF_INT)
|
||||
DEF(sub, 1, 2, 0, TCG_OPF_INT)
|
||||
DEF(xor, 1, 2, 0, TCG_OPF_INT)
|
||||
|
||||
DEF(addco, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT)
|
||||
DEF(addc1o, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT)
|
||||
DEF(addci, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN)
|
||||
DEF(addcio, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN | TCG_OPF_CARRY_OUT)
|
||||
|
||||
DEF(subbo, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT)
|
||||
DEF(subb1o, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_OUT)
|
||||
DEF(subbi, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN)
|
||||
DEF(subbio, 1, 2, 0, TCG_OPF_INT | TCG_OPF_CARRY_IN | TCG_OPF_CARRY_OUT)
|
||||
|
||||
DEF(add2_i32, 2, 4, 0, 0)
|
||||
DEF(sub2_i32, 2, 4, 0, 0)
|
||||
DEF(mulu2_i32, 2, 2, 0, 0)
|
||||
DEF(muls2_i32, 2, 2, 0, 0)
|
||||
DEF(muluh_i32, 1, 2, 0, 0)
|
||||
DEF(mulsh_i32, 1, 2, 0, 0)
|
||||
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
|
||||
DEF(setcond2_i32, 1, 4, 1, 0)
|
||||
|
||||
DEF(ext8s_i32, 1, 1, 0, 0)
|
||||
DEF(ext16s_i32, 1, 1, 0, 0)
|
||||
DEF(ext8u_i32, 1, 1, 0, 0)
|
||||
DEF(ext16u_i32, 1, 1, 0, 0)
|
||||
DEF(bswap16_i32, 1, 1, 1, 0)
|
||||
DEF(bswap32_i32, 1, 1, 1, 0)
|
||||
DEF(not_i32, 1, 1, 0, 0)
|
||||
DEF(neg_i32, 1, 1, 0, 0)
|
||||
DEF(andc_i32, 1, 2, 0, 0)
|
||||
DEF(orc_i32, 1, 2, 0, 0)
|
||||
DEF(eqv_i32, 1, 2, 0, 0)
|
||||
DEF(nand_i32, 1, 2, 0, 0)
|
||||
DEF(nor_i32, 1, 2, 0, 0)
|
||||
DEF(clz_i32, 1, 2, 0, 0)
|
||||
DEF(ctz_i32, 1, 2, 0, 0)
|
||||
DEF(ctpop_i32, 1, 1, 0, 0)
|
||||
|
||||
DEF(mov_i64, 1, 1, 0, TCG_OPF_NOT_PRESENT)
|
||||
DEF(setcond_i64, 1, 2, 1, 0)
|
||||
DEF(negsetcond_i64, 1, 2, 1, 0)
|
||||
DEF(movcond_i64, 1, 4, 1, 0)
|
||||
/* load/store */
|
||||
DEF(ld8u_i64, 1, 1, 1, 0)
|
||||
DEF(ld8s_i64, 1, 1, 1, 0)
|
||||
DEF(ld16u_i64, 1, 1, 1, 0)
|
||||
DEF(ld16s_i64, 1, 1, 1, 0)
|
||||
DEF(ld32u_i64, 1, 1, 1, 0)
|
||||
DEF(ld32s_i64, 1, 1, 1, 0)
|
||||
DEF(ld_i64, 1, 1, 1, 0)
|
||||
DEF(st8_i64, 0, 2, 1, 0)
|
||||
DEF(st16_i64, 0, 2, 1, 0)
|
||||
DEF(st32_i64, 0, 2, 1, 0)
|
||||
DEF(st_i64, 0, 2, 1, 0)
|
||||
/* arith */
|
||||
DEF(add_i64, 1, 2, 0, 0)
|
||||
DEF(sub_i64, 1, 2, 0, 0)
|
||||
DEF(mul_i64, 1, 2, 0, 0)
|
||||
DEF(div_i64, 1, 2, 0, 0)
|
||||
DEF(divu_i64, 1, 2, 0, 0)
|
||||
DEF(rem_i64, 1, 2, 0, 0)
|
||||
DEF(remu_i64, 1, 2, 0, 0)
|
||||
DEF(div2_i64, 2, 3, 0, 0)
|
||||
DEF(divu2_i64, 2, 3, 0, 0)
|
||||
DEF(and_i64, 1, 2, 0, 0)
|
||||
DEF(or_i64, 1, 2, 0, 0)
|
||||
DEF(xor_i64, 1, 2, 0, 0)
|
||||
/* shifts/rotates */
|
||||
DEF(shl_i64, 1, 2, 0, 0)
|
||||
DEF(shr_i64, 1, 2, 0, 0)
|
||||
DEF(sar_i64, 1, 2, 0, 0)
|
||||
DEF(rotl_i64, 1, 2, 0, 0)
|
||||
DEF(rotr_i64, 1, 2, 0, 0)
|
||||
DEF(deposit_i64, 1, 2, 2, 0)
|
||||
DEF(extract_i64, 1, 1, 2, 0)
|
||||
DEF(sextract_i64, 1, 1, 2, 0)
|
||||
DEF(extract2_i64, 1, 2, 1, 0)
|
||||
|
||||
/* size changing ops */
|
||||
DEF(ext_i32_i64, 1, 1, 0, 0)
|
||||
DEF(extu_i32_i64, 1, 1, 0, 0)
|
||||
DEF(extrl_i64_i32, 1, 1, 0, 0)
|
||||
DEF(extrh_i64_i32, 1, 1, 0, 0)
|
||||
|
||||
DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH)
|
||||
DEF(ext8s_i64, 1, 1, 0, 0)
|
||||
DEF(ext16s_i64, 1, 1, 0, 0)
|
||||
DEF(ext32s_i64, 1, 1, 0, 0)
|
||||
DEF(ext8u_i64, 1, 1, 0, 0)
|
||||
DEF(ext16u_i64, 1, 1, 0, 0)
|
||||
DEF(ext32u_i64, 1, 1, 0, 0)
|
||||
DEF(bswap16_i64, 1, 1, 1, 0)
|
||||
DEF(bswap32_i64, 1, 1, 1, 0)
|
||||
DEF(bswap64_i64, 1, 1, 1, 0)
|
||||
DEF(not_i64, 1, 1, 0, 0)
|
||||
DEF(neg_i64, 1, 1, 0, 0)
|
||||
DEF(andc_i64, 1, 2, 0, 0)
|
||||
DEF(orc_i64, 1, 2, 0, 0)
|
||||
DEF(eqv_i64, 1, 2, 0, 0)
|
||||
DEF(nand_i64, 1, 2, 0, 0)
|
||||
DEF(nor_i64, 1, 2, 0, 0)
|
||||
DEF(clz_i64, 1, 2, 0, 0)
|
||||
DEF(ctz_i64, 1, 2, 0, 0)
|
||||
DEF(ctpop_i64, 1, 1, 0, 0)
|
||||
|
||||
DEF(add2_i64, 2, 4, 0, 0)
|
||||
DEF(sub2_i64, 2, 4, 0, 0)
|
||||
DEF(mulu2_i64, 2, 2, 0, 0)
|
||||
DEF(muls2_i64, 2, 2, 0, 0)
|
||||
DEF(muluh_i64, 1, 2, 0, 0)
|
||||
DEF(mulsh_i64, 1, 2, 0, 0)
|
||||
|
||||
#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
|
||||
|
||||
/* There are tcg_ctx->insn_start_words here, not just one. */
|
||||
@@ -188,22 +124,10 @@ DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
|
||||
DEF(plugin_cb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
|
||||
DEF(plugin_mem_cb, 0, 1, 1, TCG_OPF_NOT_PRESENT)
|
||||
|
||||
DEF(qemu_ld_i32, 1, 1, 1,
|
||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st_i32, 0, 1 + 1, 1,
|
||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld_i64, DATA64_ARGS, 1, 1,
|
||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st_i64, 0, DATA64_ARGS + 1, 1,
|
||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
|
||||
/* Only used by i386 to cope with stupid register constraints. */
|
||||
DEF(qemu_st8_i32, 0, 1 + 1, 1,
|
||||
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
|
||||
/* Only for 64-bit hosts at the moment. */
|
||||
DEF(qemu_ld_i128, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_st_i128, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
|
||||
DEF(qemu_ld, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_INT)
|
||||
DEF(qemu_st, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_INT)
|
||||
DEF(qemu_ld2, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_INT)
|
||||
DEF(qemu_st2, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_INT)
|
||||
|
||||
/* Host vector support. */
|
||||
|
||||
|
||||
+13
-2
@@ -418,6 +418,11 @@ struct TCGContext {
|
||||
MemOp riscv_cur_vsew;
|
||||
TCGType riscv_cur_type;
|
||||
#endif
|
||||
/*
|
||||
* During the tcg_reg_alloc_op loop, we are within a sequence of
|
||||
* carry-using opcodes like addco+addci.
|
||||
*/
|
||||
bool carry_live;
|
||||
|
||||
GHashTable *const_table[TCG_TYPE_COUNT];
|
||||
TCGTempSet free_temps[TCG_TYPE_COUNT];
|
||||
@@ -741,19 +746,25 @@ enum {
|
||||
/* Instruction has side effects: it cannot be removed if its outputs
|
||||
are not used, and might trigger exceptions. */
|
||||
TCG_OPF_SIDE_EFFECTS = 0x08,
|
||||
/* Instruction operands may be I32 or I64 */
|
||||
TCG_OPF_INT = 0x10,
|
||||
/* Instruction is optional and not implemented by the host, or insn
|
||||
is generic and should not be implemented by the host. */
|
||||
TCG_OPF_NOT_PRESENT = 0x20,
|
||||
/* Instruction operands are vectors. */
|
||||
TCG_OPF_VECTOR = 0x40,
|
||||
/* Instruction is a conditional branch. */
|
||||
TCG_OPF_COND_BRANCH = 0x80
|
||||
TCG_OPF_COND_BRANCH = 0x80,
|
||||
/* Instruction produces carry out. */
|
||||
TCG_OPF_CARRY_OUT = 0x100,
|
||||
/* Instruction consumes carry in. */
|
||||
TCG_OPF_CARRY_IN = 0x200,
|
||||
};
|
||||
|
||||
typedef struct TCGOpDef {
|
||||
const char *name;
|
||||
uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
|
||||
uint8_t flags;
|
||||
uint16_t flags;
|
||||
} TCGOpDef;
|
||||
|
||||
extern const TCGOpDef tcg_op_defs[];
|
||||
|
||||
@@ -1076,11 +1076,9 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
|
||||
TCGv_i64 cf_64 = tcg_temp_new_i64();
|
||||
TCGv_i64 vf_64 = tcg_temp_new_i64();
|
||||
TCGv_i64 tmp = tcg_temp_new_i64();
|
||||
TCGv_i64 zero = tcg_constant_i64(0);
|
||||
|
||||
tcg_gen_extu_i32_i64(cf_64, cpu_CF);
|
||||
tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
|
||||
tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
|
||||
tcg_gen_addcio_i64(result, cf_64, t0, t1, cf_64);
|
||||
tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
|
||||
gen_set_NZ64(result);
|
||||
|
||||
@@ -1094,12 +1092,10 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
|
||||
TCGv_i32 t0_32 = tcg_temp_new_i32();
|
||||
TCGv_i32 t1_32 = tcg_temp_new_i32();
|
||||
TCGv_i32 tmp = tcg_temp_new_i32();
|
||||
TCGv_i32 zero = tcg_constant_i32(0);
|
||||
|
||||
tcg_gen_extrl_i64_i32(t0_32, t0);
|
||||
tcg_gen_extrl_i64_i32(t1_32, t1);
|
||||
tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
|
||||
tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
|
||||
tcg_gen_addcio_i32(cpu_NF, cpu_CF, t0_32, t1_32, cpu_CF);
|
||||
|
||||
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
|
||||
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
|
||||
@@ -8600,7 +8596,7 @@ static bool trans_CCMP(DisasContext *s, arg_CCMP *a)
|
||||
tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
|
||||
|
||||
nzcv = a->nzcv;
|
||||
has_andc = tcg_op_supported(INDEX_op_andc_i32, TCG_TYPE_I32, 0);
|
||||
has_andc = tcg_op_supported(INDEX_op_andc, TCG_TYPE_I32, 0);
|
||||
if (nzcv & 8) { /* N */
|
||||
tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
|
||||
} else {
|
||||
|
||||
@@ -629,7 +629,7 @@ static void gen_bsl2n_i64(TCGv_i64 d, TCGv_i64 n, TCGv_i64 m, TCGv_i64 k)
|
||||
* = | ~(m | k)
|
||||
*/
|
||||
tcg_gen_and_i64(n, n, k);
|
||||
if (tcg_op_supported(INDEX_op_orc_i64, TCG_TYPE_I64, 0)) {
|
||||
if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I64, 0)) {
|
||||
tcg_gen_or_i64(m, m, k);
|
||||
tcg_gen_orc_i64(d, n, m);
|
||||
} else {
|
||||
|
||||
@@ -494,20 +494,9 @@ static void gen_add_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
|
||||
static void gen_adc_CC(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
|
||||
{
|
||||
TCGv_i32 tmp = tcg_temp_new_i32();
|
||||
if (tcg_op_supported(INDEX_op_add2_i32, TCG_TYPE_I32, 0)) {
|
||||
tcg_gen_movi_i32(tmp, 0);
|
||||
tcg_gen_add2_i32(cpu_NF, cpu_CF, t0, tmp, cpu_CF, tmp);
|
||||
tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1, tmp);
|
||||
} else {
|
||||
TCGv_i64 q0 = tcg_temp_new_i64();
|
||||
TCGv_i64 q1 = tcg_temp_new_i64();
|
||||
tcg_gen_extu_i32_i64(q0, t0);
|
||||
tcg_gen_extu_i32_i64(q1, t1);
|
||||
tcg_gen_add_i64(q0, q0, q1);
|
||||
tcg_gen_extu_i32_i64(q1, cpu_CF);
|
||||
tcg_gen_add_i64(q0, q0, q1);
|
||||
tcg_gen_extr_i64_i32(cpu_NF, cpu_CF, q0);
|
||||
}
|
||||
|
||||
tcg_gen_addcio_i32(cpu_NF, cpu_CF, t0, t1, cpu_CF);
|
||||
|
||||
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
|
||||
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0);
|
||||
tcg_gen_xor_i32(tmp, t0, t1);
|
||||
|
||||
+6
-11
@@ -1209,10 +1209,10 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 orig_in1,
|
||||
cb_msb = tcg_temp_new_i64();
|
||||
cb = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero);
|
||||
if (is_c) {
|
||||
tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb,
|
||||
get_psw_carry(ctx, d), ctx->zero);
|
||||
tcg_gen_addcio_i64(dest, cb_msb, in1, in2, get_psw_carry(ctx, d));
|
||||
} else {
|
||||
tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero);
|
||||
}
|
||||
tcg_gen_xor_i64(cb, in1, in2);
|
||||
tcg_gen_xor_i64(cb, cb, dest);
|
||||
@@ -1308,9 +1308,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1,
|
||||
if (is_b) {
|
||||
/* DEST,C = IN1 + ~IN2 + C. */
|
||||
tcg_gen_not_i64(cb, in2);
|
||||
tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero,
|
||||
get_psw_carry(ctx, d), ctx->zero);
|
||||
tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, ctx->zero);
|
||||
tcg_gen_addcio_i64(dest, cb_msb, in1, cb, get_psw_carry(ctx, d));
|
||||
tcg_gen_xor_i64(cb, cb, in1);
|
||||
tcg_gen_xor_i64(cb, cb, dest);
|
||||
} else {
|
||||
@@ -3008,9 +3006,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
|
||||
tcg_gen_xor_i64(add2, in2, addc);
|
||||
tcg_gen_andi_i64(addc, addc, 1);
|
||||
|
||||
tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, ctx->zero, add2, ctx->zero);
|
||||
tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb,
|
||||
addc, ctx->zero);
|
||||
tcg_gen_addcio_i64(dest, cpu_psw_cb_msb, add1, add2, addc);
|
||||
|
||||
/* Write back the result register. */
|
||||
save_gpr(ctx, a->t, dest);
|
||||
@@ -3553,8 +3549,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1,
|
||||
TCGv_i64 cb = tcg_temp_new_i64();
|
||||
TCGv_i64 cb_msb = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_movi_i64(cb_msb, 0);
|
||||
tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb);
|
||||
tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero);
|
||||
tcg_gen_xor_i64(cb, in1, in2);
|
||||
tcg_gen_xor_i64(cb, cb, dest);
|
||||
cb_cond = get_carry(ctx, d, cb, cb_msb);
|
||||
|
||||
@@ -19,16 +19,6 @@
|
||||
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Sometimes, knowing what the backend has can produce better code.
|
||||
* The exact opcode to check depends on 32- vs. 64-bit.
|
||||
*/
|
||||
#ifdef TARGET_X86_64
|
||||
#define INDEX_op_extract2_tl INDEX_op_extract2_i64
|
||||
#else
|
||||
#define INDEX_op_extract2_tl INDEX_op_extract2_i32
|
||||
#endif
|
||||
|
||||
#define MMX_OFFSET(reg) \
|
||||
({ assert((reg) >= 0 && (reg) <= 7); \
|
||||
offsetof(CPUX86State, fpregs[reg].mmx); })
|
||||
@@ -3023,7 +3013,7 @@ static void gen_PMOVMSKB(DisasContext *s, X86DecodedInsn *decode)
|
||||
tcg_gen_ld8u_tl(s->T0, tcg_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1)));
|
||||
while (vec_len > 8) {
|
||||
vec_len -= 8;
|
||||
if (tcg_op_supported(INDEX_op_extract2_tl, TCG_TYPE_TL, 0)) {
|
||||
if (tcg_op_supported(INDEX_op_extract2, TCG_TYPE_TL, 0)) {
|
||||
/*
|
||||
* Load the next byte of the result into the high byte of T.
|
||||
* TCG does a similar expansion of deposit to shl+extract2; by
|
||||
|
||||
@@ -311,11 +311,7 @@ static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
|
||||
/* Input and output carry. */
|
||||
static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
|
||||
{
|
||||
TCGv_i32 zero = tcg_constant_i32(0);
|
||||
TCGv_i32 tmp = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero);
|
||||
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
|
||||
tcg_gen_addcio_i32(out, cpu_msr_c, ina, inb, cpu_msr_c);
|
||||
}
|
||||
|
||||
/* Input carry, but no output carry. */
|
||||
@@ -544,12 +540,10 @@ static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
|
||||
/* Input and output carry. */
|
||||
static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
|
||||
{
|
||||
TCGv_i32 zero = tcg_constant_i32(0);
|
||||
TCGv_i32 tmp = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_not_i32(tmp, ina);
|
||||
tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero);
|
||||
tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero);
|
||||
tcg_gen_addcio_i32(out, cpu_msr_c, tmp, inb, cpu_msr_c);
|
||||
}
|
||||
|
||||
/* No input or output carry. */
|
||||
|
||||
@@ -221,8 +221,7 @@ static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
|
||||
TCGv t0 = tcg_temp_new();
|
||||
TCGv res = tcg_temp_new();
|
||||
|
||||
tcg_gen_add2_tl(res, cpu_sr_cy, srca, dc->zero, cpu_sr_cy, dc->zero);
|
||||
tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, dc->zero);
|
||||
tcg_gen_addcio_tl(res, cpu_sr_cy, srca, srcb, cpu_sr_cy);
|
||||
tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
|
||||
tcg_gen_xor_tl(t0, res, srcb);
|
||||
tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
|
||||
|
||||
@@ -1746,11 +1746,10 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
|
||||
tcg_gen_mov_tl(ca32, ca);
|
||||
}
|
||||
} else {
|
||||
TCGv zero = tcg_constant_tl(0);
|
||||
if (add_ca) {
|
||||
tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero);
|
||||
tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero);
|
||||
tcg_gen_addcio_tl(t0, ca, arg1, arg2, ca);
|
||||
} else {
|
||||
TCGv zero = tcg_constant_tl(0);
|
||||
tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero);
|
||||
}
|
||||
gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0);
|
||||
@@ -1949,11 +1948,9 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
|
||||
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
|
||||
}
|
||||
} else if (add_ca) {
|
||||
TCGv zero, inv1 = tcg_temp_new();
|
||||
TCGv inv1 = tcg_temp_new();
|
||||
tcg_gen_not_tl(inv1, arg1);
|
||||
zero = tcg_constant_tl(0);
|
||||
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
|
||||
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
|
||||
tcg_gen_addcio_tl(t0, cpu_ca, arg2, inv1, cpu_ca);
|
||||
gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0);
|
||||
} else {
|
||||
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
|
||||
|
||||
@@ -1250,11 +1250,7 @@ static DisasJumpType op_addc32(DisasContext *s, DisasOps *o)
|
||||
static DisasJumpType op_addc64(DisasContext *s, DisasOps *o)
|
||||
{
|
||||
compute_carry(s);
|
||||
|
||||
TCGv_i64 zero = tcg_constant_i64(0);
|
||||
tcg_gen_add2_i64(o->out, cc_src, o->in1, zero, cc_src, zero);
|
||||
tcg_gen_add2_i64(o->out, cc_src, o->out, cc_src, o->in2, zero);
|
||||
|
||||
tcg_gen_addcio_i64(o->out, cc_src, o->in1, o->in2, cc_src);
|
||||
return DISAS_NEXT;
|
||||
}
|
||||
|
||||
|
||||
+15
-21
@@ -695,14 +695,8 @@ static void _decode_opc(DisasContext * ctx)
|
||||
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
|
||||
return;
|
||||
case 0x300e: /* addc Rm,Rn */
|
||||
{
|
||||
TCGv t0, t1;
|
||||
t0 = tcg_constant_tl(0);
|
||||
t1 = tcg_temp_new();
|
||||
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
|
||||
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
|
||||
REG(B11_8), t0, t1, cpu_sr_t);
|
||||
}
|
||||
tcg_gen_addcio_i32(REG(B11_8), cpu_sr_t,
|
||||
REG(B11_8), REG(B7_4), cpu_sr_t);
|
||||
return;
|
||||
case 0x300f: /* addv Rm,Rn */
|
||||
{
|
||||
@@ -1940,16 +1934,16 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
NEXT_INSN;
|
||||
switch (ctx->opcode & 0xf00f) {
|
||||
case 0x300c: /* add Rm,Rn */
|
||||
op_opc = INDEX_op_add_i32;
|
||||
op_opc = INDEX_op_add;
|
||||
goto do_reg_op;
|
||||
case 0x2009: /* and Rm,Rn */
|
||||
op_opc = INDEX_op_and_i32;
|
||||
op_opc = INDEX_op_and;
|
||||
goto do_reg_op;
|
||||
case 0x200a: /* xor Rm,Rn */
|
||||
op_opc = INDEX_op_xor_i32;
|
||||
op_opc = INDEX_op_xor;
|
||||
goto do_reg_op;
|
||||
case 0x200b: /* or Rm,Rn */
|
||||
op_opc = INDEX_op_or_i32;
|
||||
op_opc = INDEX_op_or;
|
||||
do_reg_op:
|
||||
/* The operation register should be as expected, and the
|
||||
other input cannot depend on the load. */
|
||||
@@ -1976,7 +1970,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
goto fail;
|
||||
}
|
||||
op_dst = B11_8;
|
||||
op_opc = INDEX_op_xor_i32;
|
||||
op_opc = INDEX_op_xor;
|
||||
op_arg = tcg_constant_i32(-1);
|
||||
break;
|
||||
|
||||
@@ -1984,7 +1978,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
if (op_dst != B11_8 || mv_src >= 0) {
|
||||
goto fail;
|
||||
}
|
||||
op_opc = INDEX_op_add_i32;
|
||||
op_opc = INDEX_op_add;
|
||||
op_arg = tcg_constant_i32(B7_0s);
|
||||
break;
|
||||
|
||||
@@ -1995,7 +1989,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
if ((ld_dst == B11_8) + (ld_dst == B7_4) != 1 || mv_src >= 0) {
|
||||
goto fail;
|
||||
}
|
||||
op_opc = INDEX_op_setcond_i32; /* placeholder */
|
||||
op_opc = INDEX_op_setcond; /* placeholder */
|
||||
op_src = (ld_dst == B11_8 ? B7_4 : B11_8);
|
||||
op_arg = REG(op_src);
|
||||
|
||||
@@ -2030,7 +2024,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
if (ld_dst != B11_8 || ld_dst != B7_4 || mv_src >= 0) {
|
||||
goto fail;
|
||||
}
|
||||
op_opc = INDEX_op_setcond_i32;
|
||||
op_opc = INDEX_op_setcond;
|
||||
op_arg = tcg_constant_i32(0);
|
||||
|
||||
NEXT_INSN;
|
||||
@@ -2087,7 +2081,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
ctx->memidx, ld_mop);
|
||||
break;
|
||||
|
||||
case INDEX_op_add_i32:
|
||||
case INDEX_op_add:
|
||||
if (op_dst != st_src) {
|
||||
goto fail;
|
||||
}
|
||||
@@ -2105,7 +2099,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
}
|
||||
break;
|
||||
|
||||
case INDEX_op_and_i32:
|
||||
case INDEX_op_and:
|
||||
if (op_dst != st_src) {
|
||||
goto fail;
|
||||
}
|
||||
@@ -2119,7 +2113,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
}
|
||||
break;
|
||||
|
||||
case INDEX_op_or_i32:
|
||||
case INDEX_op_or:
|
||||
if (op_dst != st_src) {
|
||||
goto fail;
|
||||
}
|
||||
@@ -2133,7 +2127,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
}
|
||||
break;
|
||||
|
||||
case INDEX_op_xor_i32:
|
||||
case INDEX_op_xor:
|
||||
if (op_dst != st_src) {
|
||||
goto fail;
|
||||
}
|
||||
@@ -2147,7 +2141,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
|
||||
}
|
||||
break;
|
||||
|
||||
case INDEX_op_setcond_i32:
|
||||
case INDEX_op_setcond:
|
||||
if (st_src == ld_dst) {
|
||||
goto fail;
|
||||
}
|
||||
|
||||
@@ -396,8 +396,7 @@ static void gen_op_addcc_int(TCGv dst, TCGv src1, TCGv src2, TCGv cin)
|
||||
TCGv z = tcg_constant_tl(0);
|
||||
|
||||
if (cin) {
|
||||
tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, src1, z, cin, z);
|
||||
tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, cpu_cc_N, cpu_cc_C, src2, z);
|
||||
tcg_gen_addcio_tl(cpu_cc_N, cpu_cc_C, src1, src2, cin);
|
||||
} else {
|
||||
tcg_gen_add2_tl(cpu_cc_N, cpu_cc_C, src1, z, src2, z);
|
||||
}
|
||||
|
||||
@@ -1346,15 +1346,11 @@ static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
|
||||
|
||||
static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
|
||||
{
|
||||
TCGv carry = tcg_temp_new_i32();
|
||||
TCGv t0 = tcg_temp_new_i32();
|
||||
TCGv t0 = tcg_temp_new_i32();
|
||||
TCGv result = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_movi_tl(t0, 0);
|
||||
tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
|
||||
/* Addition, carry and set C/V/SV bits */
|
||||
tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
|
||||
tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
|
||||
tcg_gen_addcio_i32(result, cpu_PSW_C, r1, r2, cpu_PSW_C);
|
||||
/* calc V bit */
|
||||
tcg_gen_xor_tl(cpu_PSW_V, result, r1);
|
||||
tcg_gen_xor_tl(t0, r1, r2);
|
||||
@@ -3981,7 +3977,7 @@ static void decode_bit_andacc(DisasContext *ctx)
|
||||
pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
|
||||
break;
|
||||
case OPC2_32_BIT_AND_NOR_T:
|
||||
if (tcg_op_supported(INDEX_op_andc_i32, TCG_TYPE_I32, 0)) {
|
||||
if (tcg_op_supported(INDEX_op_andc, TCG_TYPE_I32, 0)) {
|
||||
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
|
||||
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
|
||||
} else {
|
||||
@@ -4114,7 +4110,7 @@ static void decode_bit_orand(DisasContext *ctx)
|
||||
pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
|
||||
break;
|
||||
case OPC2_32_BIT_OR_NOR_T:
|
||||
if (tcg_op_supported(INDEX_op_orc_i32, TCG_TYPE_I32, 0)) {
|
||||
if (tcg_op_supported(INDEX_op_orc, TCG_TYPE_I32, 0)) {
|
||||
gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
|
||||
pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
|
||||
} else {
|
||||
|
||||
@@ -18,14 +18,16 @@ C_O1_I1(r, r)
|
||||
C_O1_I1(w, r)
|
||||
C_O1_I1(w, w)
|
||||
C_O1_I1(w, wr)
|
||||
C_O1_I2(r, 0, rz)
|
||||
C_O1_I2(r, r, r)
|
||||
C_O1_I2(r, r, rA)
|
||||
C_O1_I2(r, r, rAL)
|
||||
C_O1_I2(r, r, rC)
|
||||
C_O1_I2(r, r, ri)
|
||||
C_O1_I2(r, r, rL)
|
||||
C_O1_I2(r, rZ, rA)
|
||||
C_O1_I2(r, rz, rMZ)
|
||||
C_O1_I2(r, rz, rz)
|
||||
C_O1_I2(r, rZ, rZ)
|
||||
C_O1_I2(w, 0, w)
|
||||
C_O1_I2(w, w, w)
|
||||
C_O1_I2(w, w, wN)
|
||||
@@ -34,4 +36,3 @@ C_O1_I2(w, w, wZ)
|
||||
C_O1_I3(w, w, w, w)
|
||||
C_O1_I4(r, r, rC, rz, rz)
|
||||
C_O2_I1(r, r, r)
|
||||
C_O2_I4(r, r, rz, rz, rA, rMZ)
|
||||
|
||||
@@ -13,64 +13,7 @@
|
||||
#define have_lse2 (cpuinfo & CPUINFO_LSE2)
|
||||
|
||||
/* optional instructions */
|
||||
#define TCG_TARGET_HAS_div_i32 1
|
||||
#define TCG_TARGET_HAS_rem_i32 1
|
||||
#define TCG_TARGET_HAS_ext8s_i32 1
|
||||
#define TCG_TARGET_HAS_ext16s_i32 1
|
||||
#define TCG_TARGET_HAS_ext8u_i32 1
|
||||
#define TCG_TARGET_HAS_ext16u_i32 1
|
||||
#define TCG_TARGET_HAS_bswap16_i32 1
|
||||
#define TCG_TARGET_HAS_bswap32_i32 1
|
||||
#define TCG_TARGET_HAS_not_i32 1
|
||||
#define TCG_TARGET_HAS_rot_i32 1
|
||||
#define TCG_TARGET_HAS_andc_i32 1
|
||||
#define TCG_TARGET_HAS_orc_i32 1
|
||||
#define TCG_TARGET_HAS_eqv_i32 1
|
||||
#define TCG_TARGET_HAS_nand_i32 0
|
||||
#define TCG_TARGET_HAS_nor_i32 0
|
||||
#define TCG_TARGET_HAS_clz_i32 1
|
||||
#define TCG_TARGET_HAS_ctz_i32 1
|
||||
#define TCG_TARGET_HAS_ctpop_i32 0
|
||||
#define TCG_TARGET_HAS_extract2_i32 1
|
||||
#define TCG_TARGET_HAS_negsetcond_i32 1
|
||||
#define TCG_TARGET_HAS_add2_i32 1
|
||||
#define TCG_TARGET_HAS_sub2_i32 1
|
||||
#define TCG_TARGET_HAS_mulu2_i32 0
|
||||
#define TCG_TARGET_HAS_muls2_i32 0
|
||||
#define TCG_TARGET_HAS_muluh_i32 0
|
||||
#define TCG_TARGET_HAS_mulsh_i32 0
|
||||
#define TCG_TARGET_HAS_extr_i64_i32 0
|
||||
#define TCG_TARGET_HAS_qemu_st8_i32 0
|
||||
|
||||
#define TCG_TARGET_HAS_div_i64 1
|
||||
#define TCG_TARGET_HAS_rem_i64 1
|
||||
#define TCG_TARGET_HAS_ext8s_i64 1
|
||||
#define TCG_TARGET_HAS_ext16s_i64 1
|
||||
#define TCG_TARGET_HAS_ext32s_i64 1
|
||||
#define TCG_TARGET_HAS_ext8u_i64 1
|
||||
#define TCG_TARGET_HAS_ext16u_i64 1
|
||||
#define TCG_TARGET_HAS_ext32u_i64 1
|
||||
#define TCG_TARGET_HAS_bswap16_i64 1
|
||||
#define TCG_TARGET_HAS_bswap32_i64 1
|
||||
#define TCG_TARGET_HAS_bswap64_i64 1
|
||||
#define TCG_TARGET_HAS_not_i64 1
|
||||
#define TCG_TARGET_HAS_rot_i64 1
|
||||
#define TCG_TARGET_HAS_andc_i64 1
|
||||
#define TCG_TARGET_HAS_orc_i64 1
|
||||
#define TCG_TARGET_HAS_eqv_i64 1
|
||||
#define TCG_TARGET_HAS_nand_i64 0
|
||||
#define TCG_TARGET_HAS_nor_i64 0
|
||||
#define TCG_TARGET_HAS_clz_i64 1
|
||||
#define TCG_TARGET_HAS_ctz_i64 1
|
||||
#define TCG_TARGET_HAS_ctpop_i64 0
|
||||
#define TCG_TARGET_HAS_extract2_i64 1
|
||||
#define TCG_TARGET_HAS_negsetcond_i64 1
|
||||
#define TCG_TARGET_HAS_add2_i64 1
|
||||
#define TCG_TARGET_HAS_sub2_i64 1
|
||||
#define TCG_TARGET_HAS_mulu2_i64 0
|
||||
#define TCG_TARGET_HAS_muls2_i64 0
|
||||
#define TCG_TARGET_HAS_muluh_i64 1
|
||||
#define TCG_TARGET_HAS_mulsh_i64 1
|
||||
|
||||
/*
|
||||
* Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load,
|
||||
|
||||
+935
-691
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user